Optoelectronic detector chip based on a highly reliable misaligned electrode structure and manufacturing method thereof

Abstract

The present invention relates to a photodetector chip based on a highly reliable misaligned electrode structure and a manufacturing method thereof. Coplanar P and N metal electrodes are fabricated through an epitaxial wafer with a PIN-type double heterojunction structure and a double n-type heteroconductance layer structure. An antireflection film is grown in the light incident hole, and a photosensitive polymer material is filled to form a flat back surface of the chip. Finally, the wafer is cleaved to form unit chips. In the present invention, the double heterojunction structure enables bidirectional high-precision control and low-damage processes during N electrode contact hole etching and InP substrate removal; the misaligned electrode structure reduces the thickness of the n-type InP conductance layer and improves the device's response to visible light; the double-sided lithography technology is used to selectively and locally remove the InP substrate to fabricate the light incident hole, realizing wafer-level batch processing; the use of a polymer material transparent to visible light to fill the light incident hole provides mechanical support for the active region and improves the chip reliability.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor photodetectors, and relates to a photodetector chip based on a highly reliable misaligned electrode structure and a manufacturing method thereof. Background Art

[0002] Standard InP / In 0.53 Ga 0.47 The response band of an As short-wave infrared detector is 0.87μm - 1.7μm. By means of material optimization design and substrate removal process, the response band can be extended to the visible light, realizing wide-spectrum + composite information detection including visible light and short-wave bands, thereby significantly improving the information amount and recognition rate of the detection target. It has important significance in military and civilian fields such as reconnaissance and recognition, low-light night vision, optoelectronic countermeasure, fire prevention and fire fighting, industrial detection, machine vision, and biomedicine.

[0003] The difficulty of the existing substrate removal process lies in that the finished surface after the chip substrate removal process must have a high degree of consistency and avoid direct damage or mechanical stress damage to the active region; meanwhile, InP and In 0.53 Ga 0.47 As are lattice-matched, and a certain thickness of InP layer (InP substrate and InP conductivity layer) needs to be retained as a surface passivation layer and cathode contact. In order to reduce the absorption of visible light by the InP layer, the thickness of this layer is generally designed to be 100nm or less, which requires the control accuracy and consistency of the corrosion depth of the N electrode lead-out hole to reach the 50nm level, and the process difficulty is extremely high.

[0004] In addition, the detector chip after substrate removal usually only remains several microns thick, and is extremely easy to break due to the lack of mechanical support of the substrate, which is not conducive to the reliability of the device; meanwhile, due to its fragility, the chip must be vertically flip-chip interconnected to the substrate and then the substrate removal process is carried out, and this process can only be completed piece by piece, which is not conducive to mass production. Summary of the Invention

[0005] Aiming at the deficiencies of the above-mentioned existing technologies, the technical problem to be solved by the present invention is: to provide a photodetector chip based on a highly reliable misaligned electrode structure and a manufacturing method thereof that are convenient for wafer-level mass production.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A manufacturing method of a photodetector chip based on a highly reliable misaligned electrode structure, comprising the following steps:

[0008] S100. Grow an epitaxial wafer based on a PIN-type double heterojunction structure and a double n-type heteroconductivity layer structure;

[0009] S200. Define an active region on the epitaxial wafer and perform P-type doping in the active region to form a P-type doped region;

[0010] S300. Define an N-electrode window around the active region and fabricate an N-electrode contact hole in the N-electrode window using a wet etching process;

[0011] S400. Lead out a P-metal electrode from the active region and an N-metal electrode from the N-electrode contact hole, and the P-metal electrode and the N-metal electrode are coplanar;

[0012] S500. Thin the InP substrate of the epitaxial wafer to a predetermined thickness;

[0013] S600. Define a light incident window and fabricate a light incident hole in the light incident window using a wet etching process;

[0014] S700. Grow an antireflection film in the light incident hole and fill it with a photosensitive polymer material to form a flat back surface of the chip;

[0015] S800. Cleave the wafer to form unit chips.

[0016] Further, the S100 step includes the following sub-steps:

[0017] S110. Grow an n-type dislocation conductance layer on the n-type indium phosphide substrate, with a growth thickness of 0.2 μm to 1 μm and a doping concentration of 2×10 18 cm -3 ~5×10 18 cm -3 ;

[0018] S120. Grow an n-type indium phosphide conductance layer on the n-type dislocation conductance layer, with a growth thickness of 0.05 μm to 0.2 μm and a doping concentration of 2×10 18 cm -3 ~5×10 18 cm -3 ;

[0019] S130. Grow an n-type indium phosphide buffer layer on the n-type indium phosphide conductance layer, with a growth thickness of 0.05 μm to 0.2 μm and a doping concentration less than or equal to 2×10 15 cm -3 ;

[0020] S140. Grow an undoped indium gallium arsenide absorption layer on the n-type indium phosphide buffer layer, with a growth thickness of 1 μm to 5 μm;

[0021] S150. Grow an n-type indium phosphide cap layer on the absorption layer, with a growth thickness of 0.1 μm to 1 μm and a doping concentration less than or equal to 5×10 16 cm-3 ;

[0022] S160. Grow an n-type indium gallium arsenide contact layer on the cap layer, with a growth thickness of 0.05 to 0.5 microns and a doping concentration less than or equal to 5×10 16 cm -3 .

[0023] Furthermore, the n-type dislocation conductance layer is an InAlAs conductance layer, an InGaAlAs conductance layer, an InGaAsP conductance layer, or an InGaAs conductance layer.

[0024] Furthermore, the S200 step includes the following sub-steps:

[0025] S210. Grow a silicon oxide thin film on the surface of the epitaxial wafer as a doping barrier dielectric film, with a growth thickness of 50 nm to 300 nm;

[0026] S220. Define an active region window on the doping barrier dielectric film by means of photolithographic exposure;

[0027] S230. Perform p-type doping on the active region with a dimethylzinc source to form a P-type doping region.

[0028] Furthermore, the S300 step includes the following sub-steps:

[0029] S310. Define an N electrode contact window around the active region by means of photolithographic exposure;

[0030] S320. Alternately use a first material selective etching solution and a second material selective etching solution to wet-etch and remove the indium gallium arsenide contact layer, indium phosphide cap layer, indium gallium arsenide absorption layer, indium phosphide buffer layer, and indium phosphide conductance layer in sequence to form an N electrode contact hole.

[0031] Furthermore, the S400 step includes the following sub-steps:

[0032] S410. Define a P electrode lift-off film hole above the active region by means of photolithographic exposure;

[0033] S420. Define an N electrode lift-off film hole in the N contact hole and adjacent areas;

[0034] S430. Evaporate a metal film on the surface of the epitaxial layer, with a thickness of 0.2 to 1.0 microns;

[0035] S440. Lift off the metal film outside the P electrode lift-off film hole and the N electrode lift-off film hole to obtain a P metal electrode and an N metal electrode.

[0036] Furthermore, the S600 step includes the following sub-steps:

[0037] S610. Grow a silicon oxide thin film on the surface of the epitaxial wafer as a substrate to selectively remove the barrier dielectric film, with a growth thickness of 50 nm to 300 nm;

[0038] S620. Define a light incident window, and its area is the vertical projection area of the active region on the back polished surface;

[0039] S630. Alternately use the second material selective etchant and the first material selective etchant to wet-etch and remove the InP substrate and the n-type dislocation conductance layer of the light incident window in sequence to form a light incident hole.

[0040] Furthermore, the first material selective etchant is a mixed solution of citric acid, hydrogen peroxide, and deionized water; the second material selective etchant is a mixed solution of glacial acetic acid, phosphoric acid, hydrochloric acid, and deionized water.

[0041] Furthermore, the step S700 includes the following sub-steps:

[0042] S710. Fabricate a wide-spectrum antireflection film of titanium oxide and silicon oxide with a thickness of 200 nm to 300 nm;

[0043] S720. Fill the light incident hole by spin-coating a photosensitive polymer material;

[0044] S730. Use photolithography technology to selectively remove the photosensitive polymer material in the non-light incident window area to obtain a flat back surface of the chip.

[0045] A photodetector chip is fabricated by using the manufacturing method of a photodetector chip based on a highly reliable dislocation electrode structure.

[0046] In the present invention, the structure of a double heterojunction is adopted to facilitate the formation of an etching stop layer, and bidirectional high-precision control and low-damage processes can be achieved during the etching of the N electrode contact hole and the removal of the InP substrate through wet etching; the dislocation electrode structure is adopted to reduce the thickness of the n-type InP conductance layer and improve the responsivity of the device to visible light; a photosensitive polymer material is used to fill the light incident hole to provide mechanical support for the active region and improve the reliability of the chip; a double-sided photolithography technology is used to selectively and locally remove the InP substrate, and the remaining part of the substrate provides support for the wafer to achieve wafer-level batch processing. Description of the Drawings

[0047] The drawings described herein are used to provide a further understanding of the present application, form a part of the present application, and the schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0048] Figure 1This is a flowchart of a preferred embodiment of the method for fabricating a photodetector chip based on a highly reliable misaligned electrode structure according to the present invention.

[0049] Figure 2 FIG. is a schematic structural diagram of an epitaxial wafer.

[0050] Figure 3 FIG. is a schematic structural diagram after forming a P-type doped region.

[0051] Figure 4 FIG. is a schematic structural diagram after forming a P-metal electrode and an N-metal electrode.

[0052] Figure 5 FIG. is a schematic structural diagram after forming a light incident hole.

[0053] Figure 6 FIG. is a schematic structural diagram of a photodetector chip.

[0054] The meanings of the reference numerals in the drawings are as follows:

[0055] Substrate: 1; InAlAs conductance layer: 2; n-InP conductance layer: 3; n-InP buffer layer: 4; i-InGaAs absorption layer: 5; n-InP cap layer: 6; n-InGaAs contact layer: 7; Doping blocking dielectric film: 8; Substrate selective removal blocking dielectric film: 9; Active region: 11; P-type doped region: 12; P-metal electrode: 13; N-electrode contact hole: 21; N-metal electrode: 22; Light incident hole: 31; Antireflection film: 32; Polymer material - 33. Detailed implementation manners

[0056] The following specifically illustrates the implementation manners of the present invention through specific examples. The diagrams provided in the following examples only schematically illustrate the basic concept of the present invention. Without conflict, the following examples and the features in the examples can be combined with each other.

[0057] As Figure 1 shown, a preferred embodiment of the method for fabricating a photodetector chip based on a highly reliable misaligned electrode structure according to the present invention includes the following steps:

[0058] S100. As Figure 2 shown, grow an epitaxial wafer based on a PIN-type double heterojunction structure and a double n-type heteroconductance layer structure by using the method of metal organic chemical vapor deposition (MOCVD). Specifically, it may include the following sub-steps:

[0059] S110. Grow an n-type misaligned conductance layer on an n-type indium phosphide (n + -InP) substrate 1, with a growth thickness of 0.2 micrometers to 1 micrometer and a doping concentration of 2×10 18 cm -3 ~5×1018 cm -3 In this embodiment, the n-type staggered conductance layer is the InAlAs conductance layer 2. Of course, the n-type staggered conductance layer can also be an InGaAlAs conductance layer, an InGaAsP conductance layer, or an InGaAs conductance layer.

[0060] S120. Grow an n-type indium phosphide (n-InP) conductance layer 3 on the InAlAs conductance layer 2, with a growth thickness of 0.05 μm to 0.2 μm and a doping concentration of 2×10 18 cm -3 ~5×10 18 cm -3 .

[0061] S130. Grow an n-type indium phosphide (n-InP) buffer layer 4 on the n-InP conductance layer 3, with a growth thickness of 0.05 μm to 0.2 μm and a doping concentration not greater than 2×10 15 cm -3 .

[0062] S140. Grow an undoped indium gallium arsenide (i-InGaAs) absorption layer 5 on the n-InP buffer layer 4, with a growth thickness of 1 μm to 5 μm.

[0063] S150. Grow an n-type indium phosphide (n-InP) cap layer 6 on the i-InGaAs absorption layer 5, with a growth thickness of 0.1 μm to 1 μm and a doping concentration not greater than 5×10 16 cm -3 .

[0064] S160. Grow an n-type indium gallium arsenide (n-InGaAs) contact layer 7 on the n-InP cap layer 6, with a growth thickness of 0.05 μm to 0.5 μm and a doping concentration not greater than 5×1016 cm-3.

[0065] S200. As Figure 3 shown, following the InGaAs photodetector fabrication process, define the active region 11 on the epitaxial wafer and perform P-type doping in the active region 11 to form the P-type doped region 12. Specifically, it can include the following sub-steps:

[0066] S210. Use plasma-enhanced chemical vapor deposition (PECVD) equipment to grow a silicon dioxide (SiO2) thin film as a doping barrier dielectric film 8 on the surface of the epitaxial wafer, with a growth thickness of 50 nm to 300 nm.

[0067] S220. Use photolithography and exposure to define the window of the active region 11 on the doping barrier dielectric film 8.

[0068] S230. P-type doping of the active region 11 is performed using a dimethylzinc source to form a P-type doped region 12.

[0069] S300. An N electrode window is defined around the active region 11, and an N electrode contact hole 21 is fabricated in the N electrode window using a wet etching process. Specifically, it may include the following sub-steps:

[0070] S310. The N electrode contact window is defined around the active region 11 by means of photolithographic exposure.

[0071] S320. As Figure 4 shown, using a wet etching process, the first material selective etching solution and the second material selective etching solution are alternately used to sequentially remove the n-InGaAs contact layer 7, the n-InP cap layer 6, the i-InGaAs absorption layer 5, the n-InP buffer layer 4, and the n-InP conductance layer 3 to form the N electrode contact hole 21. The first material selective etching solution is an InGa(Al)As(P)-based material selective etching solution, and the second material selective etching solution is an InP-based material selective etching solution, so that the etching depth can be precisely controlled to above the InAlAs conductance layer 2 by virtue of the selective etching characteristics. Among them, the InGa(Al)As(P)-based material selective etching solution may be a mixed solution of citric acid (C6H8O7), hydrogen peroxide (H2O2), and deionized water (H2O). The InP-based material selective etching solution may be a mixed solution of glacial acetic acid (CH3COOH), phosphoric acid (H3PO4), hydrochloric acid (HCl), and deionized water (H2O).

[0072] S400. Please continue to refer to Figure 4 , and the P metal electrode 13 and the N metal electrode 22 are fabricated using the lift off process. The P metal electrode 13 is led out from the active region 11, and the N metal electrode 22 is led out from the N electrode contact hole 21. The P metal electrode 13 and the N metal electrode 22 are on the same plane. Specifically, it may include the following sub-steps:

[0073] S410. The P electrode lift-off photoresist film hole is defined above the active region 11 by means of photolithographic exposure.

[0074] S420. The N electrode lift-off photoresist film hole is defined in the N contact hole and the adjacent area.

[0075] S430. A Ti / Pt / Au metal film with a thickness of 0.2 micrometers to 1.0 micrometers is evaporated on the surface of the epitaxial layer using a metal evaporation process.

[0076] S440. The metal film outside the P electrode lift-off photoresist film hole and the N electrode lift-off photoresist film hole is peeled off to obtain the P metal electrode 13 and the N metal electrode 22.

[0077] S500. AsFigure 5 As shown, the InP substrate 1 on the back side of the wafer is thinned to a predetermined thickness by combining mechanical polishing and chemical polishing; the remaining thickness of the InP substrate 1 after thinning is generally 50 μm to 100 μm.

[0078] S600. Please continue to refer to Figure 5 , define a light incident window on the back side of the wafer, and fabricate a light incident hole 31 by using a wet etching process in the light incident window. Specifically, it may include the following sub-steps:

[0079] S610. Use a plasma enhanced chemical vapor deposition (PECVD) device to grow a silicon dioxide (SiO2) thin film on the back side of the wafer as a substrate selective removal barrier medium film 9, and its growth thickness is 50 nm to 300 nm.

[0080] S620. Use a double-sided lithography technique to define a light incident window on the back side of the wafer, and its area is the vertical projection area of the active region 11 on the back side of the wafer.

[0081] S630. Use a wet etching process, alternately use an InP-based material selective etching solution and an InGa(Al)As(P)-based material selective etching solution to remove the InP substrate 1 and the InAlAs conductivity layer 2 in the light incident window in sequence, and form a light incident hole 31, so that the etching depth can be accurately controlled to n + -up to the upper side of the InP conductivity layer 3.

[0082] S700. As Figure 6 shown, grow an antireflection film 32 in the light incident hole 31, and fill it with a photosensitive polymer material 33 to form a flat back surface of the chip. Specifically, it may include the following sub-steps:

[0083] S710. Use a magnetron sputtering method to fabricate a titanium oxide and silicon dioxide broadband composite antireflection film 32, and its sputtering thickness is 200 nm to 300 nm.

[0084] S720. Fill the light incident hole 31 by spin-coating a photosensitive benzocyclobutene (BCB) material; of course, other photosensitive polymer materials 33 can also be used for filling.

[0085] S730. Use a lithography technique to selectively remove the BCB material in the non-light incident window area, so as to selectively fill the light incident window by using the lithography technique and obtain a flat back surface of the chip.

[0086] S800. Cleave the array chips on the wafer to form unit chips, and the production of the photodetector chips is completed.

[0087] In this embodiment, a double heterojunction InP / InGaAs / InP structure is adopted, which is convenient for forming an etching stop layer, so that bidirectional high-precision control and low-damage processes can be achieved during the wet etching of the N electrode contact hole 21 and the removal of the InP substrate 1. An InAlAs / InP double n-type heteroconductivity layer is used to form a misaligned electrode structure, reducing the thickness of the n-InP conductivity layer 3 and improving the device's responsivity to visible light. The photosensitive polymer material 33 is used to fill the light incident hole 31, which can provide mechanical support for the active region 11 and improve the reliability of the chip; and the double-sided photolithography technology is used to selectively and locally remove the InP substrate 1. The remaining part of the substrate 1 provides support for the wafer, and the wafer can be cleaved after the chip is fabricated, without first cleaving the wafer into individual chips and then removing the substrate 1 from the individual chips, realizing wafer-level batch processing.

[0088] The present invention also discloses a photodetector chip, which can be fabricated by using the method for fabricating a photodetector chip based on a highly reliable misaligned electrode structure disclosed in any one of the above embodiments.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the present technical solution, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A manufacturing method of a photodetector chip based on a highly reliable misaligned electrode structure, characterized in that It includes the following steps: S100. Grow an epitaxial wafer based on a PIN-type double heterojunction structure and a double n-type heteroconductance layer structure; S200. Define an active region on the epitaxial wafer and perform P-type doping in the active region to form a P-type doped region; S300. Define an N electrode window around the active region, and fabricate an N electrode contact hole by wet etching process in the N electrode window; S400. Lead out a P metal electrode from the active region and an N metal electrode from the N electrode contact hole, and the P metal electrode and the N metal electrode are coplanar; S500. Thin the InP substrate of the epitaxial wafer to a predetermined thickness; S600. Define a light incident window, and fabricate a light incident hole by wet etching process in the light incident window; S700. Grow an antireflection film in the light incident hole, and fill it with a photosensitive polymer material to form a flat back surface of the chip; S800. Cleave the wafer to form unit chips; The step S100 includes the following sub-steps: S110. Grow an n-type dislocation conductance layer on an n-type indium phosphide substrate; S120. Grow an n-type indium phosphide conductance layer on the n-type dislocation conductance layer; S130. Grow an n-type indium phosphide buffer layer on the n-type indium phosphide conductance layer; S140. Grow an undoped indium gallium arsenide absorption layer on the n-type indium phosphide buffer layer; S150. Grow an n-type indium phosphide cap layer on the absorption layer; S160. Grow an n-type indium gallium arsenide contact layer on the cap layer; The step S600 includes the following sub-steps: S610. Grow a silicon oxide film on the surface of the epitaxial wafer as a substrate selective removal barrier dielectric film; S620. Define a light incident window, and its area is the vertical projection area of the active region on the back polished surface; S630. Alternately use a second material selective etching solution and a first material selective etching solution to wet-etch and remove the InP substrate and the n-type dislocation conductance layer in the light incident window in sequence to form a light incident hole.

2. The method for fabricating a photodetector chip based on a highly reliable misaligned electrode structure according to claim 1, wherein: In the step S110, the growth thickness of the n-type dislocation conductance layer is 0.2 micrometers to 1 micrometer, and the doping concentration is 2×10 18 cm -3 ~5×10 18 cm -3 ; In the step S120, the growth thickness of the n-type indium phosphide conductivity layer is 0.05 micrometers to 0.2 micrometers, and the doping concentration is 2×10 18 cm -3 ~5×10 18 cm -3 ; In the step S130, the growth thickness of the n-type indium phosphide buffer layer is 0.05 micrometers to 0.2 micrometers, and the doping concentration is less than or equal to 2×10 15 cm -3 ; In the step S140, the growth thickness of the indium gallium arsenide absorption layer is 1 μm to 5 μm; In the step S150, the growth thickness of the n-type indium phosphide cap layer is 0.1 micrometer to 1 micrometer, and the doping concentration is less than or equal to 5×10 16 cm -3 ; In the step S160, the growth thickness of the n-type indium gallium arsenide contact layer is 0.05 to 0.5 microns, and the doping concentration is less than or equal to 5×10 16 cm -3 .

3. The method for fabricating a photodetector chip based on a highly reliable misaligned electrode structure according to claim 2, wherein: The n-type dislocation conductance layer is an InAlAs conductance layer, an InGaAlAs conductance layer, an InGaAsP conductance layer or an InGaAs conductance layer.

4. The manufacturing method of the photodetector chip based on the highly reliable misaligned electrode structure according to claim 1, wherein, The step S200 includes the following sub-steps: S210. Grow a silicon oxide film on the surface of the epitaxial wafer as a doping barrier dielectric film, and the growth thickness is 50 nm to 300 nm; S220. Define an active region window on the doping barrier dielectric film by photolithography exposure; S230. Perform p-type doping on the active region using a dimethylzinc source to form a P-type doped region.

5. The method for fabricating a photodetector chip based on a highly reliable misaligned electrode structure according to claim 2, wherein The step S300 includes the following sub-steps: S310. Define an N electrode contact window around the active region by photolithography exposure; S320. Alternately use a first material selective etching solution and a second material selective etching solution to wet-etch and remove the indium gallium arsenide contact layer, the indium phosphide cap layer, the indium gallium arsenide absorption layer, the indium phosphide buffer layer and the indium phosphide conductance layer in sequence to form an N electrode contact hole.

6. The manufacturing method of the photodetector chip based on the highly reliable misaligned electrode structure according to claim 5, wherein, The step S400 includes the following sub-steps: S410. Define the P - electrode stripping photoresist film holes above the active region by photolithographic exposure; S420. Define the N - electrode stripping photoresist film holes in the N - contact hole and adjacent areas; S430. Evaporate a metal film on the surface of the epitaxial layer, with a thickness of 0.2 μm to 1.0 μm; S440. Strip the metal film outside the P - electrode stripping photoresist film holes and N - electrode stripping photoresist film holes to obtain the P - metal electrode and N - metal electrode.

7. The method for fabricating a photodetector chip based on a highly reliable misaligned electrode structure according to claim 2, wherein: In the step S610, the growth thickness of the silicon oxide thin film is 50 nm to 300 nm.

8. The method for fabricating a photodetector chip based on a highly reliable misaligned electrode structure according to claim 5 or 7, characterized in that: The first material selective etching solution is a mixed solution of citric acid, hydrogen peroxide, and deionized water; the second material selective etching solution is a mixed solution of glacial acetic acid, phosphoric acid, hydrochloric acid, and deionized water.

9. The method for fabricating a photodetector chip based on a highly reliable misaligned electrode structure according to claim 8, characterized in that, The step S700 includes the following sub - steps: S710. Fabricate a titanium oxide and silicon oxide broadband anti - reflection composite film with a thickness of 200 nm to 300 nm; S720. Fill the light - incident holes by spin - coating a photosensitive polymer material; S730. Use photolithography technology to selectively remove the photosensitive polymer material in the non - light - incident window area to obtain a flat chip back surface.

10. A photodetector chip, characterized in that: It is fabricated by the method for manufacturing a photodetector chip based on a highly reliable misaligned electrode structure according to any one of claims 1 to 9.

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