Detection substrate and flat panel detector

Abstract

The present disclosure provides a kind of detection substrate, comprising: substrate, multiple detection pixel units arranged in array on substrate, detection pixel unit includes: thin film transistor and photoelectric conversion part on the side of thin film transistor away from substrate, photoelectric conversion part is provided with bias voltage line on the side away from substrate;Thin film transistor includes: active layer, first electrode and second electrode, first electrode and second electrode are electrically connected with active layer, and active layer includes channel region;The end of photoelectric conversion part close to substrate is electrically connected with second electrode, and the end of photoelectric conversion part away from substrate is electrically connected with corresponding bias voltage line;At least one layer of dielectric layer is arranged between photoelectric conversion part and bias voltage line, first via hole is formed on dielectric layer, and at least part of the orthographic projection of channel region on substrate is located in the orthographic projection of first via hole on substrate.The present disclosure also provides a kind of flat panel detector.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of photoelectric detection, and in particular to a detection substrate and a flat panel detector. BACKGROUND

[0002] With the continuous development of X-ray digital imaging technology, the X-ray flat panel detector (FPXD) can directly convert X-ray images into digital images, and has broad application prospects in the fields of medical treatment, security and protection, and industrial detection.

[0003] The X-ray flat panel detector includes a detection substrate, and the detection substrate includes a plurality of thin film transistors (TFT) and a plurality of PIN photodiodes. At present, the thin film transistor is mostly an amorphous silicon (a-Si) thin film transistor, but the carrier mobility of the amorphous silicon thin film transistor is low and cannot meet the requirements of a dynamic X-ray flat panel detector. The carrier mobility of an IGZO (Indium Gallium Zinc Oxide) thin film transistor is between 5 and 20, which can meet the requirements of the use scenarios.

[0004] However, IGZO is a metal oxide and is very sensitive to hydrogen atoms (H Plasma) with high reducibility. When related film layers (for example, a silicon nitride layer) and PIN photodiodes are manufactured, hydrogen atoms will diffuse to the IGZO thin film transistor; the penetration of excessive H atoms into the a-IGZO active layer will have a great influence on the characteristics of the TFT. Under x-ray irradiation, the hydrogen atoms in the IGZO will be converted into shallow donor states, and the increase in hydrogen shallow donors will cause the conductivity of the TFT device to rise, the leakage current to rise, and the TFT characteristic curve to be left biased, thereby making the stability of the TFT poor and further affecting the performance of the flat panel detector. SUMMARY

[0005] In a first aspect, the present disclosure provides a detection substrate, including: a substrate, a plurality of detection pixel units arranged in an array on the substrate, each detection pixel unit including: a thin film transistor and a photoelectric conversion unit located on a side of the thin film transistor away from the substrate, the photoelectric conversion unit being provided with a bias voltage line on a side away from the substrate.

[0006] The thin film transistor includes: an active layer, a first electrode, and a second electrode, the first electrode and the second electrode are both electrically connected to the active layer, and the active layer includes a channel region.

[0007] The photoelectric conversion part is electrically connected to the second electrode at one end close to the substrate substrate, and is electrically connected to the corresponding bias voltage line at one end away from the substrate substrate.

[0008] At least one dielectric layer is arranged between the photoelectric conversion part and the bias voltage line, and a first via hole is formed on the dielectric layer. At least part of the channel region on the substrate substrate is located within the projection of the first via hole on the substrate substrate.

[0009] In some embodiments, the projection of the channel region on the substrate substrate is located within the projection of the first via hole on the substrate substrate.

[0010] In some embodiments, the at least one dielectric layer includes a second organic layer.

[0011] In some embodiments, the at least one dielectric layer further includes:

[0012] A buffer layer is located between the second organic layer and the photoelectric conversion part.

[0013] And / or, a fourth passivation layer is located between the second organic layer and the bias voltage line.

[0014] In some embodiments, a third via hole is formed on the dielectric layer and communicates with one end of the photoelectric conversion part away from the substrate substrate. The bias voltage line is in contact with one end of the corresponding photoelectric conversion part away from the substrate substrate through the corresponding third via hole.

[0015] In some embodiments, the projection of the channel region on the substrate substrate does not overlap with the projection of the photoelectric conversion part on the substrate substrate.

[0016] In some embodiments, the photoelectric conversion part includes a reading electrode and a photoelectric conversion structure, the photoelectric conversion structure is located on the side of the reading electrode away from the substrate substrate, and the material of the reading electrode includes a metal material.

[0017] The projection of the layer structure where the reading electrode is located on the substrate substrate does not overlap with the projection of the channel region on the substrate substrate.

[0018] In some embodiments, the projection of the channel region on the substrate substrate is located within the projection of the bias voltage line on the substrate substrate, and the material of the bias voltage line includes a metal material.

[0019] In some embodiments, the projection of the channel region on the substrate substrate is located within the projection of the photoelectric conversion part on the substrate substrate.

[0020] In some embodiments, the first via and the third via are the same via.

[0021] In some embodiments, the material of the bias voltage line comprises a transparent conductive material.

[0022] In some embodiments, the detection pixel unit further comprises:

[0023] a sacrificial layer between the thin film transistor and the photoelectric conversion part, the material of the sacrificial layer comprising an oxide;

[0024] At least part of the orthographic projection of the channel region on the substrate substrate is within the orthographic projection of the sacrificial layer on the substrate substrate.

[0025] In some embodiments, the sacrificial layer and the photoelectric conversion part are in contact at one end close to the substrate substrate, and the sacrificial layers in different detection pixel units are insulated from each other.

[0026] In some embodiments, the orthographic projection of the channel region on the substrate substrate and the orthographic projection of the photoelectric conversion part on the substrate substrate do not overlap;

[0027] A third passivation layer is provided between the sacrificial layer and the bias voltage line;

[0028] The orthographic projection of the first via on the substrate substrate is within the orthographic projection of the third passivation layer on the substrate substrate.

[0029] In some embodiments, the at least one dielectric layer comprises the second organic layer, a buffer layer and a fourth passivation layer;

[0030] The compactness of the third passivation layer is less than the compactness of the buffer layer, and the compactness of the third passivation layer is less than the compactness of the fourth passivation layer.

[0031] In some embodiments, the material of the third passivation layer comprises silicon oxide, the material of the buffer layer comprises silicon nitride, and the material of the fourth passivation layer comprises silicon nitride.

[0032] In some embodiments, a first passivation layer, a first organic layer and a second passivation layer are further provided between the thin film transistor and the photoelectric conversion part, the first organic layer is located on the side of the first passivation layer away from the substrate substrate, and the second passivation layer is located on the side of the first organic layer away from the substrate substrate;

[0033] The sacrificial layer is located between the second passivation layer and the photoelectric conversion part.

[0034] In some embodiments, a second via hole is formed on the first passivation layer, the first organic layer, and the second passivation layer, and is connected to the second electrode.

[0035] The photoelectric conversion unit includes a reading electrode and a photoelectric conversion structure, and the photoelectric conversion structure is located on the side of the reading electrode away from the substrate.

[0036] The reading electrode is in contact with the second electrode through the second via hole, and the sacrificial layer is not in contact with the second electrode.

[0037] In some embodiments, the orthographic projection of the sacrificial layer on the substrate does not overlap or partially overlaps with the orthographic projection of the second via hole on the substrate.

[0038] In some embodiments, at least part of the boundary of the orthographic projection of the reading electrode on the substrate is located within the boundary of the orthographic projection of the sacrificial layer on the substrate.

[0039] In some embodiments, the orthographic projection of the photoelectric conversion structure on the substrate does not overlap with the orthographic projection of the second via hole on the substrate.

[0040] In some embodiments, the boundary of the orthographic projection of the photoelectric conversion structure on the substrate is located within the boundary of the orthographic projection of the reading electrode on the substrate.

[0041] In some embodiments, a first passivation layer, a first organic layer, and a second passivation layer are further provided between the thin film transistor and the photoelectric conversion unit, the first organic layer is located on the side of the first passivation layer away from the substrate, and the second passivation layer is located on the side of the first organic layer away from the substrate.

[0042] The sacrificial layer is located between the first passivation layer and the first organic layer.

[0043] Alternatively, the sacrificial layer is located between the first organic layer and the second passivation layer.

[0044] In some embodiments, the material of the first passivation layer includes silicon oxide, and the material of the second passivation layer includes silicon oxide.

[0045] In some embodiments, the orthographic projection of the channel region on the substrate is located within the orthographic projection of the sacrificial layer on the substrate.

[0046] In some embodiments, a plurality of gate lines arranged along a first direction and a plurality of signal reading lines arranged along a second direction are further included, the gate lines extend along the second direction, and the signal reading lines extend along the first direction.

[0047] The thin film transistor further includes a gate electrode electrically connected to the corresponding gate line;

[0048] The second electrode is electrically connected to the corresponding signal read line.

[0049] In some embodiments, the detection pixel unit includes a sacrificial layer, a projection of the sacrificial layer on the substrate does not overlap with a projection of the gate line on the substrate, and a projection of the sacrificial layer on the substrate does not overlap with a projection of the signal read line on the substrate.

[0050] In some embodiments, the sacrificial layer includes a first portion and a second portion connected to each other, the first portion protrudes from the second portion near a portion of the gate line or the signal read line;

[0051] A line width of a portion of the signal read line near the first portion is smaller than a line width of a portion of the signal read line near the second portion, and a line width of a portion of the gate line near the first portion is smaller than a line width of a portion of the gate line near the second portion.

[0052] In some embodiments, the second electrode includes a first conductive portion for connecting to the active layer, a second conductive portion for connecting to an end of the photoelectric conversion portion near the substrate, and a third conductive portion connecting the first conductive portion and the second conductive portion, the third conductive portion is located between the first conductive portion and the second conductive portion;

[0053] The first conductive portion and the second conductive portion are both extended along the second direction away from a side edge of the gate line;

[0054] A distance between the first conductive portion and the gate line away from a side edge of the gate line is greater than a distance between the second conductive portion and the gate line away from a side edge of the gate line.

[0055] In some embodiments, the third conductive portion includes a first connecting portion connected to the first conductive portion, a second connecting portion connected to the second conductive portion, and a third connecting portion connecting the first connecting portion and the second connecting portion, the third connecting portion is located between the first connecting portion and the second connecting portion;

[0056] The first connecting portion is extended along the second direction, and a side edge of the first connecting portion away from the gate line is located on a same straight line as a side edge of the connected first conductive portion away from the gate line;

[0057] The second connection portion extends in the second direction, and a side edge of the second connection portion away from the gate line is on a same straight line as a side edge of the connected second conductive portion away from the gate line.

[0058] The third connection portion extends in a direction intersecting the second direction.

[0059] In some embodiments, the gate electrode includes a main body portion and a fourth connection portion connected to the main body portion, the fourth connection portion being in contact with the corresponding gate line.

[0060] The fourth connection portion has a width in the second direction that is greater than a width of the main body portion in the second direction.

[0061] In some embodiments, the width of the fourth connection portion in the second direction gradually decreases in a direction from the fourth connection portion to the main body portion.

[0062] In some embodiments, the detection substrate further includes:

[0063] A fifth passivation layer on a side of the bias voltage line away from the substrate.

[0064] A third organic layer on a side of the fifth passivation layer away from the substrate.

[0065] In a second aspect, the embodiments of the present disclosure further provide a flat panel detector, including the detection substrate provided in the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0066] Figure 1 A structural schematic diagram of a detection substrate provided by the embodiments of the present disclosure;

[0067] Figure 2 A structural schematic diagram of a region in which a detection pixel unit is located in the embodiments of the present disclosure;

[0068] Figure 3a A structural schematic diagram of a region in which a detection pixel unit is located in the embodiments of the present disclosure; Figure 2 A structural schematic diagram of a region in which a detection pixel unit is located in the embodiments of the present disclosure;

[0069] Figure 3b A structural schematic diagram of a region in which a detection pixel unit is located in the embodiments of the present disclosure; Figure 2 A structural schematic diagram of a region in which a detection pixel unit is located in the embodiments of the present disclosure;

[0070] Figure 3c A structural schematic diagram of a region in which a detection pixel unit is located in the embodiments of the present disclosure;

[0071] Figure 4 A structural schematic diagram of a region in which a detection pixel unit is located in the embodiments of the present disclosure; Figure 2A cross-sectional view of the present disclosure along the direction of A-A';

[0072] Figure 5 A cross-sectional view of the present disclosure along the direction of A-A'; Figure 2 A cross-sectional view of the present disclosure along the direction of A-A';

[0073] Figure 6 A cross-sectional view of the present disclosure along the direction of A-A'; Figure 2 A cross-sectional view of the present disclosure along the direction of A-A';

[0074] Figure 7 A cross-sectional view of the present disclosure along the direction of A-A'; Figure 2 A cross-sectional view of the present disclosure along the direction of A-A';

[0075] Figure 8 A cross-sectional view of the present disclosure along the direction of A-A'; Figure 2 A cross-sectional view of the present disclosure along the direction of A-A';

[0076] Figure 9 A cross-sectional view of the present disclosure along the direction of A-A';

[0077] Figure 10a A cross-sectional view of the present disclosure along the direction of A-A'; Figure 9 A cross-sectional view of the present disclosure along the direction of A-A';

[0078] Figure 10b A cross-sectional view of the present disclosure along the direction of A-A'; Figure 9 A cross-sectional view of the present disclosure along the direction of A-A';

[0079] Figure 10c A cross-sectional view of the present disclosure along the direction of A-A'; Figure 9 A cross-sectional view of the present disclosure along the direction of A-A';

[0080] Figure 11 A cross-sectional view of the present disclosure along the direction of A-A'; Figure 9 A cross-sectional view of the present disclosure along the direction of B-B';

[0081] Figure 12 A cross-sectional view of the present disclosure along the direction of B-B'; Figure 9 A cross-sectional view of the present disclosure along the direction of B-B';

[0082] Figure 13 A cross-sectional view of the present disclosure along the direction of B-B';

[0083] Figure 14 A cross-sectional view of the present disclosure along the direction of B-B';

[0084] Figure 15 A cross-sectional view of the present disclosure along the direction of B-B';

[0085] Figures 16a-16g A cross-sectional view of the present disclosure along the direction of B-B'; Figure 15A cross-sectional view of an intermediate product in the process of preparing the detection substrate by the preparation method shown in the figure;

[0086] Figure 17 A flow chart of another preparation method of a detection substrate provided by the embodiments of the present disclosure;

[0087] Figures 18a-18f For the embodiments of the present disclosure Figure 17 A cross-sectional view of an intermediate product in the process of preparing the detection substrate by the preparation method shown in the figure. DETAILED DESCRIPTION

[0088] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present disclosure.

[0089] In the embodiments of the present disclosure, the same items or similar items with basically the same functions and effects are distinguished by using "first", "second", etc., only for the purpose of clearly describing the technical solutions of the embodiments of the present disclosure, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features.

[0090] In the embodiments of the present disclosure, the meaning of "multiple" is two or more, and the meaning of "multiple" is two or more, unless otherwise explicitly and specifically limited.

[0091] In the embodiments of the present disclosure, the positions or position relationships indicated by the terms "upper", "lower", etc. are based on the positions or position relationships shown in the drawings, and are only for the purpose of facilitating the description of the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present disclosure.

[0092] Figure 1 A structural schematic diagram of a detection substrate provided by the embodiments of the present disclosure, Figure 2 A structural schematic diagram of a region in which a detection pixel unit is located in the embodiments of the present disclosure, Figure 3a A structural schematic diagram of a detection substrate provided by the embodiments of the present disclosure, Figure 2 A structural schematic diagram of forming a sacrificial layer on the side of the thin film transistor away from the substrate in the embodiments of the present disclosure, Figure 3b A structural schematic diagram of a detection substrate provided by the embodiments of the present disclosure, Figure 2 A structural schematic diagram of forming a third passivation layer on the side of the photoelectric conversion part away from the substrate in the embodiments of the present disclosure, Figure 3c A structural schematic diagram of forming a dielectric layer on the side of the third passivation layer away from the substrate, Figure 4 A structural schematic diagram of a detection substrate provided by the embodiments of the present disclosure, Figure 2Fig. 1 is a schematic view of a cross section along A-A' direction; as shown in the figure, the detection substrate comprises a substrate 1 and a plurality of detection pixel units Pix arranged in an array on the substrate 1. Figures 1-4

[0093] The detection pixel unit Pix comprises a thin film transistor 3 and a photoelectric conversion part 2 located on the side of the thin film transistor 3 away from the substrate 1, and the photoelectric conversion part 2 is provided with a bias voltage line 4 on the side away from the substrate 1.

[0094] The thin film transistor 3 comprises an active layer 302, a first electrode 303 and a second electrode 304, the active layer 302 comprises a channel region 30 and electrode contact regions located on both sides of the channel region 30, and the first electrode 303 and the second electrode 304 are respectively in contact with the electrode contact regions located on both sides of the channel region 30 to realize electrical connection with the active layer 302.

[0095] The photoelectric conversion part 2 is electrically connected to the second electrode 304 on the end close to the substrate 1, and the photoelectric conversion part 2 is electrically connected to the corresponding bias voltage line 4 on the end away from the substrate 1.

[0096] At least one dielectric layer is provided between the photoelectric conversion part 2 and the bias voltage line 4, a first via hole 6 is formed on the dielectric layer, and at least part of the projection of the channel region 30 on the substrate 1 is located within the projection of the first via hole 6 on the substrate 1; that is, the first via hole 6 and the channel region 30 overlap in the direction perpendicular to the substrate 1.

[0097] In the embodiments of the present disclosure, the first via hole 6 is provided in at least one dielectric layer above the channel region 30 of the thin film transistor 3, and the first via hole 6 and the channel region 30 overlap in the direction perpendicular to the substrate 1. Based on this pixel design, in the later high-temperature annealing process, it is beneficial to release hydrogen atoms in the channel region 30 outward, that is, the content of hydrogen atoms in the channel region 30 can be effectively reduced, thereby effectively reducing the conductivity of the thin film transistor 3 in the off state, preventing the channel region 30 from being conductive, and enhancing the stability of the thin film transistor 3.

[0098] In some embodiments, preferably, the projection of the channel region 30 on the substrate 1 is located within the projection of the first via hole 6 on the substrate 1; that is, the projection of the first via hole 6 on the substrate 1 can completely cover the projection of the channel region 30 on the substrate 1, which is beneficial to release hydrogen atoms in the channel region 30 outward.

[0099] In the embodiments of the present disclosure, the material of the substrate 1 is not limited; the material of the substrate 1 can include a rigid material, such as glass; or it can also include a flexible material, such as polyimide (PI).

[0100] ​In the thin film transistor 3 described above, the first electrode 303 and the second electrode 304 can be a drain and a source, respectively, and their functions can be interchanged according to the type of the thin film transistor 3 and the input signal, which is not specifically distinguished here. For example, if the thin film transistor 3 is an N-type thin film transistor 3, the first electrode 303 can be a drain, and the second electrode 304 can be a source. If the thin film transistor 3 is a P-type thin film transistor 3, the first electrode 303 can be a source, and the second electrode 304 can be a drain.

[0101] The thin film transistor 3 can further include a gate 301. The thin film transistor 3 can be a bottom-gate type thin film transistor 3 (the gate 301 is located on the side of the active layer 302 close to the substrate 1) as shown in FIG. 1, or can also be a top-gate type thin film transistor 3 (the gate 301 is located on the side of the active layer 302 away from the substrate 1, which is not given a corresponding figure), which is not limited here. It should be noted that since the gate 301 in the top-gate type thin film transistor 3 is located above the channel region 30, the gate 301 will block the movement of hydrogen atoms in the channel region 30 to the first via 6, which is not conducive to the release of hydrogen atoms in the channel region 30. Therefore, the bottom-gate type thin film transistor 3 is preferred in the present disclosure. Figure 4

[0102] In the embodiments of the present disclosure, the materials of the first electrode 303, the second electrode 304, and the gate 301 in the thin film transistor 3 can include metals such as molybdenum, aluminum, silver, copper, titanium, platinum, tungsten, etc., and can also include other conductive materials such as metal alloys, which can be selected according to actual requirements.

[0103] In the embodiments of the present disclosure, the active layer 302 in the thin film transistor 3 can adopt a metal oxide type semiconductor material. The metal oxide type thin film transistor 3 has the characteristics of high carrier mobility and fast switching speed, and is suitable for detecting a substrate. In some embodiments, the material of the active layer 302 includes at least one of indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), gallium indium tin oxide (GITO), and indium gallium zinc tin oxide (IGZTO).

[0104] In the embodiments of the present disclosure, the photoelectric conversion part 2 can convert light energy into electrical energy, and the specific structure of the photoelectric conversion part 2 is not limited. Referring to FIG. 2, the photoelectric conversion part 2 can include a photodiode 201, a readout integrated circuit (ROIC) 202, and a readout circuit 203. Figure 4 ​As shown, in some embodiments, the photoelectric conversion unit 2 may include a read electrode 201, a photoelectric conversion structure 202 and a conductive electrode 203. The conductive electrode 203 is located on the side of the read electrode 201 away from the substrate 1, and the photoelectric conversion structure 202 is located between the read electrode 201 and the conductive electrode 203.

[0105] In this disclosure, the photoelectric conversion unit 2 can be a PIN photodiode. The photoelectric conversion structure 202 may include a first doped layer, an intrinsic layer, and a second doped layer sequentially stacked on the read electrode 201, wherein the polarities of the first doped layer and the second doped layer are opposite; the first doped layer is in contact with the read electrode 201, and the second doped layer 152 is in contact with the conductive electrode 203.

[0106] The first and second doped layers described above may each include N-type or P-type impurities. The intrinsic layer described above does not contain impurities. The thickness of the intrinsic layer may be greater than the thickness of the first and second doped layers.

[0107] If the first doped layer includes N-type impurities and the second doped layer includes P-type impurities, then the first doped layer is an N-type semiconductor layer and the second doped layer is a P-type semiconductor layer. In this case, a negative bias voltage can be applied to the second doped layer through the bias electrode and the conductive electrode 203. If the first doped layer includes P-type impurities and the second doped layer includes N-type impurities, then the first doped layer is a P-type semiconductor layer and the second doped layer is an N-type semiconductor layer. In this case, a positive bias voltage can be applied to the second doped layer through the bias electrode and the conductive electrode 203.

[0108] In some embodiments, the conductive electrode 203 is a transparent electrode, which may be made of transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), and gallium zinc oxide (GZO); the reading electrode 201 is a metal electrode, which may be made of metal materials or alloy materials such as copper (Cu), aluminum (Al), and titanium (Ti).

[0109] See Figure 2 , Figure 3b as well as Figure 3c As shown, in some embodiments, the orthographic projection of the channel region 30 on the substrate 1 does not overlap with the orthographic projection of the photoelectric conversion section 3 on the substrate 1. That is, there is no portion of the photoelectric conversion section 3 located directly above the channel region; this design effectively reduces the amount of hydrogen atoms diffusing into the channel region during the fabrication process of the photoelectric conversion section 3.

[0110] In some embodiments, the material of the read electrode 201 comprises a metal material; the orthographic projection of the layer structure where the read electrode 201 is located on the substrate 1 does not overlap with the orthographic projection of the channel region 30 on the substrate 1; by this design, the read electrode 201 can effectively avoid adversely affecting the process of the channel region 30 releasing hydrogen atoms outward through the first via 6.

[0111] Since the orthographic projection of the layer structure where the read electrode 201 is located on the substrate 1 does not overlap with the orthographic projection of the channel region 30 on the substrate 1, that is, the read electrode does not cover the channel region 30, external light can irradiate the channel region 30, thereby causing the electrical characteristics of the thin film transistor 3 to deviate. To solve this problem, further, in some embodiments, the material of the bias voltage line 4 comprises a metal material, and the orthographic projection of the channel region 30 on the substrate 1 is located within the orthographic projection of the bias voltage line 4 on the substrate. That is, the part of the bias voltage line 4 covering the channel region 30 can play a role in shading light, which can avoid the problem of light irradiating the channel region 30 of the thin film transistor 3 and causing the electrical characteristics of the thin film transistor 3 to deviate.

[0112] The detection substrate provided by the embodiments of the present disclosure can be applied to an X-ray flat panel detector. The X-ray flat panel detector can be a direct conversion type (Direct DR) detector, or can also be an indirect conversion type (Indirect DR) detector, which is not limited here. Among them, the indirect conversion type X-ray flat panel detector technology is relatively mature, the cost is relatively low, the detection quantum efficiency (Detective Quantum Efficiency, DQE) is high, and the reliability is good, so it has been widely developed and applied. The display principle of the indirect conversion type X-ray flat panel detector is: under X-ray irradiation, the scintillator layer or the fluorescent layer of the indirect conversion type X-ray flat panel detector converts X-ray photons into visible light, and then converts the visible light into an electrical signal under the action of the photoelectric conversion unit 2. Finally, the electrical signal is read by the thin film transistor 3 and outputted to obtain a display image.

[0113] Of course, the above detection substrate can also be applied to other products using metal oxide thin film transistors 3. After the metal oxide thin film transistor 3 of such products is manufactured, there is a high hydrogen, high water, high oxygen, and other sensitizing environment in the subsequent process. By using the above detection substrate, the metal oxide thin film transistor 3 can be protected as much as possible to avoid being reduced, so as to improve the stability of the metal oxide thin film transistor 3.

[0114] Continuing to refer to Figure 4As shown in some embodiments, the at least one dielectric layer includes a second organic layer 5. The second organic layer 5 can serve as insulation and planarization to facilitate the preparation of subsequent film layers. The first via hole 6 for releasing hydrogen atoms outward from the channel region 30 is formed in the second organic layer 5. In some embodiments, the material of the second organic layer 5 can include polyacrylic resin, polyepoxy acrylic resin, polyester acrylate, polyurethane acrylate resin, or the like organic resin material.

[0115] Figure 5 As shown in some embodiments, the at least one dielectric layer includes a second organic layer 5. The second organic layer 5 can serve as insulation and planarization to facilitate the preparation of subsequent film layers. The first via hole 6 for releasing hydrogen atoms outward from the channel region 30 is formed in the second organic layer 5. In some embodiments, the material of the second organic layer 5 can include polyacrylic resin, polyepoxy acrylic resin, polyester acrylate, polyurethane acrylate resin, or the like organic resin material. Figure 2 As shown in some embodiments, the at least one dielectric layer includes a second organic layer 5. The second organic layer 5 can serve as insulation and planarization to facilitate the preparation of subsequent film layers. The first via hole 6 for releasing hydrogen atoms outward from the channel region 30 is formed in the second organic layer 5. In some embodiments, the material of the second organic layer 5 can include polyacrylic resin, polyepoxy acrylic resin, polyester acrylate, polyurethane acrylate resin, or the like organic resin material. Figure 5 As shown in some embodiments, the at least one dielectric layer includes a second organic layer 5. The second organic layer 5 can serve as insulation and planarization to facilitate the preparation of subsequent film layers. The first via hole 6 for releasing hydrogen atoms outward from the channel region 30 is formed in the second organic layer 5. In some embodiments, the material of the second organic layer 5 can include polyacrylic resin, polyepoxy acrylic resin, polyester acrylate, polyurethane acrylate resin, or the like organic resin material. Figure 5 As shown in some embodiments, the at least one dielectric layer includes a second organic layer 5. The second organic layer 5 can serve as insulation and planarization to facilitate the preparation of subsequent film layers. The first via hole 6 for releasing hydrogen atoms outward from the channel region 30 is formed in the second organic layer 5. In some embodiments, the material of the second organic layer 5 can include polyacrylic resin, polyepoxy acrylic resin, polyester acrylate, polyurethane acrylate resin, or the like organic resin material.

[0116] Figure 6 As shown in some embodiments, the at least one dielectric layer includes a second organic layer 5. The second organic layer 5 can serve as insulation and planarization to facilitate the preparation of subsequent film layers. The first via hole 6 for releasing hydrogen atoms outward from the channel region 30 is formed in the second organic layer 5. In some embodiments, the material of the second organic layer 5 can include polyacrylic resin, polyepoxy acrylic resin, polyester acrylate, polyurethane acrylate resin, or the like organic resin material. Figure 2 As shown in some embodiments, the at least one dielectric layer includes a second organic layer 5. The second organic layer 5 can serve as insulation and planarization to facilitate the preparation of subsequent film layers. The first via hole 6 for releasing hydrogen atoms outward from the channel region 30 is formed in the second organic layer 5. In some embodiments, the material of the second organic layer 5 can include polyacrylic resin, polyepoxy acrylic resin, polyester acrylate, polyurethane acrylate resin, or the like organic resin material. Figure 6 As shown in some embodiments, the at least one dielectric layer includes a second organic layer 5. The second organic layer 5 can serve as insulation and planarization to facilitate the preparation of subsequent film layers. The first via hole 6 for releasing hydrogen atoms outward from the channel region 30 is formed in the second organic layer 5. In some embodiments, the material of the second organic layer 5 can include polyacrylic resin, polyepoxy acrylic resin, polyester acrylate, polyurethane acrylate resin, or the like organic resin material.

[0117] In the process of the photoelectric conversion unit 2 and the process of various passivation layers after the process of the sacrificial layer 10, a large amount of hydrogen atoms will be generated, which will penetrate towards the thin film transistor 3 below. In the embodiment of the present disclosure, by arranging the sacrificial layer 10 between the thin film transistor 3 and the photoelectric conversion unit 2, the sacrificial layer 10 can chemically react with the hydrogen atoms generated in the subsequent processes, thereby playing a role of consuming and blocking the hydrogen atoms, and further preventing the hydrogen atoms from penetrating to the thin film transistor 3. Therefore, the arrangement of the sacrificial layer 10 can reduce the content of hydrogen atoms in the channel region 30 to a certain extent, thereby effectively reducing the conductivity of the thin film transistor 3 in the off state, preventing the channel region 30 from being conductorized, and greatly improving the stability of the thin film transistor 3. Preferably, the orthographic projection of the channel region 30 on the substrate 1 is completely located within the orthographic projection of the sacrificial layer 10 on the substrate 1, at which time the blocking effect of the sacrificial layer 10 on the hydrogen atoms penetrating towards the channel region 30 is better.

[0118] In some embodiments, the material of the sacrificial layer 10 includes any one of indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), and indium gallium tin oxide (GITO). The sacrificial layer 10 is more likely to react with hydrogen atoms and can consume more hydrogen atoms to play a role of protecting the thin film transistor 3.

[0119] As an optional embodiment, the sacrificial layer 10 is in contact with the photoelectric conversion unit 2 at one end close to the substrate 1, and the sacrificial layers 10 in different detection pixel units Pix are insulated from each other. In the embodiment of the present disclosure, since the sacrificial layer 10 is electrically connected with the photoelectric conversion unit 2, no capacitance will be generated between them. At the same time, the sacrificial layers 10 of each detection pixel unit Pix are independent and insulated from each other, thereby avoiding the influence of the sacrificial layers 10 of different detection pixel units Pix on each other, and further solving the signal crosstalk problem, and further improving the product performance.

[0120] In the embodiments of the present disclosure, the orthogonal projection of the bias voltage line 4 on the substrate 1 completely covers the orthogonal projection of the channel region 30 on the substrate 1, the orthogonal projection of the sacrificial layer 10 on the substrate 1 at least partially covers the orthogonal projection of the channel region 30 on the substrate 1, and the orthogonal projection of the first via 6 on the substrate 1 partially covers the orthogonal projection of the channel region 30 on the substrate 1, which can easily cause the bias voltage line 4 to contact the underlying sacrificial layer 10 through the first via 6, resulting in electrical connection between the bias voltage line 4 and the sacrificial layer 10, and thus causing defects. To solve this problem, a third passivation layer 15 is arranged between the sacrificial layer 10 and the bias voltage line 4, and the orthogonal projection of the first via 6 on the substrate 1 is located within the orthogonal projection of the third passivation layer 15 on the substrate 1. That is, at the bottom of the first via 6, the third passivation layer 15 is used to isolate the bias voltage line 4 from the sacrificial layer 10.

[0121] To minimize the influence of the third passivation layer 15 on the effect of the channel region 30 on the release of hydrogen atoms through the first via 6, the third passivation layer 15 can be made of an insulating material with relatively low density. In some embodiments, the density of the third passivation layer 15 is less than the density of the buffer layer 11, and the density of the third passivation layer 15 is less than the density of the fourth passivation layer 12. Further optionally, the material of the third passivation layer 15 includes silicon oxide, the material of the buffer layer 11 includes silicon nitride, and the material of the fourth passivation layer 12 includes silicon nitride.

[0122] In some embodiments, a first passivation layer 7, a first organic layer 8, and a second passivation layer 9 are further arranged between the thin film transistor 3 and the photoelectric conversion part 2, the first organic layer 8 is located on the side of the first passivation layer 7 away from the substrate 1, and the second passivation layer 9 is located on the side of the first organic layer 8 away from the substrate 1; the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2. As a specific implementation, the sacrificial layer 10 is located above the passivation layer and contacts the read electrode 201 in the photoelectric conversion part 2.

[0123] In some embodiments, a second via 16 is formed on the first passivation layer 7, the first organic layer 8, and the second passivation layer 9 and communicates with the second electrode 304; the photoelectric conversion part 2 includes a read electrode 201 and a photoelectric conversion structure 202, and the photoelectric conversion structure 202 is located on the side of the read electrode 201 away from the substrate 1; the read electrode 201 contacts the second electrode 304 through the second via 16, and the sacrificial layer 10 does not contact the second electrode 304.

[0124] The first passivation layer 7 covers the thin film transistor 3 and can play a protective and insulating role. The material of the first passivation layer 7 can include silicon nitride, silicon oxide, or silicon oxynitride. The first organic layer 8 is located between the first passivation layer 7 and the sacrificial layer 10, and can play a role of insulation and planarization. The material of the first organic layer 8 can include organic resin materials such as polyacrylic resin, polyepoxy acrylic resin, polyester acrylate, polyurethane acrylate resin, etc. The second insulating layer covers the first organic layer 8 and can also play a protective and insulating role. In addition, the second insulating layer can also improve the bonding firmness between the sacrificial layer 10 and the underlying film layer.

[0125] It should be noted that the sacrificial layer 10 can be arranged only on the side of the first organic layer 8 away from the substrate 1, and not arranged in the second via hole 16; or the sacrificial layer 10 can also extend to the sidewall of the second via hole 16 (in this case, no corresponding figure is given).

[0126] In the embodiments of the present disclosure, the reading electrode 201 and the second electrode 304 are both metal electrodes, and the material of the sacrificial layer 10 is an oxide material. The contact resistance between the two metal electrodes is much smaller than the contact resistance between the metal electrode and the oxide layer. Therefore, in the present disclosure, the reading electrode 201 is in contact with the second electrode 304, which can form a smaller contact resistance and is beneficial to signal transmission.

[0127] In some embodiments, the orthographic projection of the sacrificial layer 10 on the substrate 1 and the orthographic projection of the second via hole 16 on the substrate 1 do not overlap or partially overlap.

[0128] When the orthographic projection of the sacrificial layer 10 on the substrate 1 and the orthographic projection of the second via hole 16 on the substrate 1 do not overlap, the sacrificial layer 10 can be arranged around the area where the second via hole 16 is located, or the sacrificial layer 10 can also have a hollow structure in the area where the second via hole 16 is located. This structure has a simple manufacturing process and is easy to implement.

[0129] When the orthographic projection of the sacrificial layer 10 on the substrate 1 and the orthographic projection of the second via hole 16 on the substrate 1 partially overlap, the sacrificial layer 10 extends into the second via hole 16. In this structure, the coverage range of the sacrificial layer 10 is larger, and the shielding area is larger, so that the thin film transistor 3 can be protected more comprehensively.

[0130] In some embodiments, at least part of the boundary of the orthographic projection of the reading electrode 201 on the substrate 1 is located within the boundary of the orthographic projection of the sacrificial layer 10 on the substrate 1.

[0131] In the aforementioned detection substrate, a portion of the boundary of the orthogonal projection of the read electrode 201 onto the substrate 1 lies within the boundary of the orthogonal projection of the sacrificial layer 10 onto the substrate 1; or, all the boundaries of the orthogonal projection of the read electrode 201 onto the substrate 1 lie within the boundary of the orthogonal projection of the sacrificial layer 10 onto the substrate 1. Alternatively, all the boundaries of the orthogonal projection of the sacrificial layer 10 onto the substrate 1 may also lie within the boundary of the orthogonal projection of the read electrode 201 onto the substrate 1; or, the boundaries of the orthogonal projection of the read electrode 201 onto the substrate 1 may coincide with the boundaries of the orthogonal projection of the sacrificial layer 10 onto the substrate 1.

[0132] The following sections will explain the two scenarios in detail.

[0133] The first type, reference Figure 6 As shown, the boundary of the orthographic projection of the read electrode 201 on the substrate 1 is located within the boundary of the orthographic projection of the sacrificial layer 10 on the substrate 1. Specifically, the boundary of the orthographic projection of the read electrode 201 on the substrate 1 refers to the outer boundary of the orthographic projection of the read electrode 201 on the substrate 1, and the boundary of the orthographic projection of the sacrificial layer 10 on the substrate 1 refers to the outer boundary of the orthographic projection of the sacrificial layer 10 on the substrate 1.

[0134] In this case, a relatively flat read electrode 201 can be formed, and the photoelectric conversion structure 202 subsequently formed on the read electrode 201 is also relatively flat, which is beneficial to improving the performance of the photoelectric conversion structure 202.

[0135] The second case is where the boundary of the orthogonal projection of the read electrode 201 onto the substrate 1 is located outside the boundary of the orthogonal projection of the sacrificial layer 10 onto the substrate 1 (no corresponding figure is given for this case).

[0136] In this case, the size of the read electrode 201 can be made slightly larger, and the size of the sacrificial layer 10 can be made slightly smaller, which can improve the read speed of the read electrode 201; however, the formed read electrode 201 will form a discontinuity at the edge of the sacrificial layer 10, which is not conducive to the subsequent formation of a flat photoelectric conversion structure 202.

[0137] In some embodiments, the orthographic projection of the photoelectric conversion structure 202 on the substrate 1 does not overlap with the orthographic projection of the second via 16 on the substrate 1. Therefore, the photoelectric conversion section 2 is not provided within the second via 16. The photoelectric conversion structure 202 can then be disposed around the area where the second via 16 is located, or it can have a hollow structure in the area where the second via 16 is located; this is not limited here. This design is beneficial for forming a flat photoelectric conversion section 2, thereby improving the performance of the photoelectric conversion section 2. Of course, the photoelectric conversion section 2 can also cover the second via 16, which can increase the fill rate, but the bottom of the photoelectric conversion section 2 will be uneven, resulting in poor photoelectric conversion performance.

[0138] In some embodiments, in order to improve the reading efficiency of the reading electrode 201, the boundary of the orthographic projection of the photoelectric conversion structure 202 on the substrate 1 is located within the boundary of the orthographic projection of the reading electrode 201 on the substrate 1. Here, the boundary of the orthographic projection of the photoelectric conversion structure 202 on the substrate 1 refers to the outer boundary of the orthographic projection of the photoelectric conversion structure 202 on the substrate 1, and the boundary of the orthographic projection of the reading electrode 201 on the substrate 1 refers to the outer boundary of the orthographic projection of the reading electrode 201 on the substrate 1.

[0139] It should be noted that the case where the boundary of the orthographic projection of the photoelectric conversion structure 202 on the substrate 1 coincides with the boundary of the orthographic projection of the reading electrode 201 on the substrate 1 also falls within the above-mentioned category.

[0140] In some embodiments, the orthographic projection of the conductive electrode 203 on the substrate 1 is located within the orthographic projection of the photoelectric conversion structure 202 on the substrate 1.

[0141] Continuing to refer to Figure 1 As shown in the figure, the detection substrate further includes a plurality of gate lines 21 arranged along a first direction and a plurality of signal reading lines 22 arranged along a second direction. The gate lines 21 and the signal reading lines 22 intersect with each other to form a plurality of pixel regions; wherein the detection pixel unit Pix is located in the pixel region, and the first direction and the second direction intersect. The gate line 21 is electrically connected to at least the gate electrode 301 of the thin film transistor 3 in a row of detection pixel units Pix arranged along the second direction, and the signal reading line 22 is electrically connected to at least the first electrode 303 of the thin film transistor 3 in a row of detection pixel units Pix arranged along the first direction. Figure 1 The first direction is exemplarily taken as the column direction, and the second direction is exemplarily taken as the row direction, and the first direction is perpendicular to the second direction, which only serves as an example and does not limit the technical solutions of the present disclosure.

[0142] The gate line 21 can provide a control signal to the gate electrode 301 of the thin film transistor 3 to control the thin film transistor 3 to open or close; the electrical signal converted by the photoelectric conversion unit 2 from the visible light is output through the thin film transistor 3 and transmitted to the processing unit through the signal reading line 22, and the processing unit processes the electrical signal to realize the display of the image.

[0143] It should be noted that the gate line 21 can be disposed in the same layer as the gate electrode 301 of the thin film transistor 3, and the signal reading line 22 can be disposed in the same layer as the first electrode and the second electrode of the thin film transistor 3, so as to reduce the number of patterning processes and reduce the cost. Here, the same layer refers to one-time patterning process. The one-time patterning process refers to a process of forming the required layer structure through one-time film formation and photolithography. The one-time patterning process includes film formation, exposure, development, etching, and stripping, etc.

[0144] In some embodiments, the detecting pixel unit Pix comprises a sacrifice layer 10, a projection of the sacrifice layer 10 on the substrate 1 does not overlap with a projection of the gate line 21 on the substrate 1, and a projection of the sacrifice layer 10 on the substrate 1 does not overlap with a projection of the signal reading line 22 on the substrate 1.

[0145] Continuing to refer to Figure 3a As shown, the sacrifice layer 10 comprises a first part 10a and a second part 10b connected with each other, and the first part 10a protrudes from the second part 10b near the part of the gate line 21 or the signal reading line 22. Figure 3a In the drawings, the first part 10a and the second part 10b are spaced apart by a black dashed line for the purpose of clear distinction, but the dashed line does not exist in practice.

[0146] The line width W1 of the part of the signal reading line 22 near the first part 10a is smaller than the line width W2 of the part of the signal reading line 22 near the second part 10b, and the line width W3 of the part of the gate line 21 near the first part 10a is smaller than the line width W4 of the part of the gate line 21 near the second part 10b.

[0147] Referring to Figure 3a As shown, a projection of the thin film transistor 3 on the substrate 1 is located within a projection of the first part 10a of the sacrifice layer 10 on the substrate 1, and a projection of the second part 10b on the substrate 1 does not overlap with a projection of the thin film transistor 3 on the substrate 1.

[0148] The part of the first part 10a of the sacrifice layer 10 near the gate line 21 or the signal reading line 22 protrudes from the second part 10b, which on one hand can expand the coverage of the sacrifice layer 10 as much as possible without increasing the original design area, and ensure that the projection of the thin film transistor 3 on the substrate 1 is located within the projection of the first part 10a on the substrate 1, so as to protect the whole thin film transistor 3, and on the other hand, can improve the filling rate of the photoelectric conversion unit 2, so as to further improve the detection accuracy.

[0149] The line width will directly affect the resistance of the signal reading line 22 and the gate line 21, and further affect the data transmission rate. The line width design structure of the signal reading line 22 and the gate line 21 can on one hand reduce the influence on the line width of the signal reading line 22 and the gate line 21 as much as possible, so as to ensure the data transmission rate, and on the other hand, can utilize the original design area as much as possible without increasing the design area, so as to ensure the detection accuracy of the detection substrate.

[0150] Figure 7 For Figure 2 Another cross-sectional view in the direction of A-A’ is shown in FIG. 4, which is similar to the view shown in FIG. 3. Figure 7As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8. Figure 7 As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8.

[0151] Figure 8 As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8. Figure 2 As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8. Figure 8 As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8. Figure 8 As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8.

[0152] As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8. Figure 7 As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8. Figure 8 As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8. Figure 7 As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8. Figure 8 As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8.

[0153] As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8. Figure 7 As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8. Figure 8 As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8.

[0154] As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8. Figure 7 As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8. Figure 8 As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8.

[0155] As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8. Figures 4-8 As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8.

[0156] As shown, unlike the case shown in the foregoing embodiments where the sacrificial layer 10 is located between the second passivation layer 9 and the photoelectric conversion part 2, in the case shown in FIG. 6, the sacrificial layer 10 is located between the first passivation layer 7 and the first organic layer 8. Figure 4In the illustrated case, the dielectric layer located between the photoelectric conversion unit 2 and the bias voltage line 4 is specifically the second organic layer 5, on which a third via 17 connecting to the conductive electrode 203 is formed. Figures 5-8 In the case shown, the dielectric layer located between the photoelectric conversion unit 2 and the bias voltage line 4 is specifically a buffer layer 11, an organic layer and a fourth passivation layer 12. At this time, a third via 17 connected to the conductive electrode 203 is formed on the buffer layer 11, the organic layer and the fourth passivation layer 12.

[0157] See Figures 4-8 As shown, in some embodiments, the probe substrate further includes a fifth passivation layer 13 and a third organic layer 14. The fifth passivation layer 13 and the third organic layer 14 serve to encapsulate the probe substrate. In some embodiments, the fifth passivation layer 13 is made of a relatively dense insulating material, such as silicon nitride, and the material of the third organic layer 14 may include organic resin materials such as polyacrylic acid resin, polyepoxy acrylate resin, polyester acrylate, and polyurethane acrylate resin.

[0158] See also Figure 1 As shown, the aforementioned probe substrate may further include a gate driving unit, a processing unit, and a bias driving unit. The gate driving unit is connected to multiple gate lines and can provide control signals to the gate lines. The processing unit is connected to multiple data lines and can acquire and process the electrical signals output from the data lines. The bias driving unit is connected to multiple bias voltage lines 4 and can provide bias signals to the bias voltage lines 4. The specific structures of the gate driving unit, processing unit, and bias driving unit are not limited. Furthermore, Figure 1 The illustration only shows a case where 12 detector pixel units (Pix) are arranged in 3 rows and 4 columns. This case is for illustrative purposes only and does not limit the technical solution of this disclosure.

[0159] Figure 9 This is a schematic diagram illustrating another structural feature of the region where a detection pixel unit is located, as described in an embodiment of this disclosure. Figure 10a for Figure 9 A schematic diagram of a structure in which a sacrificial layer is formed on the side of a thin-film transistor away from the substrate. Figure 10b for Figure 9 A schematic diagram of a structure in which a photoelectric conversion section is formed on the side of a thin-film transistor away from the substrate. Figure 10c for Figure 9 A schematic diagram of a structure in which a dielectric layer is formed on the side of the photoelectric conversion unit away from the substrate. Figure 11 for Figure 9 A schematic diagram of a cross-section along the B-B' direction. Figure 12 for Figure 9 Another cross-sectional diagram along the B-B' direction, as shown below. Figures 9-12 As shown, with Figure 2 ,Figure 3b 、 Figure 3c In the present embodiment, the orthogonal projection of the channel region 30 on the substrate 1 is located within the orthogonal projection of the photoelectric conversion portion 2 on the substrate 1; that is, the orthogonal projection of the photoelectric conversion portion 2 on the substrate 1 completely covers the channel region 30.

[0160] In some embodiments, the first via 6 for releasing hydrogen atoms in the channel region 30 and the third via 17 for connecting the bias voltage line 4 and the conductive electrode 203 are the same via, and at least part of the orthogonal projection of the channel region 30 on the substrate 1 is located within the orthogonal projection of the via on the substrate 1.

[0161] In the embodiments of the present disclosure, the orthogonal projection of the photoelectric conversion portion 2 on the substrate 1 completely covers the channel region 30; that is, the orthogonal projection of the read electrode on the substrate 1 can completely cover the channel region, so that the read electrode can avoid light irradiation to the channel region 30 of the thin film transistor 3, and thus there is no need to use the bias voltage line 4 to cover the channel region 30. Therefore, in order to improve the light emitting area of the pixel region, preferably, the material of the bias voltage line 4 includes a transparent conductive material, such as indium tin oxide, indium zinc oxide, gallium zinc oxide, etc.

[0162] In the case shown in FIG. 6, the areas where the first via 6, the second via 16, and the third via 17 are located in the pixel unit Pix cannot emit light, while in the case shown in FIG. 7, only the area where the second via 16 is located in the pixel unit Pix cannot emit light; therefore, compared with the scheme shown in FIG. 6, the scheme shown in FIG. 7 can effectively improve the light emitting area of the pixel region. Figure 2 Figure 9 It should be noted that, Figure 2 In the case shown in FIG. 6, the thin film transistor 3 is located at the lower right corner of the pixel region, and the second via 16 is located at the lower left corner of the pixel region, which only serves as an exemplary role and does not limit the technical scheme of the present disclosure. Figure 9 Of course, in some embodiments, the case shown in FIG. 7 can also use the sacrificial layer 10 in the foregoing embodiments, and the sacrificial layer 10 is located between the thin film transistor 3 and the photoelectric conversion portion 2; for the position of the sacrificial layer 10, the material, the relative position relationship between the sacrificial layer 10 and the channel region 30, the relative position relationship between the sacrificial layer 10 and the photoelectric conversion portion 2, and the relative position relationship between the sacrificial layer 10 and each via, the corresponding contents in the foregoing embodiments can be referred to, and will not be described herein.

[0163] Figure 9

[0164] Of course, in some embodiments, the case shown in FIG. 7 can also use the sacrificial layer 10 in the foregoing embodiments, and the sacrificial layer 10 is located between the thin film transistor 3 and the photoelectric conversion portion 2; for the position of the sacrificial layer 10, the material, the relative position relationship between the sacrificial layer 10 and the channel region 30, the relative position relationship between the sacrificial layer 10 and the photoelectric conversion portion 2, and the relative position relationship between the sacrificial layer 10 and each via, the corresponding contents in the foregoing embodiments can be referred to, and will not be described herein. Figure 9

[0165] ​​​​It should be noted that since the first via 6 is located directly above the photoelectric conversion unit 2, even if the sacrificial layer is in contact with the end of the sacrificial layer 10 and the photoelectric conversion unit 2 near the substrate 1, there is no risk that the bias voltage line 4 will contact the sacrificial layer 10 through the first via 6. Therefore, there is no need to provide the third passivation layer in the previous embodiment.

[0166] Figure 13 This is a schematic diagram of the gate line, read signal line, and thin-film transistor in an embodiment of this disclosure, such as... Figure 13 As shown, in some embodiments, the second electrode 304 of the thin-film transistor 3 includes: a first conductive portion 3041 for connection to the active layer 302, a second conductive portion 3042 for connection to the end of the photoelectric conversion unit 2 near the substrate 1, and a third conductive portion 3043 connecting the first conductive portion 3041 and the second conductive portion 3042, the third conductive portion 3043 being located between the first conductive portion 3041 and the second conductive portion 3042; the edge of the first conductive portion 3041 away from the gate line 21 and the edge of the second conductive portion 3042 away from the gate line both extend along a second direction; the distance between the edge of the first conductive portion 3041 away from the gate line 21 and the gate line 21 is greater than the distance between the edge of the second conductive portion 3042 away from the gate line 21 and the gate line 21. This design allows the second conductive portion 3042, which is connected to the end of the photoelectric conversion unit 2 near the substrate 1, to be closer to the gate line 21, which is beneficial for improving the fill rate of the pixel region by the detection pixel unit Pix.

[0167] Further, in some embodiments, the third conductive portion 3043 includes: a first connecting portion 30431 connected to the first conductive portion 3041, a second connecting portion 30432 connected to the second conductive portion 3042, and a third connecting portion 30433 connecting the first connecting portion 30431 and the second connecting portion 30432, wherein the third connecting portion 30433 is located between the first connecting portion 30431 and the second connecting portion 30432; the first connecting portion 30431 extends along a second direction, and the edge of the first connecting portion 30431 away from the gate line 21 is on the same straight line as the edge of the first conductive portion 3041 away from the gate line 21; the second connecting portion 30432 extends along a second direction, and the edge of the second connecting portion 30432 away from the gate line 21 is on the same straight line as the edge of the second conductive portion 3042 away from the gate line; the extending direction of the third connecting portion 30433 intersects the second direction. That is, the third conductive part 3043 is bent on the side closest to the gate line.

[0168] See also Figure 13As shown in FIG. 1, the gate electrode 301 includes a main body part 3011 and a fourth connecting part 3012 connected to the main body part 3011, and the fourth connecting part 3012 is in contact with the corresponding gate line 21; the width of the fourth connecting part 3012 in the second direction is greater than the width of the main body part 3011 in the second direction. That is, the part of the gate electrode 301 connected to the gate line 21 is widened; through this design, it is beneficial for the gate line 21 to deliver the control signal to the gate electrode 301. In some embodiments, the width of the fourth connecting part 3012 in the second direction gradually decreases in the direction from the fourth connecting part 3012 to the main body part 3011.

[0169] It should be noted that, Figure 2 、 Figures 3a-3c The gate line 301, the read signal line 22, and the thin film transistor 3 shown in FIG. 1 can also adopt the structure shown in FIG. 2. Figure 13

[0170] Based on the same inventive concept, the embodiments of the present application also provide a flat panel detector, which includes a detection substrate, and the detection substrate can adopt the detection substrate provided in the foregoing embodiments.

[0171] The flat panel detector provided by the embodiments of the present application can be an X-ray flat panel detector, which can be applied in the fields of medical treatment, security and protection, and industrial detection, and has the advantages of stable performance and fast response speed; the related structure description of the detection substrate included in the flat panel detector can refer to the content in the foregoing embodiments, which will not be described herein again.

[0172] The embodiments of the present application also provide a preparation method of a detection substrate, which can be used to prepare the detection substrate provided in the foregoing embodiments. Figure 14 The flow chart of the preparation method of the detection substrate provided by the embodiments of the present application is shown in FIG. 1, and the preparation method includes the following steps. Figure 14

[0173] Step S101: forming a plurality of detection pixel units arranged in an array on one side of a substrate.

[0174] The detection pixel unit includes a thin film transistor and a photoelectric conversion part located on the side of the thin film transistor away from the substrate. The thin film transistor includes an active layer, a first electrode and a second electrode, and the first electrode and the second electrode are both electrically connected to the active layer, and the active layer includes a channel region; one end of the photoelectric conversion part close to the substrate is electrically connected to the second electrode of the thin film transistor in the same detection pixel unit.

[0175] Step S102: forming at least one dielectric layer on the side of the thin film transistor away from the substrate, and a first via hole is formed on the dielectric layer.

[0176] ​​Wherein, at least a portion of the orthographic projection of the channel region on the substrate is located within the orthographic projection of the first via on the substrate.

[0177] Step S103: Form a bias voltage line on the side of the dielectric layer away from the substrate.

[0178] The bias voltage line is electrically connected to the end of the corresponding photoelectric conversion unit that is away from the substrate.

[0179] In this embodiment, a first via is provided in at least one dielectric layer above the channel region of the thin-film transistor, and the first via overlaps with the channel region in a direction perpendicular to the substrate. Based on this pixel design, in subsequent high-temperature annealing and other processes, it is beneficial for hydrogen atoms in the channel region to be released outward, that is, the content of hydrogen atoms in the channel region can be effectively reduced, thereby effectively reducing the conductivity of the thin-film transistor in the off state, preventing the channel region from becoming conductive, and enhancing the stability of the thin-film transistor.

[0180] Figure 15 This is a flowchart illustrating another method for fabricating a detector substrate according to an embodiment of this disclosure. Figures 16a-16g To adopt Figure 15 The diagram shows a cross-sectional view of an intermediate product during the fabrication of the probe substrate using the method described above. Figures 15-16g As shown, this preparation method can be used to prepare products with... Figure 6 A probe substrate shown in the cross-section, the preparation method of which includes:

[0181] Step S201: Form multiple gate lines, multiple signal readout lines, and multiple thin-film transistors on the array substrate.

[0182] See Figure 16a As shown, in step S201, gate lines (not shown), signal readout lines (not shown), and thin-film transistors 3 can be formed on the substrate 1 based on the array (Ararry) process.

[0183] Step S202: A first passivation layer, a first organic layer, and a second passivation layer are sequentially formed on the side of the thin-film transistor away from the substrate.

[0184] See Figure 16b As shown, a second via 16 is formed on the first passivation layer 7, the first organic layer 8, and the second passivation layer 9, which is connected to the second electrode 304 of the thin film transistor 3.

[0185] The first passivation layer 7 and the second passivation layer 9 can be made of silicon oxide, and the first organic layer 8 can be made of organic resin materials such as polyacrylic acid resin, polyepoxy acrylic resin, polyester acrylate, and polyurethane acrylate resin.

[0186] Step S203, forming a sacrificial layer on the side of the second passivation layer away from the substrate substrate.

[0187] Referring to Figure 16c As shown, at least part of the orthographic projection of the channel region 30 on the substrate substrate 1 is located within the orthographic projection of the sacrificial layer 10 on the substrate substrate 1.

[0188] In some embodiments, the orthographic projection of the sacrificial layer 10 on the substrate substrate 1 does not overlap or partially overlaps with the orthographic projection of the second via 16 on the substrate substrate 1, and the sacrificial layer 10 does not contact the second electrode 304.

[0189] In some embodiments, the material of the sacrificial layer 10 includes an oxide, such as at least one of indium zinc oxide, indium tin oxide, indium gallium zinc oxide, indium tin zinc oxide, and indium gallium tin oxide.

[0190] Step S204, sequentially forming a reading electrode, a photoelectric conversion structure, and a conductive electrode on the side of the sacrificial layer away from the substrate substrate.

[0191] Referring to Figure 16d As shown, the reading electrode 201, the photoelectric conversion structure 202, and the conductive electrode 203 within each detection pixel unit Pix constitute the photoelectric conversion part 2. Among them, the orthographic projection of the channel region 30 on the substrate substrate 1 does not overlap with the orthographic projection of the photoelectric conversion part 3 on the substrate substrate 1. That is, there is no part in the photoelectric conversion part 3 located directly above the channel part.

[0192] In some embodiments, the material of the reading electrode 201 can be a metal material, such as at least one of copper, aluminum, and titanium. The material of the conductive electrode 203 can be a transparent metal oxide, such as at least one of indium tin oxide, indium zinc oxide, and gallium zinc oxide.

[0193] Step S205, forming a third passivation layer.

[0194] Referring to Figure 16e As shown, in some embodiments, the orthographic projection of the third passivation layer 15 on the substrate substrate 1 can completely cover the orthographic projection of the channel region 30 on the substrate substrate 1. The material of the third passivation layer 15 can adopt silicon oxide.

[0195] Step S206, sequentially forming a buffer layer, a second organic layer, and a fourth passivation layer on the side of the third passivation layer away from the substrate substrate.

[0196] Referring to Figure 16fAs shown, the first via hole 6 is formed on the buffer layer 11, the second organic layer 5 and the fourth passivation layer 12, and the at least partial orthographic projection of the channel region 30 on the substrate 1 is located within the orthographic projection of the first via hole 6 on the substrate 1. In addition, the third via hole 17 is formed on the buffer layer 11, the second organic layer 5 and the fourth passivation layer 12, and is connected to the conductive electrode 203.

[0197] The material of the buffer layer 11 and the fourth passivation layer 12 can be silicon nitride, and the material of the second organic layer 5 can be an organic resin material such as polyacrylic resin, polyepoxyacrylic resin, polyester acrylate, polyurethane acrylate resin, etc.

[0198] In step S207, a bias voltage line is formed on the side of the fourth passivation layer away from the substrate.

[0199] Referring to Figure 16g As shown, the bias voltage line 4 is connected to the corresponding conductive electrode 203 through the corresponding third via hole 17.

[0200] It should be noted that in some embodiments, the orthographic projection of the bias voltage line 4 on the substrate 1 completely covers the orthographic projection of the channel region 30 on the substrate 1, and part of the bias voltage line 4 is located within the first via hole 6. However, due to the presence of the third passivation layer 15, the part of the bias voltage line 4 located within the first via hole 6 will not be in contact with the sacrificial layer 10.

[0201] In step S208, a fifth passivation layer and a third organic layer are sequentially formed on the side of the bias voltage line away from the substrate.

[0202] Referring to Figure 6 As shown, the material of the fifth passivation layer 13 can be silicon nitride. The material of the third organic layer 14 can be an organic resin material such as polyacrylic resin, polyepoxyacrylic resin, polyester acrylate, polyurethane acrylate resin, etc.

[0203] Figure 17 Another preparation method flow chart of a detection substrate provided by the embodiments of the present disclosure; Figures 18a-18f The preparation method provided by the embodiments of the present disclosure can be used to prepare a detection substrate having Figure 17 As shown, the preparation method can be used to prepare a detection substrate having Figure 12 The preparation method includes:

[0204] In step S301, a plurality of gate lines, a plurality of signal reading lines and a plurality of thin film transistors are formed on an array substrate.

[0205] As shown, compared with the second electrode 304 of the thin film transistor shown in Figure 18a Figure 16a As shown, compared with the second electrode 304 of the thin film transistor shown in Figure 18a ​The second electrode 304 of the thin film transistor shown in FIG. 1 has a larger size. In this case, Figure 18a The second electrode 304 shown in FIG. 1 can adopt Figure 13 The case shown in FIG. 1.

[0206] Step S302, sequentially forming a first passivation layer, a first organic layer and a second passivation layer on the side of the thin film transistor away from the substrate.

[0207] Referring to Figure 18b As shown in FIG. 2, a second via hole 16 is formed on the first passivation layer 7, the first organic layer 8 and the second passivation layer 9, and is connected to the second electrode 304 of the thin film transistor 3. In this case, Figure 18b The position of the second via hole 16 shown in FIG. 2 can adopt Figure 12 The case shown in FIG. 2.

[0208] Step S303, forming a sacrificial layer on the side of the second passivation layer away from the substrate.

[0209] Referring to Figure 18c As shown in FIG. 3, at least part of the orthographic projection of the channel region 30 on the substrate 1 is located within the orthographic projection of the sacrificial layer 10 on the substrate 1.

[0210] In some embodiments, the orthographic projection of the sacrificial layer 10 on the substrate 1 does not overlap or partially overlaps with the orthographic projection of the second via hole 16 on the substrate 1, and the sacrificial layer 10 does not contact the second electrode 304.

[0211] Step S304, sequentially forming a reading electrode, a photoelectric conversion structure and a conductive electrode on the side of the sacrificial layer away from the substrate.

[0212] Referring to Figure 18d As shown in FIG. 4, the reading electrode 201, the photoelectric conversion structure 202 and the conductive electrode 203 in each detection pixel unit Pix constitute a photoelectric conversion part 2. In this case, the orthographic projection of the channel region 30 on the substrate 1 is located within the orthographic projection of the photoelectric conversion part 2 on the substrate 1; that is, the orthographic projection of the photoelectric conversion part 2 on the substrate 1 completely covers the channel region 30.

[0213] Step S305, sequentially forming a buffer layer, a second organic layer and a fourth passivation layer on the side of the conductive electrode away from the substrate.

[0214] Referring to Figure 18eAs shown, the first via hole 6 is formed on the buffer layer 11, the second organic layer 5 and the fourth passivation layer 12, and at least part of the orthogonal projection of the channel region 30 on the substrate 1 is located within the orthogonal projection of the first via hole 6 on the substrate 1. In this embodiment, the first via hole 6 can also be used as a via hole for connecting the bias voltage line 4 with the conductive electrode 203 in the photoelectric conversion part 2 (i.e., the first via hole 6 and the third via hole 17 in the above embodiment are the same via hole).

[0215] In step S306, the bias voltage line is formed on the side of the fourth passivation layer away from the substrate.

[0216] Referring to Figure 18f As shown, the bias voltage line 4 is connected with the corresponding conductive electrode 203 through the corresponding first via hole 6 (also the third via hole 17).

[0217] It should be noted that in some embodiments, the orthogonal projection of the bias voltage line 4 on the substrate 1 completely covers the orthogonal projection of the channel region 30 on the substrate 1.

[0218] In step S307, the fifth passivation layer and the third organic layer are sequentially formed on the side of the bias voltage line away from the substrate.

[0219] Referring to Figure 12 As shown, the fifth passivation layer 13 and the third organic layer 14 can play a role of encapsulating the detection substrate.

[0220] It should be understood that the above embodiments are only exemplary embodiments adopted for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also considered as the protection scope of the present disclosure.

Claims

1. A probe card, comprising: a substrate; a plurality of probes extending from the substrate, wherein, The application relates to a substrate, a plurality of detection pixel units arranged in an array on the substrate, the detection pixel unit comprising a thin film transistor and a photoelectric conversion part on the side of the thin film transistor away from the substrate, and a bias voltage line arranged on the side of the photoelectric conversion part away from the substrate. The thin film transistor comprises an active layer, a first electrode and a second electrode, the first electrode and the second electrode are electrically connected with the active layer, and the active layer comprises a channel region. The photoelectric conversion part is electrically connected with the second electrode at one end close to the substrate, and is electrically connected with the corresponding bias voltage line at the other end away from the substrate. At least one dielectric layer is arranged between the photoelectric conversion part and the bias voltage line, a first through hole is formed on the dielectric layer, the bias voltage line covers the bottom and the sidewall of the first through hole, and the bias voltage line and the thin film transistor are insulated from each other; at least part of the projection of the channel region on the substrate is located within the projection of the first through hole on the substrate. The detection pixel unit further comprises a sacrificial layer between the thin film transistor and the photoelectric conversion part, at least part of the projection of the channel region on the substrate is located within the projection of the sacrificial layer on the substrate, and the material of the sacrificial layer comprises metal oxide. A third passivation layer is arranged between the sacrificial layer and the bias voltage line; the projection of the first through hole on the substrate is located within the projection of the third passivation layer on the substrate. The photoelectric conversion part comprises a reading electrode and a photoelectric conversion structure, the photoelectric conversion structure is located on the side of the reading electrode away from the substrate; the boundary of the projection of the reading electrode on the substrate is located within the boundary of the projection of the sacrificial layer on the substrate. The projection of the channel region on the substrate is located within the projection of the first through hole on the substrate. The at least one dielectric layer comprises a second organic layer.

2. The probe substrate of claim 1, wherein, The at least one dielectric layer further comprises a buffer layer between the second organic layer and the photoelectric conversion part, and / or a fourth passivation layer between the second organic layer and the bias voltage line.

3. The probe substrate of claim 1, wherein, A third through hole is formed on the dielectric layer and communicates with the end of the photoelectric conversion part away from the substrate, and the bias voltage line contacts the end of the corresponding photoelectric conversion part away from the substrate through the corresponding third through hole.

4. The probe substrate of claim 3, wherein, The projection of the channel region on the substrate does not overlap with the projection of the photoelectric conversion part on the substrate. The material of the reading electrode comprises a metal material. The projection of the layer structure where the reading electrode is located on the substrate does not overlap with the projection of the channel region on the substrate.

5. The probe substrate according to any one of claims 1 to 4, wherein, The projection of the channel region on the substrate is located within the projection of the bias voltage line on the substrate, and the material of the bias voltage line comprises a metal material.

6. The probe substrate of claim 5, wherein, ​ 7. The probe substrate as claimed in claim 6, wherein, ​ ​ 8. The probe substrate of claim 6, wherein, ​ 9. The probe substrate of claim 5, wherein, A projection of the channel region on the substrate substrate is within a projection of the photoelectric conversion unit on the substrate substrate.

10. The probe substrate of claim 9, wherein, The first via and the third via are the same via.

11. The probe substrate of claim 9, wherein, The material of the bias voltage line comprises a transparent conductive material.

12. The probe substrate of claim 1, wherein, The sacrificial layer is in contact with an end of the photoelectric conversion unit close to the substrate substrate, and the sacrificial layers in different detection pixel units are insulated from each other.

13. The probe card of claim 12, wherein, A projection of the channel region on the substrate substrate does not overlap with a projection of the photoelectric conversion unit on the substrate substrate.

14. The probe card of claim 13, wherein, The at least one medium layer comprises a second organic layer, a buffer layer and a fourth passivation layer. The density of the third passivation layer is less than the density of the buffer layer, and the density of the third passivation layer is less than the density of the fourth passivation layer.

15. The probe card of claim 14, wherein, The material of the third passivation layer comprises silicon oxide, the material of the buffer layer comprises silicon nitride, and the material of the fourth passivation layer comprises silicon nitride.

16. The probe substrate of claim 1, wherein, The thin film transistor and the photoelectric conversion unit further comprise a first passivation layer, a first organic layer and a second passivation layer, the first organic layer is located on a side of the first passivation layer away from the substrate substrate, and the second passivation layer is located on a side of the first organic layer away from the substrate substrate. The sacrificial layer is located between the second passivation layer and the photoelectric conversion unit.

17. The probe card of claim 16, wherein, The first passivation layer, the first organic layer and the second passivation layer are formed with a second via which communicates with the second electrode. The reading electrode is in contact with the second electrode through the second via, and the sacrificial layer is not in contact with the second electrode.

18. The probe card of claim 17, wherein, The projection of the sacrificial layer on the substrate substrate does not overlap with the projection of the second via on the substrate substrate.

19. The probe card of claim 17, wherein, The projection of the photoelectric conversion structure on the substrate substrate does not overlap with the projection of the second via on the substrate substrate.

20. The probe card of claim 17, wherein, The boundary of the projection of the photoelectric conversion structure on the substrate substrate is within the boundary of the projection of the reading electrode on the substrate substrate.

21. The probe card of claim 1, wherein, The thin film transistor and the photoelectric conversion unit further comprise a first passivation layer, a first organic layer and a second passivation layer, the first organic layer is located on a side of the first passivation layer away from the substrate substrate, and the second passivation layer is located on a side of the first organic layer away from the substrate substrate. The sacrificial layer is located between the first passivation layer and the first organic layer. Alternatively, the sacrificial layer is located between the first organic layer and the second passivation layer.

22. The probe card of claim 16, wherein, The material of the first passivation layer comprises silicon oxide, and the material of the second passivation layer comprises silicon oxide.

23. The probe card of claim 1, wherein, The projection of the channel region on the substrate substrate is within the projection of the sacrificial layer on the substrate substrate.

24. The probe card of claim 1, wherein, Further comprising: A plurality of gate lines arranged along a first direction and a plurality of signal reading lines arranged along a second direction, the gate lines extend along the second direction, and the signal reading lines extend along the first direction. The thin film transistor further comprises a gate electrode, and the gate electrode is electrically connected with the corresponding gate line. The second electrode is electrically connected with the corresponding signal reading line.

25. The probe card of claim 24, wherein, The detecting pixel unit includes a sacrifice layer, a projection of the sacrifice layer on the substrate is not overlapped with a projection of the gate line on the substrate, and a projection of the sacrifice layer on the substrate is not overlapped with a projection of the signal reading line on the substrate.

26. The probe card of claim 25, wherein, The sacrifice layer includes a first part and a second part connected to each other, and the first part protrudes from the second part. A line width of a part of the signal reading line close to the first part is smaller than a line width of a part of the signal reading line close to the second part, and a line width of a part of the gate line close to the first part is smaller than a line width of a part of the gate line close to the second part.

27. The probe card of claim 24, wherein, The second electrode includes a first conductive part for connecting to the active layer, a second conductive part for connecting to a part of the photoelectric conversion part close to the substrate, and a third conductive part connecting the first conductive part and the second conductive part, and the third conductive part is located between the first conductive part and the second conductive part. The first conductive part and the second conductive part are both extended along the second direction. A distance between a side edge of the first conductive part away from the gate line and the gate line is greater than a distance between a side edge of the second conductive part away from the gate line and the gate line.

28. The probe card of claim 27, wherein, The third conductive part includes a first connecting part connected to the first conductive part, a second connecting part connected to the second conductive part, and a third connecting part connecting the first connecting part and the second connecting part, and the third connecting part is located between the first connecting part and the second connecting part. The first connecting part is extended along the second direction, and a side edge of the first connecting part away from the gate line is located on a same straight line as a side edge of the first conductive part away from the gate line. The second connecting part is extended along the second direction, and a side edge of the second connecting part away from the gate line is located on a same straight line as a side edge of the second conductive part away from the gate line. An extension direction of the third connecting part intersects the second direction.

29. The probe card of claim 24, wherein, The gate electrode includes a main body part and a fourth connecting part connected to the main body part, and the fourth connecting part is in contact with a corresponding gate line. A width of the fourth connecting part in the second direction is greater than a width of the main body part in the second direction.

30. The probe card of claim 29, wherein, In a direction from the fourth connecting part to the main body part, the width of the fourth connecting part in the second direction gradually decreases.

31. The probe substrate of claim 1, wherein, Further comprising: A fifth passivation layer located on a side of the bias voltage line away from the substrate; A third organic layer located on a side of the fifth passivation layer away from the substrate.

32. A flat panel detector, wherein, A detecting substrate as claimed in any one of claims 1-31.

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