Current detection device and method, low voltage difference linear regulator and electronic equipment

Abstract

The present application relates to a current detection device and method thereof, a low-voltage difference linear regulator and an electronic device, and belongs to the field of electronic circuit technology. The current detection device includes: a current sampling circuit, a current detection circuit; the current sampling circuit is used to sample the load current and obtain a target sampling current; the current detection circuit is connected to the current sampling circuit, and the current detection circuit is used to detect the number of oscillation cycles of the oscillation signal generated by the target sampling current within a specified time; wherein the number of oscillation cycles is used to characterize the size of the target sampling current. The present application is based on the principle of TDC (Time Digital Converter) to convert the detected target sampling current into the number of detected oscillation cycles (Counter), thereby realizing current detection. It can realize current detection without the need for off-chip resistors and ADC, and has the advantages of small area and fast response time.

Description

Technical Field

[0001] The present application belongs to the field of electronic circuit technology, and specifically relates to a current detection device and method thereof, a low voltage difference linear regulator and an electronic device. Background Art

[0002] With the development of chips, chiplet technology is increasingly used in SOC (System On Chip, also known as system on chip) chips. For example, in CPU (Central Processing Unit) applications, multiple chiplets are connected on the substrate through high-speed interconnection 0PHY chips to meet the application needs of various large servers.

[0003] High-current loads such as L3 cache, DDR (Double Data Rate), PCIE (Peripheral Component Interconnect Express) interfaces, and interconnect PHYs are often powered by on-chip LDOs (Low Dropout Voltage regulators) to achieve independent voltage regulation and noise isolation.

[0004] In the CPU power consumption prediction system, it is necessary to detect the current of each large current load. Existing current detection circuits based on LDO, such as Figure 1 As shown, it includes LDO, current mirror unit and current detection unit. LDO and mirror unit are used to accurately mirror the output current Iout to obtain

[0005] The mirror current Isense is then injected into the current detection unit, and the current is converted to voltage using resistor 0, and finally the high-precision ADC (Analog Digital Converter,

[0006] Analog-to-digital converter) completes voltage detection.

[0007] However, this detection solution requires additional off-chip resistors to complete the current-to-voltage conversion, which will occupy the wiring resources of the substrate; and requires a high-precision ADC, which will result in a larger chip area and longer response time. Summary of the Invention

[0008] In view of this, the purpose of the present application is to provide a current detection device and method thereof, a low-voltage difference linear regulator and an electronic device to improve the problem that the existing current detection device requires additional off-chip resistors to complete the current-to-voltage conversion, which occupies the wiring resources of the substrate, and requires a high-precision ADC, resulting in a larger chip area and a longer response time.

[0009] The embodiment of the present application is implemented as follows:

[0010] In a first aspect, an embodiment of the present application provides a current detection device, comprising: a current sampling circuit and a current detection circuit; the current sampling circuit is used to sample the load current to obtain a target sampling current; the current detection circuit is connected to the current sampling circuit, and the current detection circuit is used to detect the number of oscillation cycles of an oscillation signal generated by the target sampling current within a specified time; wherein the number of oscillation cycles is used to characterize the magnitude of the target sampling current.

[0011] In the embodiment of the present application, based on the TDC (Time Digital Converter) principle, the detection target sampling current is converted into the detection oscillation cycle number (Counter), thereby realizing current detection. The current detection can be realized without the need for off-chip resistors and ADC, and has the advantages of small area and fast response time.

[0012] In combination with a possible implementation manner of the embodiment of the first aspect, the current detection circuit includes: an N-stage differential ring oscillator, a first counter, a second counter and a decoder; the N-stage differential ring oscillator is used to generate N oscillation signals based on the target sampling current, N is a positive integer greater than or equal to 2, and each of the oscillation signals includes two differential signals with a phase difference of 90 degrees; the first counter is used to count the number of times a specified edge appears in any of the N oscillation signals within the specified time, so as to obtain an integer multiple of the oscillation period within the specified time; the second counter is used to count the phase states of the N oscillation signals detected within the specified time, so as to obtain a fractional multiple of the oscillation period other than the integer multiple of the oscillation period counted by the first counter; the decoder is used to obtain all oscillation periods within the specified time based on the counting results of the first counter and the second counter.

[0013] In an embodiment of the present application, an N-stage differential ring oscillator is used to generate N oscillation signals based on the target sampling current, and a first counter is used to obtain the integer multiple oscillation period number of the oscillation signal within a specified time, and a second counter obtains the fractional multiple oscillation period number other than the integer multiple oscillation period number counted by the first counter. Finally, a decoder is used to obtain all the oscillation period numbers within the specified time, thereby realizing the conversion of the detected target sampling current into the detected oscillation period number (Counter).

[0014] In combination with a possible implementation of the embodiment of the first aspect, the current detection circuit further includes: a pulse width generator, configured to generate a counting pulse, and the specified time is the time between two adjacent falling edges of the counting pulse.

[0015] In the embodiment of the present application, a pulse width generator is added to the current detection circuit to generate a counting pulse, thereby obtaining a specified time without the need to apply an additional specified time.

[0016] In combination with a possible implementation manner of the embodiment of the first aspect, the current detection device further includes: a current control circuit, connected to the current sampling circuit, for controlling the magnitude of the target sampling current sampled by the current sampling circuit according to the voltage corresponding to the target sampling current, so as to limit the voltage corresponding to the target sampling current to a specified range after adjustment to meet the range requirement of the current detection circuit.

[0017] In the embodiment of the present application, a current control circuit is added to adjust the magnitude of the target sampling current sampled by the current sampling circuit to meet the range requirement of the current detection circuit.

[0018] In combination with a possible implementation manner of the embodiment of the first aspect, the current control circuit includes: a first comparator, a second comparator and a controller; the first comparator is used to compare the voltage corresponding to the target sampling current with a first reference voltage to obtain a first comparison result; the second comparator is used to compare the voltage corresponding to the target sampling current with a second reference voltage to obtain a second comparison result, and the second reference voltage is greater than the first reference voltage; the controller is used to adjust the sampling ratio of the current sampling circuit according to the first comparison result and the second comparison result, so as to limit the adjusted voltage corresponding to the target sampling current to between the first reference voltage and the second reference voltage to meet the range requirement of the current detection circuit.

[0019] In the embodiment of the present application, two comparators are used to compare the voltage corresponding to the target sampling current with two reference voltages, and the magnitude of the target sampling current is adjusted according to the respective comparison results, so that the voltage corresponding to the adjusted target sampling current can be accurately and quickly limited between the first reference voltage and the second reference voltage to meet the range requirements of the current detection circuit.

[0020] In combination with a possible implementation manner of the embodiment of the first aspect, the current sampling circuit includes: N controllable current sampling units connected in parallel, the first ends of each controllable current sampling unit are connected together for connecting to a power supply, the second ends of each controllable current sampling unit are connected together and connected to the current detection circuit, and N is a positive integer greater than or equal to 2; each controllable current sampling unit has two states: working and standby. When in the working state, it is used to sample the load current to obtain a sampled current, and the target sampled current is the sum of the sampled currents of all controllable current sampling units in the working state; accordingly, the current control circuit adjusts the magnitude of the target sampled current by controlling the number of controllable current sampling units in the working state.

[0021] In the embodiment of the present application, the target sampling current is adjusted by controlling the number of controllable current sampling units in a working state, so that the target sampling current can be adjusted quickly.

[0022] In combination with a possible implementation of the embodiment of the first aspect, the sampling ratio of each controllable current sampling unit is different, and the N sampling ratios form a geometric progression with a common ratio of 2 or 1 / 2.

[0023] In the embodiment of the present application, the current sampling circuit adopting this method can save the circuit speed of the controllable current sampling unit, thereby reducing the area of ​​the circuit.

[0024] In combination with a possible implementation manner of the embodiment of the first aspect, the current sampling circuit further includes: a first fixed current sampling unit, a first current mirror unit, and a second fixed current sampling unit, wherein the second fixed current sampling unit and the first fixed current sampling unit are both connected to the first current mirror unit; the first fixed current sampling unit is configured to sample the load current to obtain an initial sampling current; the first current mirror unit is configured to mirror the initial sampling current to the second fixed current sampling unit; the second fixed current sampling unit is configured to perform a 1:1 sampling of the initial sampling current to obtain the initial sampling current; accordingly, when each controllable current sampling unit is in an operating state, is configured to sample the initial sampling current output by the second fixed current sampling unit to obtain a sampling current.

[0025] In the embodiment of the present application, by adding a first fixed current sampling unit, a first current mirror unit and a second fixed current sampling unit, the current detection device can operate at a larger VRO voltage (the voltage corresponding to the target sampling current), that is, corresponding to a larger current detection range, so as to be applicable to more complex current detection scenarios.

[0026] In a second aspect, an embodiment of the present application further provides a low voltage difference linear regulator, comprising: a current detection device as provided in the above-mentioned embodiment of the first aspect and / or any possible implementation method in combination with the embodiment of the first aspect.

[0027] In a third aspect, an embodiment of the present application further provides an electronic device comprising: a load and a current detection device as provided in the above-mentioned first aspect embodiment and / or any possible implementation method in combination with the first aspect embodiment, wherein the current detection device is used to detect the load current of the load.

[0028] In a fourth aspect, an embodiment of the present application also provides a current detection method, comprising: sampling a load current to obtain a target sampling current; generating an oscillation signal based on the target sampling current; detecting the number of oscillation cycles of the oscillation signal within a specified time; wherein the number of oscillation cycles is used to characterize the magnitude of the target sampling current.

[0029] In combination with a possible implementation manner of the fourth aspect, an oscillation signal is generated based on the target sampling current, including: generating N oscillation signals based on the target sampling current, where N is a positive integer greater than or equal to 2, and each of the oscillation signals includes two differential signals with a phase difference of 90 degrees; accordingly, detecting the number of oscillation cycles of the oscillation signal within a specified time, including: counting the number of times a specified edge appears in any one of the N oscillation signals within the specified time to obtain an integer multiple of the oscillation cycle number within the specified time; counting the phase states of the N oscillation signals detected within the specified time to obtain a fractional multiple of the oscillation cycle number other than the integer multiple of the oscillation cycle number; and obtaining all oscillation cycles within the specified time based on the integer multiple of the oscillation cycle number and the fractional multiple of the oscillation cycle number.

[0030] In combination with a possible implementation manner of the fourth aspect, the specified time is the time between two adjacent falling edges in the counting pulse.

[0031] In conjunction with a possible implementation of the fourth aspect, the method further includes:

[0032] According to the voltage corresponding to the target sampling current, a sampling ratio of the target sampling current is adjusted to limit the adjusted voltage corresponding to the target sampling current to within a specified range.

[0033] In combination with a possible implementation manner of the fourth aspect, adjusting the sampling ratio of the target sampling current includes: comparing the voltage corresponding to the target sampling current with a first reference voltage to obtain a first comparison result; comparing the voltage corresponding to the target sampling current with a second reference voltage to obtain a second comparison result, the second reference voltage being greater than the first reference voltage; and adjusting the sampling ratio based on the first comparison result and the second comparison result to limit the adjusted voltage corresponding to the target sampling current to between the first reference voltage and the second reference voltage.

[0034] Other features and advantages of the present application will be described in the following description. The purpose and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. The above and other purposes, features and advantages of the present application will be more clearly shown in the accompanying drawings. The same reference numerals indicate the same parts throughout the drawings. The drawings are not intentionally scaled to actual size, and the focus is on illustrating the main purpose of the present application.

[0036] Figure 1 The schematic diagram of the existing LDO-based current detection circuit is shown in FIG.

[0037] Figure 2 A module schematic diagram of a first current detection device provided in an embodiment of the present application is shown.

[0038] Figure 3 A module schematic diagram of a second current detection device provided in an embodiment of the present application is shown.

[0039] Figure 4 A schematic diagram of a fitting curve of the oscillation period number Counter and the current Imonitor provided in an embodiment of the present application is shown.

[0040] Figure 5 A timing diagram of the detection principle of a current detection circuit provided in an embodiment of the present application is shown.

[0041] Figure 6 A circuit diagram showing the connection between the first current detection device provided by an embodiment of the present application and an LDO unit is shown.

[0042] Figure 7 A circuit diagram showing the connection between the second current detection device provided by an embodiment of the present application and an LDO unit is shown.

[0043] Figure 8 A circuit diagram showing the connection between the third current detection device provided by an embodiment of the present application and an LDO unit is shown.

[0044] Figure 9 A module schematic diagram of a third current detection device provided in an embodiment of the present application is shown.

[0045] Figure 10 A circuit diagram showing the connection between the fourth current detection device provided by an embodiment of the present application and an LDO unit is shown.

[0046] Figure 11 A circuit diagram showing the connection between a current sampling circuit, a current control power supply, and an LDO unit provided in an embodiment of the present application is shown.

[0047] Figure 12 A timing diagram of a current detection device provided in an embodiment of the present application is shown.

[0048] Figure 13 A flow chart of a current detection method provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0050] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in the subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, article or equipment. In the absence of more restrictions, the elements limited by the statement "comprise a..." do not exclude the presence of other identical elements in the process, article or equipment including the elements.

[0051] In view of the existing current detection circuit (such as Figure 1As shown in the figure, additional off-chip resistors and ADC are required, which leads to the problem that the chip area becomes larger and the response time becomes longer. The embodiment of the present application provides a new current detection device, which is based on the TDC (Time Digital Converter) principle, completes the conversion of current to oscillation cycle number (such as represented by Counter), and realizes current detection by detecting Counter. Current detection can be realized without off-chip resistors and ADC, and has the advantages of small area and fast response time.

[0052] The following will be combined Figure 2 , the principle of the current detection device provided by the embodiment of the present application is described. The current detection device includes: a current sampling circuit and a current detection circuit, and the current detection circuit is connected to the current sampling circuit.

[0053] The current sampling circuit is used to sample the load current to obtain the target sampling current. The current detection circuit is used to detect the number of oscillation cycles of the oscillation signal generated by the target sampling current within a specified time, wherein the number of oscillation cycles represents the magnitude of the target sampling current.

[0054] In the embodiment of the present application, after obtaining the target sampled current, the current is not detected by converting it into a voltage using a resistor and then detecting it using an ADC. Instead, the current is detected by detecting the number of oscillation cycles of the oscillation signal generated by the target sampled current within a specified time. For example, after obtaining the number of oscillation cycles, the corresponding current magnitude can be obtained based on a pre-set correspondence between the number of oscillation cycles and the current.

[0055] The current detection circuit includes a current sensor (Current Monitor), in one embodiment, as Figure 3 As shown, the current detection circuit includes: an N-stage differential ring oscillator, a first counter, a first

[0056] The N-stage differential ring oscillator is connected to the first counter and the second counter. At the same time, the first counter and the second counter are also connected to the decoder respectively.

[0057] An N-stage differential ring oscillator generates N oscillating signals based on the target sampling current. The frequency of the oscillating signals varies with the target sampling current. N is a positive integer greater than or equal to 2. Each oscillating signal consists of two differential signals (e.g., r and rb) with a 90-degree phase difference. This means that one differential signal consists of both the r and rb signals.

[0058] 0 Among them, the N-stage differential ring oscillator can be a current-controlled differential ring oscillator (ICO, I corresponds to Current), and the N-stage differential ring oscillator includes 2N inverters connected end to end. For a better understanding, taking a 16-stage differential ring oscillator as an example, it includes 32 inverters connected end to end, which will generate 16 oscillation signals, and each oscillation signal

[0059] The signal contains two differential signals with a phase difference of 90 degrees, so the 16 oscillation signals can be represented by r<15:0> and rb<15:0>. It is understood that N is not limited to 16, and it can be greater than or equal to 16.

[0060] The larger the value of N is, the higher the accuracy is.

[0061] The first counter is used to count the number of times a specified edge appears in a specified time period for any one of the N oscillation signals, such as the oscillation signals r15 and rb15 (assuming A,

[0062] is an integer) to obtain the integer multiple oscillation cycles (A*T, T cycle) within the specified time. Among them, 0 specifies that the edge can be a rising edge or a falling edge. The first counter counts the oscillations of r15 and rb15.

[0063] When counting the number of times a specified edge appears in a specified time for a differential signal, the number of times a specified edge appears in a specified time for either R15 or RB15 can be counted.

[0064] The second counter is used to count the phase states of N oscillation signals detected within a specified time.

[0065] In order to obtain the fractional multiple oscillation period 5 number in addition to the integer multiple oscillation period number counted by the first counter. Taking N as 16 as an example, the second counter can count how many of the 32 differential signals are

[0066] The phase state of N oscillator signals is determined by the occurrence of a specified edge in the differential signal within a specified time. For example, if B (an integer ranging from 0 to 32) differential signals have a specified edge within a specified time, the phase state is B / 32. Correspondingly, the fractional oscillation period number is (B / 32)*T.

[0067] The decoder is used to calculate the total number of oscillation cycles within a specified time period based on the count results of the first and second counters. For example, the total number of oscillation cycles within a specified time period can be calculated based on A*T and (B / 32)*T. For example, the count results of the first and second counters can be multiplied by 32 and added together to obtain (32A+B)*T. Finally, (32A+B) is converted into a code Counter output in a specified base (e.g., base 16).

[0068] After obtaining the counter value representing the number of oscillation cycles output by the current detection circuit, the target sampling current can be determined based on the relationship between the counter value and the actual detection current. Figure 4 As shown, based on the fitting curve, we can obtain: Imonitor = f(Counter). By testing a large number of Counter values ​​and detection currents (which are known values) in advance, we can fit the relationship between the Counter value and the actual detection current Imonitor. Then, when detecting current, we only need to obtain the Counter value output by the current detection circuit to determine the magnitude of the current to be detected Imonitor based on this fitting relationship.

[0069] In an optional embodiment, the current detection circuit further includes a pulse width generator for generating a count pulse. The time between two adjacent falling edges in the count pulse is the specified time, i.e., the time of the counting phase of the first counter and the second counter. The specified time can also be regarded as the time interval between the two pulses. The pulse width generator is respectively connected to the N-stage differential ring oscillator, the first counter, and the second counter. This allows the first counter and the second counter to count according to the count pulse. The N-stage differential ring oscillator is also used to initialize according to the count pulse. The initialization time is the time between adjacent rising and falling edges in the count pulse, i.e., the time of the reset phase.

[0070] For a better understanding, the following Figure 5 CLK_ICO can be any differential signal among the 2N differential signals generated by the N-stage differential ring oscillator, the time corresponding to T3 is the above-mentioned specified time, and the time corresponding to T2 is the time for ICO initialization.

[0071] In one embodiment, the current sampling circuit may be an existing current sampling circuit, for example, comprising only a fixed current sampling unit for sampling the load current, as shown in the schematic diagram. Figure 6 shown.

[0072] In another embodiment, a new current sampling circuit may be used. The current sampling circuit includes a fixed current sampling unit, a first current mirror unit, and a second current mirror unit. The second current mirror unit and the fixed current sampling unit are both connected to the first current mirror unit.

[0073] The fixed current sampling unit is used to sample the load current to obtain an initial sampled current. Optionally, the fixed current sampling unit can sample the load current in an M:1 ratio to obtain the initial sampled current. If the load current is represented by Iload, then the initial sampled current = Iload / M, where M is a positive integer greater than or equal to 1.

[0074] The first current mirror unit is used to mirror the initial sampling current to the second current mirror unit. Optionally, the first current mirror unit can mirror the initial sampling current to the second current mirror unit in a 1:1 ratio.

[0075] The second current mirror unit is used to perform a 1:1 mirroring on the initial sampling current to obtain the initial sampling current, and output the initial sampling current to the current detection circuit.

[0076] In one embodiment, the circuit schematic diagram of the new current sampling circuit is as follows: Figure 7 As shown, op2 is used to clamp the drain potential of MP2 to Vout in order to accurately sample the load current. It can be understood that in one way, it is also possible to remove Figure 7 The sampling accuracy will be reduced when the op2 and MP0 tubes are used. The initial sampling current is transmitted by the MN0 to MN4 tubes. The initial sampling transmitted by the MN0 to MN4 tubes is mirrored by the second current mirror unit to output the initial sampling current. Figure 7 The MP5 and MP6 tubes in the circuit are in a normally closed state, that is, a conducting state, under the control of the Vpb1 signal.

[0077] In another embodiment, the circuit schematic diagram of the current sampling circuit is as follows: Figure 8 As shown. Figure 7 The main difference is that the first current mirror unit is different. Figure 8 The MN2 and MN3 tubes in the circuit are in a normally closed state, that is, a conducting state, under the control of the Vbn1 signal.

[0078] In an optional embodiment, the current detection device also includes a current control circuit, which is connected to the current sampling circuit and is used to control the magnitude of the target sampling current sampled by the current sampling circuit according to the voltage corresponding to the target sampling current, so as to limit the voltage corresponding to the adjusted target sampling current to a specified range, such as between two reference voltages, to meet the range requirements of the current detection circuit.

[0079] Optionally, the current control circuit may include a first comparator, a second comparator and a controller, such as Figure 9 As shown, the first comparator and the second comparator are both connected to the output end of the current sampling circuit, and are also connected to the controller.

[0080] The first comparator is configured to compare the voltage corresponding to the target sampling current with a first reference voltage (e.g., represented by VREF1) to obtain a first comparison result (e.g., represented by UP). The first comparison result is either a high level or a low level. For example, when the voltage corresponding to the target sampling current is greater than or equal to the first reference voltage, the first comparison result is a high level, otherwise it is a low level.

[0081] The second comparator is configured to compare the voltage corresponding to the target sampling current with a second reference voltage (e.g., represented by VREF2) to obtain a second comparison result (e.g., represented by DOWN), wherein the second reference voltage is greater than the first reference voltage. The second comparison result is either a high level or a low level. For example, when the voltage corresponding to the target sampling current is greater than the second reference voltage, the second comparison result is a low level, otherwise, the second comparison result is a high level.

[0082] The controller is configured to adjust a sampling ratio of the current sampling circuit based on the first comparison result and the second comparison result, so as to limit the voltage corresponding to the adjusted target sampling current to between the first reference voltage and the second reference voltage, thereby meeting the range requirement of the current detection circuit. Specifically, the controller may count the number of high levels in the first comparison result over a period of time to obtain a first count value, count the number of high levels in the first comparison result to obtain a second count value, and adjust the sampling ratio of the current sampling circuit based on the difference between the first count value and the second count value, so as to limit the voltage corresponding to the target sampling current to between the first reference voltage and the second reference voltage, thereby meeting the range requirement of the current detection circuit.

[0083] When the difference between the first count value and the second count value is 0, it indicates that the voltage corresponding to the target sampling current is between the first reference voltage and the second reference voltage. At this time, the target sampling current sampled by the current sampling circuit should be kept unchanged. If the difference between the first count value and the second count value is greater than 0, it indicates that the voltage corresponding to the target sampling current is greater than the second reference voltage more often. The target sampling current sampled by the current sampling circuit should be reduced. If the difference between the first count value and the second count value is large,

[0084] If it is less than 0, it indicates that the voltage corresponding to the target sampling current is often less than the second reference voltage, and the target sampling current sampled by the current sampling circuit should be increased.

[0085] In one optional embodiment, the controller can be an up-down counter (UP DOWN Counter), and in another embodiment, the controller can be an integrated circuit chip with signal processing capabilities. The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor can be a microprocessor or the controller can also be any conventional processor, etc.

[0086] 5 It is understood that the current sampling circuit of the current detection device when it includes a current control circuit

[0087] The schematic diagram is different from the schematic diagram of the current sampling circuit of the current detection device when the current control circuit is not included.

[0088] When the current detection device further includes a current control circuit, in an optional embodiment, the current

[0089] The sampling circuit includes: N controllable current sampling units connected in parallel, the first end of each controllable current sampling unit 0 is connected together for connecting to a power supply, and the second end of each controllable current sampling unit

[0090] They are all connected together and connected to the current detection circuit, and N is a positive integer greater than or equal to 2.

[0091] Each controllable current sampling unit has two states: working and standby. When in working state, it is used to sample the load current and obtain the sampling current. The target sampling current is the current of all the controllable current sampling units.

[0092] The sum of the sampling currents of the controllable current sampling units in the working state. Accordingly, the current control circuit adjusts the size of the target sampling current by controlling the number of the controllable current sampling units in the working state.

[0093] In an optional implementation, the circuit schematic diagram of the current sampling circuit is as follows: Figure 10 As shown. It is understandable that Figure 10 The op2 and MP0 tubes in the OP2 and MP0 can also be omitted, but the sampling accuracy will be reduced. Figure 10The schematic diagram shown is understood as a limitation of the current sampling circuit. Each controllable current sampling unit includes two PMOS transistors connected in series (one is a switch transistor and the other is a sampling transistor).

[0094] The sampling ratio of each controllable current sampling unit can be the same, for example, 1:1 sampling, or can be different. For example, the sampling ratio of each controllable current sampling unit is different, and N sampling ratios form a geometric progression with a common ratio of 2 or 1 / 2. Figure 10 5 controllable current sampling units are shown in FIG. 1 . From the left to the right, the sampling ratio of the controllable current sampling unit in the last channel is twice the sampling ratio of the controllable current sampling unit in the last channel. Figure 10 The relationship between the multiples of 1, 2, 4, 8, and 16 in the figure can also be reversed. For example, when viewing the sequence from left to right, the sampling ratio of the controllable current sampling unit in the last channel is 1 / 2 times the sampling ratio of the controllable current sampling unit in the next channel, that is, Mm0:Mm1:Mm2:Mm3:Mm4=16:8:4:2:1. This can reduce the number of controllable current sampling units. For example, if 1:1 sampling is required, if triple sampling is required, it is necessary to control 3 controllable current sampling units to be in the working state. If the above example is used, it is only necessary to control 2 controllable current sampling units to be in the working state, that is, to control the controllable current sampling unit with a sampling ratio of 1 and the controllable current sampling unit with a sampling ratio of 2 to be in the working state.

[0095] In another optional embodiment, the current sampling circuit may further include: a first fixed current sampling unit, a first current mirror unit, and a second fixed current sampling unit based on the N-way controllable current sampling units connected in parallel. The second fixed current sampling unit and the first fixed current sampling unit are both connected to the first current mirror unit. In this case, the schematic diagram of the current sampling circuit is as follows: Figure 11 shown.

[0096] The first fixed current sampling unit is configured to sample the load current to obtain an initial sampled current. For example, the first fixed current sampling unit may sample the load current in an M:1 ratio to obtain the initial sampled current. The structure of the first fixed current sampling unit is consistent with that of the aforementioned fixed current sampling unit.

[0097] The first current mirror unit is used to mirror the initial sampling current to the second fixed current sampling unit. For example, the first current mirror unit mirrors the initial sampling current to the second fixed current sampling unit at a ratio of 1:1. It is understandable that the first current mirror unit can also be replaced by Figure 8 The first current mirror unit is shown.

[0098] The second fixed current sampling unit is used to perform a 1:1 mirroring of the initial sampled current to obtain the initial sampled current. Optionally, the second fixed current sampling unit includes three PMOS tubes connected in series (including an MP3 tube and two PMOS tubes located above and below the MP3 tube). It is understandable that since the gate terminal of the PMOS tube located above the MP3 tube is grounded, it is in a normally closed state, that is, a conductive state. In one embodiment, the PMOS tube located above the MP3 tube can be omitted. The reason for retaining this PMOS tube is to maintain consistency with the structure of the controllable current sampling unit on the right, so as to offset the sampling error caused by the switch tube in the controllable current sampling unit.

[0099] Correspondingly, when each controllable current sampling unit is in the working state, it is used to sample the initial sampling current output by the second fixed current sampling unit to obtain the sampling current.

[0100] It is understandable that Figure 11 The PMOS transistor located below MP3, as well as the PMOS transistors located below Mm0, Mm1, Mm2, Mm3, ..., MmN in each controllable current sampling unit, can be omitted. These PMOS transistors primarily serve as clamps and are added to improve sampling accuracy. These PMOS transistors are controlled by the Vpb1 signal and are in a normally closed state, or in the on state.

[0101] In order to better understand the principle of the above current detection device, the following Figure 12 The timing diagram shown is used for explanation. Figure 12 The Couting_Pulse in the code is the counting pulse.

[0102] At T0, the circuit starts and the current control circuit defaults to b <n:0>= 5’h2, converted to binary is 5’b00010. The actual current of Imonitor is small, and the operating frequency CLK_ICO of ICO is relatively low. At this time, VRO < VREF1, and the controller automatically completes the control of the current sampling circuit, b <n:0>It increases gradually and reaches stability before time T1. The Counter output by the current detection circuit (CurrentMonitor) also increases gradually until it stabilizes.

[0103] At T1, the load current suddenly increases, the actual Imonitor also increases suddenly, VRO and CLK_ICO both increase gradually until VRO>VREF2, the controller automatically completes the control of the current sampling circuit, b <n:0>Gradually decrease until stable. Counter also gradually decreases until stable.

[0104] At time T2, the load current suddenly becomes smaller, the actual Imonitor suddenly decreases, and VRO and CLK_ICO also gradually decrease. After VRO < VREF1, the controller automatically completes the control of the current sampling circuit, b <n:0>The value of Counter also increases gradually until it stabilizes.

[0105] Based on the same inventive concept, embodiments of the present application also provide a low-dropout linear regulator including the aforementioned current detection device. This improves an existing low-dropout linear regulator (LDO unit) by adding a current detection device for current detection. The improved low-dropout linear regulator includes an LDO unit and the aforementioned current detection device.

[0106] The current detection device provided in the low-voltage difference linear regulator embodiment has the same implementation principle and technical effects as those in the aforementioned current detection device embodiment. For the sake of brief description, any matters not mentioned in the low-voltage difference linear regulator embodiment can be referred to the corresponding content in the aforementioned current detection device embodiment.

[0107] Based on the same inventive concept, an embodiment of the present application further provides an electronic device, comprising a load and the aforementioned current detection device, wherein the current detection device is configured to detect the load current of the load. The electronic device can be any electronic device including the aforementioned current detection device, such as a mobile phone, tablet, computer, server, or the like.

[0108] Based on the same inventive concept, the present application also provides a current detection method applied to the above current detection device, such as Figure 13 As shown below. Figure 13 The steps included in this current detection method will be described.

[0109] S1: Sample the load current to obtain the target sampling current.

[0110] Optionally, the current sampling circuit in the above-mentioned battery detection device can be used to sample the load current to obtain a target sampling current.

[0111] S2: Generate an oscillation signal based on the target sampling current.

[0112] Optionally, the above-mentioned N-stage differential ring oscillator may be used to generate an oscillation signal based on the target sampling current.

[0113] S3: Detecting the number of oscillation cycles of the oscillation signal within a specified time; wherein the number of oscillation cycles is used to represent the magnitude of the target sampling current.

[0114] Optionally, the above-mentioned current detection circuit can be used to detect the number of oscillation cycles of the oscillation signal within a specified time.

[0115] The process of detecting the number of oscillation cycles of the oscillation signal within a specified time may be: counting the number of times a specified edge appears in any one of the N oscillation signals within the specified time to obtain an integer multiple of the oscillation cycles within the specified time; counting the phase states of the N oscillation signals detected within the specified time to obtain a fractional multiple of the oscillation cycles other than the integer multiple of the oscillation cycles; and obtaining all the oscillation cycles within the specified time based on the integer multiple of the oscillation cycles and the fractional multiple of the oscillation cycles.

[0116] Optionally, the first counter may be used to count the number of times a specified edge appears in any one of the N oscillation signals within a specified time, so as to obtain an integer multiple of the oscillation period within the specified time.

[0117] The second counter may be used to count the phase states of the N oscillation signals detected within a specified time, so as to obtain the fractional multiple oscillation period number in addition to the integer multiple oscillation period number counted by the first counter.

[0118] The decoder may be used to obtain the number of all oscillation cycles within a specified time based on the counting result of the first counter and the counting result of the second counter.

[0119] Optionally, the current detection method further includes adjusting a sampling ratio of the target sampling current based on a voltage corresponding to the target sampling current, so as to limit the voltage corresponding to the adjusted target sampling current to within a specified range. In other words, the sampling ratio of the current sampling circuit is adjusted so as to limit the voltage corresponding to the adjusted target sampling current to within the specified range.

[0120] The process of adjusting the sampling ratio of the target sampling current may be: comparing the voltage corresponding to the target sampling current with a first reference voltage to obtain a first comparison result, comparing the voltage corresponding to the target sampling current with a second reference voltage to obtain a second comparison result, the second reference voltage being greater than the first reference voltage, and adjusting the sampling ratio based on the first comparison result and the second comparison result to limit the voltage corresponding to the adjusted target sampling current to between the first reference voltage and the second reference voltage.

[0121] The first comparator can be used to compare the voltage corresponding to the target sampling current with the first reference voltage to obtain a first comparison result. The second comparator can be used to compare the voltage corresponding to the target sampling current with the second reference voltage to obtain a second comparison result. The controller can be used to adjust the sampling ratio of the current sampling circuit based on the first comparison result and the second comparison result.

[0122] The current detection principle and technical effects provided by the method embodiment are the same as those of the aforementioned current detection device embodiment. For the sake of brief description, for matters not mentioned in the method embodiment, reference can be made to the corresponding content in the aforementioned current detection device embodiment.

[0123] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0124] In addition, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0125] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A current detection device, characterized in that: include: A current sampling circuit is used to sample the load current to obtain a target sampling current; a current detection circuit connected to the current sampling circuit, the current detection circuit being configured to detect the number of oscillation cycles of an oscillation signal generated by the target sampling current within a specified time; wherein the number of oscillation cycles is used to characterize the magnitude of the target sampling current; Wherein, the current detection circuit includes: An N-stage differential ring oscillator, configured to generate N oscillation signals based on the target sampled current, where N is a positive integer greater than or equal to 2, and each of the oscillation signals includes two differential signals with a phase difference of 90 degrees; a first counter, configured to count the number of times a specified edge appears in any one of the N oscillation signals within the specified time, so as to obtain an integer multiple of the oscillation period within the specified time; a second counter, configured to count the phase states of the N oscillation signals detected within the specified time, so as to obtain a fractional multiple of the oscillation period number other than the integer multiple of the oscillation period number; A decoder is used to obtain the number of all oscillation cycles within the specified time according to the counting result of the first counter and the counting result of the second counter.

2. The current detection device according to claim 1, characterized in that: The current detection circuit further includes: The pulse width generator is used to generate a counting pulse, and the specified time is the time between two adjacent falling edges of the counting pulse.

3. The current detection device according to any one of claims 1 to 2, characterized in that: The current detection device further includes: A current control circuit is connected to the current sampling circuit and is used to control the magnitude of the target sampling current sampled by the current sampling circuit according to the voltage corresponding to the target sampling current, so as to limit the voltage corresponding to the adjusted target sampling current to a specified range to meet the range requirement of the current detection circuit.

4. The current detection device according to claim 3, characterized in that: The current control circuit comprises: a first comparator, configured to compare a voltage corresponding to the target sampling current with a first reference voltage to obtain a first comparison result; a second comparator, configured to compare a voltage corresponding to the target sampling current with a second reference voltage to obtain a second comparison result, wherein the second reference voltage is greater than the first reference voltage; A controller is configured to adjust a sampling ratio of the current sampling circuit according to the first comparison result and the second comparison result, so as to limit a voltage corresponding to the adjusted target sampling current to between the first reference voltage and the second reference voltage, so as to meet a range requirement of the current detection circuit.

5. The current detection device according to claim 3, characterized in that: The current sampling circuit includes: N controllable current sampling units connected in parallel, the first ends of each controllable current sampling unit are connected together for connecting to a power supply, and the second ends of each controllable current sampling unit are connected together and connected to the current detection circuit, where N is a positive integer greater than or equal to 2; Each controllable current sampling unit has two states: working and standby. When in the working state, it is used to sample the load current to obtain a sampling current. The target sampling current is the sum of the sampling currents of all controllable current sampling units in the working state. Accordingly, The current control circuit adjusts the magnitude of the target sampling current by controlling the number of controllable current sampling units in a working state.

6. The current detection device according to claim 5, characterized in that: The sampling ratio of each controllable current sampling unit is different, and the N sampling ratios form a geometric progression with a common ratio of 2 or 1 / 2.

7. The current detection device according to claim 5, characterized in that: The current sampling circuit further includes: a first fixed current sampling unit, a first current mirror unit, and a second fixed current sampling unit, wherein the second fixed current sampling unit and the first fixed current sampling unit are both connected to the first current mirror unit; The first fixed current sampling unit is used to sample the load current to obtain an initial sampling current; The first current mirror unit is configured to mirror the initial sampling current to the second fixed current sampling unit; The second fixed current sampling unit is configured to perform 1:1 sampling on the initial sampling current to obtain the initial sampling current; Correspondingly, when each controllable current sampling unit is in the working state, it is used to sample the initial sampling current output by the second fixed current sampling unit to obtain the sampling current.

8. A low-dropout linear regulator, characterized in that: include: The current detection device according to any one of claims 1 to 7.

9. An electronic device, characterized in that: include: A load and a current detection device according to any one of claims 1 to 7, wherein the current detection device is used to detect a load current of the load.

10. A current detection method, characterized in that: include: Sampling the load current to obtain a target sampling current; generating an oscillation signal based on the target sampling current; Detecting the number of oscillation cycles of the oscillation signal within a specified time; wherein the number of oscillation cycles is used to represent the magnitude of the target sampling current; Generating an oscillation signal based on the target sampling current includes: Based on the target sampling current, N oscillation signals are generated, where N is a positive integer greater than or equal to 2, and each oscillation signal includes two differential signals with a phase difference of 90 degrees; accordingly, Detecting the number of oscillation cycles of the oscillation signal within a specified time includes: Counting the number of times a specified edge appears in any one of the N oscillation signals within the specified time, so as to obtain an integer multiple of the oscillation period within the specified time; Counting the phase states of the N oscillation signals detected within the specified time to obtain a fractional multiple of the oscillation period number other than the integer multiple of the oscillation period number; According to the integer multiple oscillation period number and the fractional multiple oscillation period number, all oscillation period numbers within the specified time are obtained.

11. The method according to claim 10, characterized in that The specified time is the time between two adjacent falling edges of the counting pulse.

12. The method according to any one of claims 10-11, characterized in that The method further comprises: According to the voltage corresponding to the target sampling current, the sampling ratio of the target sampling current is adjusted to limit the adjusted voltage corresponding to the target sampling current to a specified range.

13. The method according to claim 12, characterized in that Adjusting the sampling ratio of the target sampling current includes: Comparing the voltage corresponding to the target sampling current with a first reference voltage to obtain a first comparison result; Comparing the voltage corresponding to the target sampling current with a second reference voltage to obtain a second comparison result, wherein the second reference voltage is greater than the first reference voltage; The sampling ratio is adjusted according to the first comparison result and the second comparison result, so as to limit the voltage corresponding to the adjusted target sampling current to between the first reference voltage and the second reference voltage.

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