Wafer acceptance test method and test structure
By constructing a four-terminal test structure on the wafer and using the difference to determine the relationship between resistance test abnormalities and contact abnormalities, the problem of difficulty in distinguishing between resistance module abnormalities and contact abnormalities in the prior art is solved, thereby improving the reliability and efficiency of wafer acceptance testing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUA HONG SEMICON WUXI LTD
- Filing Date
- 2023-01-05
- Publication Date
- 2026-05-29
AI Technical Summary
Existing wafer acceptance testing methods struggle to distinguish between abnormalities in the resistor module itself and abnormalities in the test data caused by abnormal contact between the resistor module and the testing equipment.
By selecting four specific PADs on the wafer to form a four-terminal test structure, the difference between the test data at both ends and the four ends is obtained. Based on the difference, the relationship between resistance test abnormalities and contact abnormalities is determined. Using the four-terminal test structure composed of the first target PAD, the second target PAD, the first re-inspection PAD, and the second re-inspection PAD, the potential and current are obtained to distinguish the cause of the abnormality.
Without adding extra equipment, it is easy and effective to determine the relationship between resistance test abnormalities and contact abnormalities, improving the reliability of the test and saving manpower and resources.
Smart Images
Figure CN116087618B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of parameter testing technology for semiconductor devices, specifically to a wafer acceptance testing method and test structure. Background Technology
[0002] In WAT (Wafer Acceptance Testing), resistance testing is a very common and crucial test item. Anomalies frequently occur in resistance test data. In actual WAT testing, the resistance module is easily affected by malfunctions in the testing equipment (testing machine), leading to abnormal test data. However, current testing methods struggle to determine whether the abnormal data is caused by a genuine malfunction in the resistance module itself or by a problem in the contact between the resistance module and the testing equipment. Summary of the Invention
[0003] This application provides a wafer acceptance test method and test structure, which can solve the problem that current test methods have difficulty in determining whether the abnormal test data is caused by an actual abnormality in the resistor module or by an abnormal contact between the resistor module and the test equipment.
[0004] On one hand, embodiments of this application provide a wafer acceptance testing method, which includes: resistance testing, wherein the wafer has a resistance module and a plurality of PADs electrically connected to the resistance module for the resistance testing, and the wafer acceptance testing method includes:
[0005] In the resistance test, multiple test data at both ends of the resistance module are acquired;
[0006] Confirm whether there are any abnormalities in the test data at both ends. If there are any abnormalities in the test data at both ends, obtain the first target PAD and the second target PAD corresponding to the abnormality in the test data at both ends.
[0007] Any two PADs outside the first target PAD and the second target PAD on the wafer are selected as the first re-inspection PAD and the second re-inspection PAD, wherein the first target PAD, the second target PAD, the first re-inspection PAD and the second re-inspection PAD constitute a four-terminal test structure.
[0008] The potential of the first target PAD, the potential of the second target PAD, and the current flowing through the resistor between the first retest PAD and the second retest PAD are obtained using testing equipment.
[0009] Based on the potential of the first target PAD, the potential of the second target PAD, and the current flowing through the resistance between the first retest PAD and the second retest PAD, four-terminal test data are obtained.
[0010] Obtain the difference between the test data at both ends and the test data at all four ends. If the difference is within a preset first threshold range, it is determined that the resistance test abnormality is unrelated to the contact abnormality; if the difference is outside the preset first threshold range, it is determined that the resistance test abnormality is related to the contact abnormality.
[0011] Optionally, in the wafer acceptance test method, the test data at both ends includes: the measured resistance value between any two PADs.
[0012] Optionally, in the wafer acceptance test method, the four-terminal test data includes: the measured resistance value between the first target PAD and the second target PAD.
[0013] Optionally, in the wafer acceptance test method, the resistor module includes at least three resistors connected in series, with the series connection node between the resistors led out to the wafer surface through the PAD.
[0014] Optionally, in the wafer acceptance test method, the step of obtaining multiple test data at both ends of the resistor module during the resistance test includes:
[0015] Place the pin card on the PAD;
[0016] The potential difference between any two PADs and the current flowing between the two PADs are obtained by using the pogo pin of the test device and the pin card, respectively.
[0017] Based on the potential difference between any two PADs and the current flowing between the two PADs, multiple test data points at both ends are obtained.
[0018] Optionally, in the wafer acceptance test method, the step of confirming whether there are any abnormalities in the test data at both ends, and if there are abnormalities in the test data at both ends, obtaining the first target PAD and the second target PAD corresponding to the abnormality in the test data at both ends includes:
[0019] Compare all the test data at both ends with the ideal resistance value between the corresponding two PADs, and obtain the difference between the test data at both ends and the ideal resistance value between the corresponding two PADs;
[0020] If the difference between the test data at both ends and the ideal resistance value between the corresponding two PADs exceeds the preset second threshold range, it is confirmed that the test data at both ends is abnormal.
[0021] If there are anomalies in the test data at both ends, then obtain the first target PAD and the second target PAD corresponding to the anomalies in the test data at both ends.
[0022] Optionally, in the wafer acceptance test method, the contact abnormality includes: contact abnormality between the pogo pin and the pin card, and contact abnormality between the pin card and the PAD.
[0023] Optionally, in the wafer acceptance test method, the preset first threshold range is [-0.5, +0.5].
[0024] Optionally, in the wafer acceptance test method, the preset second threshold range is [-0.2, +0.2].
[0025] On the other hand, embodiments of this application also provide a test structure for wafer acceptance testing. The wafer acceptance test includes a resistance test. The wafer has a resistance module and multiple PADs electrically connected to the resistance module for the resistance test. The test structure includes a first target PAD, a second target PAD, a first re-inspection PAD, and a second re-inspection PAD. The first target PAD, the second target PAD, the first re-inspection PAD, and the second re-inspection PAD are four PADs. The first re-inspection PAD and the second re-inspection PAD are disposed outside the first target PAD and the second target PAD. Test data at both ends are obtained through the first target PAD and the second target PAD, and test data at all four ends are obtained through the first target PAD, the second target PAD, the first re-inspection PAD, and the second re-inspection PAD.
[0026] The technical solution of this application has at least the following advantages:
[0027] After identifying the first target PAD and the second target PAD corresponding to the abnormal test data at both ends, this application introduces a first re-inspection PAD and a second re-inspection PAD, forming a four-terminal test structure. This four-terminal test structure is used to acquire the potential of the first target PAD, the potential of the second target PAD, and the current flowing through the resistance between the first and second re-inspection PADs. Based on the potentials of the first and second target PADs and the current flowing through the resistance between the first and second re-inspection PADs, four-terminal test data is acquired. The difference between the two-end test data and the four-terminal test data is obtained. If the difference is within a preset first threshold range, it is determined that the resistance test abnormality is unrelated to the contact abnormality; if the difference is outside the preset first threshold range, it is determined that the resistance test abnormality is related to the contact abnormality. The wafer acceptance test method provided in this application can easily and effectively determine whether abnormal resistance testing is related to contact abnormalities such as abnormal contact between the pogo pin and the pin card, or abnormal contact between the pin card and the PAD, without introducing additional test equipment. This saves manpower and resources and improves the reliability of wafer acceptance testing. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0029] Figure 1 This is a flowchart of the wafer acceptance test method according to an embodiment of the present invention;
[0030] Figure 2 This is a schematic diagram of the test principle for obtaining test data at both ends in the resistance test according to an embodiment of the present invention;
[0031] Figure 3 This is a schematic diagram of the test principle for obtaining four-terminal test data in the resistance test according to an embodiment of the present invention;
[0032] The reference numerals in the attached figures are explained as follows:
[0033] 10-PAD, 11-First target PAD, 12-Second target PAD, 13-First re-inspection PAD, 14-Second re-inspection PAD. Detailed Implementation
[0034] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0035] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0036] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0037] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0038] This application provides a wafer acceptance test method, wherein the wafer acceptance test includes: resistance testing, wherein the wafer has a resistance module and a plurality of PADs electrically connected to the resistance module for the resistance test.
[0039] In this embodiment, the resistor module on the wafer includes at least three resistors connected in series, with the series nodes between the resistors led out to the wafer surface through the PAD.
[0040] refer to Figure 1 , Figure 1 This is a flowchart of a wafer acceptance test method according to an embodiment of the present invention. The wafer acceptance test method includes:
[0041] Step S10: In the resistance test, acquire multiple test data at both ends of the resistance module.
[0042] For details, please refer to Figure 2 , Figure 2 This is a schematic diagram illustrating the test principle for obtaining test data at both ends during resistance testing according to an embodiment of the present invention. Figure 2 The diagram only illustrates the principle of the electrical connection between all PAD10s and the resistors; it does not specifically indicate whether the resistor module is located on or inside the wafer, nor does it specify the exact location of the PADs on the wafer surface. The step of obtaining multiple test data points from both ends of the resistor module during the resistance test may specifically include:
[0043] Step S10.1: Place the pin clip on the PAD10;
[0044] Step S10.2: Using the pogo pin of the test device and the pin card, obtain the potential difference between any two PAD10 and the current flowing between the two PADs respectively;
[0045] Step S10.3: Based on the potential difference between any two PAD10s and the current flowing between the two PAD10s, obtain multiple test data for both ends.
[0046] Preferably, the test data at both ends includes, but is not limited to, the actual measured resistance value between any two PAD10s.
[0047] Step S20: Confirm whether there is any abnormality in the test data at both ends. If there is any abnormality in the test data at both ends, obtain the first target PAD11 and the second target PAD12 corresponding to the abnormality in the test data at both ends.
[0048] Specifically, the step of confirming whether there are any anomalies in the test data at both ends, and if there are anomalies in the test data at both ends, obtaining the first target PAD and the second target PAD corresponding to the anomalies in the test data at both ends, may specifically include:
[0049] Compare the actual measured resistance value between any two PAD10s in all the test data at both ends with the ideal resistance value between the corresponding two PAD10s, and obtain the difference between the measured resistance value between any two PAD10s and the ideal resistance value between the corresponding two PAD10s.
[0050] If the difference between the actual measured resistance value between any two PAD10s and the ideal resistance value between the corresponding two PAD10s exceeds the preset second threshold range, then it is confirmed that there is an abnormality in the test data at both ends.
[0051] If there are abnormalities in the test data at both ends, then the first target PAD11 and the second target PAD12 corresponding to the abnormality in the test data at both ends are obtained.
[0052] In this embodiment, the preset second threshold range can be [-0.2, +0.2]. If the actual measured resistance value between any two PAD10s is too large or too small, it will exceed the preset second threshold range, which can preliminarily confirm that the resistance test is abnormal.
[0053] In this embodiment, the unit of the values in the second threshold interval is Ω.
[0054] Step S30: Reference Figure 3 , Figure 3 This is a schematic diagram of the test principle for obtaining four-terminal test data in the resistance test of an embodiment of the present invention. Any two PAD10s outside the first target PAD11 and the second target PAD12 on the wafer are selected as the first re-inspection PAD13 and the second re-inspection PAD14. The first target PAD11, the second target PAD12, the first re-inspection PAD13 and the second re-inspection PAD14 constitute a four-terminal test structure.
[0055] Step S40: Use testing equipment to obtain the potential of the first target PAD11, the potential of the second target PAD12, and the current flowing through the resistor between the first re-inspection PAD13 and the second re-inspection PAD14.
[0056] Step S50: Obtain four-terminal test data based on the potential of the first target PAD11, the potential of the second target PAD12, and the current flowing through the resistor between the first retest PAD13 and the second retest PAD14.
[0057] In this embodiment, the four-terminal test data includes, but is not limited to, the actual measured resistance value between the first target PAD and the second target PAD.
[0058] Step S60: Obtain the difference between the test data at both ends and the test data at all four ends. If the difference is within a preset first threshold range, it is determined that the resistance test abnormality is not related to the contact abnormality, thereby allowing the investigation of other causes of abnormal test data at both ends. If the difference is outside the preset first threshold range, it is determined that the resistance test abnormality is related to the contact abnormality.
[0059] Preferably, the preset first threshold range is [-0.5, +0.5].
[0060] In this embodiment, the unit of the values in the first threshold interval is Ω. That is, the difference between the test data at both ends and the test data at all four ends is obtained. If the difference is between -0.5Ω and +0.5Ω, it is determined that the resistance test abnormality is not related to the contact abnormality. If the difference is less than -0.5Ω or greater than +0.5Ω, it is determined that the resistance test abnormality is related to the contact abnormality.
[0061] Furthermore, after obtaining the difference between the test data at both ends and the test data at all four ends, the ideal resistance values between the test data at all four ends and the resistance between the first target PAD and the second target PAD can be compared to obtain the difference between the test data at all four ends and the ideal resistance values between the first target PAD and the second target PAD. If the difference between the test data at all four ends and the ideal resistance values between the first target PAD and the second target PAD does not exceed the preset second threshold range, it can be further determined that the abnormal test data at both ends (abnormal resistance test) is related to abnormal contact.
[0062] In other words, if the difference between the test data at both ends and the test data at all four ends is large, but the difference between the test data at all four ends and the ideal resistance value between the first target PAD and the second target PAD is small, then it can be completely confirmed that the abnormality of the test data at both ends (resistance test abnormality) is related to contact abnormality.
[0063] In this embodiment, the contact abnormality may include: contact abnormality between the pogo pin and the pin card, and contact abnormality between the pin card and the PAD.
[0064] In this application, after determining the first target PAD11 and the second target PAD12 corresponding to the abnormal test data at both ends, a first re-inspection PAD13 and a second re-inspection PAD14 are introduced, so that the first target PAD11, the second target PAD12, the first re-inspection PAD13 and the second re-inspection PAD14 constitute a four-terminal test structure. This four-terminal test structure is used to obtain the potential of the first target PAD11, the potential of the second target PAD12, and the current flowing through the resistance between the first re-inspection PAD13 and the second re-inspection PAD14. Based on the potential of the first target PAD11, the potential of the second target PAD12, and the current flowing through the resistance between the first re-inspection PAD13 and the second re-inspection PAD14, four-terminal test data is obtained. The difference between the two-end test data and the four-terminal test data is obtained. If the difference is within a preset first threshold range, it is determined that the resistance test abnormality is unrelated to the contact abnormality; if the difference is outside the preset first threshold range, it is determined that the resistance test abnormality is related to the contact abnormality. The wafer acceptance test method provided in this application can easily and effectively determine whether abnormal resistance testing is related to contact abnormalities such as abnormal contact between the pogo pin and the pin card, or abnormal contact between the pin card and the PAD, without introducing additional test equipment. This saves manpower and resources and improves the reliability of wafer acceptance testing.
[0065] Based on the same inventive concept, embodiments of this application also provide a test structure, such as... Figure 3 As shown, the test structure is used for wafer acceptance testing. The wafer acceptance test includes a resistance test. The wafer has a resistance module and multiple PADs 10 electrically connected to the resistance module for the resistance test. The test structure includes a first target PAD 11, a second target PAD 12, a first re-inspection PAD 13, and a second re-inspection PAD 14. The first target PAD 11, the second target PAD 12, the first re-inspection PAD 13, and the second re-inspection PAD 14 are four PADs among the PADs 10. The first re-inspection PAD 13 and the second re-inspection PAD 14 are located outside the first target PAD 11 and the second target PAD 12. Test data at both ends are obtained through the first target PAD 11 and the second target PAD 12, and test data at all four ends are obtained through the first target PAD 11, the second target PAD 12, the first re-inspection PAD 13, and the second re-inspection PAD 14.
[0066] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A wafer acceptance test method, characterized in that, Wafer acceptance testing includes: resistance testing, wherein the wafer has a resistor module and multiple PADs electrically connected to the resistor module for the resistance testing, and the wafer acceptance testing method includes: In the resistance test, multiple test data at both ends of the resistance module are acquired; Confirm whether there are any abnormalities in the test data at both ends. If there are any abnormalities in the test data at both ends, obtain the first target PAD and the second target PAD corresponding to the abnormality in the test data at both ends. Any two PADs outside the first target PAD and the second target PAD on the wafer are selected as the first re-inspection PAD and the second re-inspection PAD, wherein the first target PAD, the second target PAD, the first re-inspection PAD and the second re-inspection PAD constitute a four-terminal test structure. The potential of the first target PAD, the potential of the second target PAD, and the current flowing through the resistor between the first retest PAD and the second retest PAD are obtained using testing equipment. Based on the potential of the first target PAD, the potential of the second target PAD, and the current flowing through the resistance between the first retest PAD and the second retest PAD, four-terminal test data are obtained. Obtain the difference between the test data at both ends and the test data at all four ends. If the difference is within a preset first threshold range, it is determined that the resistance test abnormality is unrelated to the contact abnormality; if the difference is outside the preset first threshold range, it is determined that the resistance test abnormality is related to the contact abnormality.
2. The wafer acceptance test method according to claim 1, characterized in that, The test data at both ends includes the measured resistance value between any two PADs.
3. The wafer acceptance test method according to claim 1, characterized in that, The four-terminal test data includes: the measured resistance value between the first target PAD and the second target PAD.
4. The wafer acceptance test method according to claim 1, characterized in that, The resistor module includes at least three resistors connected in series, with the series connection node between the resistors led out to the wafer surface via the PAD.
5. The wafer acceptance test method according to claim 4, characterized in that, The step of obtaining multiple test data at both ends of the resistor module in the resistance test includes: Place a pin card on the PAD; The potential difference between any two PADs and the current flowing between the two PADs are obtained by using the pogo pin of the test device and the pin card, respectively. Based on the potential difference between any two PADs and the current flowing between the two PADs, multiple test data points at both ends are obtained.
6. The wafer acceptance test method according to claim 4 or 5, characterized in that, The step of confirming whether there are any anomalies in the test data at both ends, and if there are anomalies in the test data at both ends, obtaining the first target PAD and the second target PAD corresponding to the anomalies in the test data at both ends includes: Compare all the test data at both ends with the ideal resistance value between the corresponding two PADs, and obtain the difference between the test data at both ends and the ideal resistance value between the corresponding two PADs; If the difference between the test data at both ends and the ideal resistance value between the corresponding two PADs exceeds the preset second threshold range, it is confirmed that the test data at both ends is abnormal. If there are anomalies in the test data at both ends, then obtain the first target PAD and the second target PAD corresponding to the anomalies in the test data at both ends.
7. The wafer acceptance test method according to claim 5, characterized in that, The contact abnormalities include: abnormal contact between the pogo pin and the pin card, and abnormal contact between the pin card and the PAD.
8. The wafer acceptance test method according to claim 1, characterized in that, The preset first threshold range is [-0.5, +0.5].
9. The wafer acceptance test method according to claim 6, characterized in that, The preset second threshold range is [-0.2, +0.2].
10. A test structure, characterized in that, The test structure is used for wafer acceptance testing, which includes resistance testing. The wafer has a resistance module and multiple PADs electrically connected to the resistance module for the resistance testing. The test structure includes a first target PAD, a second target PAD, a first re-inspection PAD, and a second re-inspection PAD. The first target PAD, the second target PAD, the first re-inspection PAD, and the second re-inspection PAD are four PADs. The first re-inspection PAD and the second re-inspection PAD are located outside the first target PAD and the second target PAD. Test data at both ends are obtained through the first target PAD and the second target PAD, and test data at all four ends are obtained through the first target PAD, the second target PAD, the first re-inspection PAD, and the second re-inspection PAD.