NMOS low voltage drop linear regulator, chip and electronic device

Abstract

The embodiments of the present disclosure provide an NMOS low-dropout linear regulator, chip, and electronic device, belonging to the field of LDO technology. The NMOS LDO includes: a soft-start circuit, an error amplifier, and a buffer stage coupled in sequence; an output terminal of the buffer stage coupled to a first electrode of a first transistor and a first node; a control electrode of the first transistor coupled to a second electrode of the first transistor and a second node; a switch control circuit coupled between the first node and the second node; an output terminal of a charge pump circuit coupled to a control electrode and a second node of an NMOS power transistor; a second electrode of the NMOS power transistor coupled to a first voltage terminal, and a first electrode thereof coupled in sequence to an output terminal of the NMOS LDO, a first feedback resistor, a second feedback resistor, and a second voltage terminal. After power-on, the soft-start circuit controls a start signal to rise as the power supply voltage rises until it reaches a preset voltage value, and provides the start signal to the switch control circuit; the switch control circuit uses the start signal to control the on and off of the first transistor to control the on and off of the NMOS power transistor.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of low dropout regulators (LDOs), and in particular to an NMOS LDO, a chip, and an electronic device. Background Art

[0002] A low-dropout linear regulator (LDO) is a linear voltage regulator. LDOs can be categorized as PMOS LDOs or NMOS LDOs, depending on whether they use NMOS or PMOS power transistors. In traditional NMOS LDOs, after the power supply voltage is applied and before the soft-start circuit is activated, the NMOS power transistor is turned on due to the high gate voltage. This causes "step-like" fluctuations in the NMOS LDO's output voltage, affecting the normal operation of subsequent load circuits. Summary of the Invention

[0003] The purpose of the embodiments of the present disclosure is to provide an NMOS low-voltage dropout linear regulator, chip, and electronic device, which utilizes a start signal generated by a soft-start circuit after power-on to control the on and off of the NMOS power tube. When the soft-start circuit is not working, the NMOS power tube is controlled to be turned off, eliminating the "step"-shaped fluctuation in the output voltage of the NMOS low-voltage dropout linear regulator.

[0004] To achieve the above objectives, according to a first aspect of the present disclosure, an NMOS low-dropout linear regulator is provided, comprising: a soft-start circuit, a switch control circuit, a charge pump circuit, an NMOS power transistor, an error amplifier, a buffer stage, a first transistor, a first feedback resistor, and a second feedback resistor, wherein an output terminal of the soft-start circuit is coupled to a non-inverting input terminal of the error amplifier, an output terminal of the error amplifier is coupled to an input terminal of the buffer stage, an output terminal of the buffer stage is coupled to a first electrode of the first transistor and a first node, a control electrode of the first transistor is coupled to a second electrode of the first transistor and a second node, the switch control circuit is coupled between the first node and the second node, an output terminal of the charge pump circuit is coupled to a control electrode of the NMOS power transistor and the second node, a first electrode of the NMOS power transistor is coupled to an output terminal of the NMOS low-dropout linear regulator and a first terminal of the first feedback resistor, a second electrode of the NMOS power transistor is coupled to a first voltage terminal, a second terminal of the first feedback resistor is coupled to a first terminal of the second feedback resistor and an inverting input terminal of the error amplifier, and a second terminal of the second feedback resistor is coupled to a second voltage terminal. In which, the charge pump circuit is used to generate a bias voltage and provide the bias voltage to the control electrode of the NMOS power tube via the second node; the soft start circuit is used to control the start signal to rise as the power supply voltage rises until it reaches a preset voltage value after power-on, and provide the start signal to the switch control circuit; the switch control circuit is used to use the start signal to control the on and off of the first transistor to control the on and off of the NMOS power tube.

[0005] In some embodiments of the present disclosure, the soft start circuit includes: a first current source and a first capacitor, wherein the first end of the first current source is coupled to the first voltage end, the second end of the first current source is coupled to the first end of the first capacitor and the output end of the soft start circuit, and the second end of the first capacitor is coupled to the second voltage end.

[0006] In some embodiments of the present disclosure, the charge pump circuit includes: a charge pump and a charge pump internal resistor, the output end of the charge pump is coupled to the first end of the charge pump internal resistor, and the second end of the charge pump internal resistor is coupled to the output end of the charge pump circuit.

[0007] In some embodiments of the present disclosure, the switch control circuit includes: a second transistor, a third transistor, a fourth transistor, a third resistor, a fourth resistor, a second capacitor and a Schmitt trigger, wherein the control electrode of the second transistor is coupled to the first output terminal of the Schmitt trigger, the first electrode of the second transistor is coupled to the third voltage terminal, and the second electrode of the second transistor is coupled to the first end of the third resistor; the control electrode of the third transistor is coupled to the second output terminal of the Schmitt trigger, the first electrode of the third transistor is coupled to the first end of the third resistor, and the second electrode of the third transistor is coupled to the second voltage terminal; the second end of the third resistor is coupled to the first end of the second capacitor; the control electrode of the fourth transistor is coupled to the first end of the second capacitor, the first electrode of the fourth transistor is coupled to the first end of the fourth resistor, and the second electrode of the fourth transistor is coupled to the second node; the second end of the fourth resistor is coupled to the first node; the second end of the second capacitor is coupled to the second voltage terminal; and the input end of the Schmitt trigger is coupled to the output end of the soft start circuit.

[0008] In some embodiments of the present disclosure, the Schmitt trigger includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a fifth resistor and a sixth resistor, wherein the control electrode of the fifth transistor is coupled to the input terminal of the Schmitt trigger, the first electrode of the fifth transistor is coupled to the first voltage terminal, and the second electrode of the fifth transistor is coupled to the first electrode of the sixth transistor and the first electrode of the ninth transistor; the control electrode of the sixth transistor is coupled to the input terminal of the Schmitt trigger, the second electrode of the sixth transistor is coupled to the first electrode of the seventh transistor and the second output terminal of the Schmitt trigger; the control electrode of the seventh transistor is coupled to the input terminal of the Schmitt trigger, the second electrode of the seventh transistor is coupled to the first electrode of the eighth transistor and the first electrode of the tenth transistor; the control electrode of the eighth transistor is coupled to the input terminal of the Schmitt trigger, The second electrode of the eighth transistor is coupled to the second voltage terminal; the control electrode of the ninth transistor is coupled to the second output terminal of the Schmitt trigger, and the second electrode of the ninth transistor is coupled to the first terminal of the sixth resistor; the control electrode of the tenth transistor is coupled to the second output terminal of the Schmitt trigger, and the second electrode of the tenth transistor is coupled to the first terminal of the fifth resistor; the second terminal of the fifth resistor is coupled to the first voltage terminal; the second terminal of the sixth resistor is coupled to the second voltage terminal; the control electrode of the eleventh transistor is coupled to the second output terminal of the Schmitt trigger, the first electrode of the eleventh transistor is coupled to the first voltage terminal, and the second electrode of the eleventh transistor is coupled to the first output terminal of the Schmitt trigger; the control electrode of the twelfth transistor is coupled to the second output terminal of the Schmitt trigger, the first electrode of the twelfth transistor is coupled to the first output terminal of the Schmitt trigger, and the second electrode of the twelfth transistor is coupled to the second voltage terminal.

[0009] In some embodiments of the present disclosure, when the start signal output by the output end of the soft start circuit does not reach the preset voltage value, the first output end of the Schmitt trigger outputs a low level, and the second output end of the Schmitt trigger outputs a high level; when the start signal output by the output end of the soft start circuit reaches the preset voltage value, the first output end of the Schmitt trigger outputs a high level, and the second output end of the Schmitt trigger outputs a low level.

[0010] In some embodiments of the present disclosure, when the first output terminal of the Schmitt trigger outputs a low level and the second output terminal of the Schmitt trigger outputs a high level, the fourth transistor is turned on, the first transistor is short-circuited, and the NMOS power tube is turned off.

[0011] In some embodiments of the present disclosure, when the first output terminal of the Schmitt trigger outputs a high level and the second output terminal of the Schmitt trigger outputs a low level, the fourth transistor is turned off, the first transistor is connected to the circuit, and the NMOS power tube is turned on.

[0012] According to a second aspect of the present disclosure, a chip is provided, which includes the NMOS low-dropout linear regulator according to the first aspect of the present disclosure.

[0013] According to a third aspect of the present disclosure, an electronic device is provided, comprising the chip according to the second aspect of the present disclosure.

[0014] Other features and advantages of the embodiments of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the embodiments of the present disclosure, but do not constitute a limitation of the embodiments of the present disclosure. In the accompanying drawings:

[0016] Figure 1 is an exemplary circuit diagram of an NMOS LDO;

[0017] Figure 2 This is a simulation waveform diagram of an NMOS LDO;

[0018] Figure 3 is a schematic block diagram of an NMOS low-dropout linear regulator according to an embodiment of the present disclosure;

[0019] Figure 4 is another schematic block diagram of an NMOS low dropout linear regulator according to an embodiment of the present disclosure;

[0020] Figure 5 is a schematic block diagram of a switch control circuit in an NMOS low-dropout linear regulator according to an embodiment of the present disclosure;

[0021] Figure 6 is an exemplary circuit diagram of a Schmitt trigger according to an embodiment of the present disclosure;

[0022] Figure 7 4 is a schematic diagram of simulation waveforms of an NMOS low-dropout linear regulator according to an embodiment of the present disclosure.

[0023] Elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0026] In all embodiments of the present disclosure, since the source and drain of a metal oxide semiconductor (MOS) transistor are symmetrical, and the directions of the conduction current between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. In addition, terms such as "first" and "second" are only used to distinguish one component (or a portion of a component) from another component (or another portion of a component).

[0027] Figure 1 FIG. 1 shows an exemplary circuit diagram of an NMOS LDO 100. Figure 1 In the example, the soft-start circuit SoftStart consists of a capacitor and a current source that charges the capacitor, which enables the input signal SS to rise slowly, thereby causing the output voltage VOUT to rise slowly. Among them, the function of transistor M0 is to prevent the source voltage of the source follower transistor Follower from being too high under heavy load (large load current), thereby causing the output voltage of the error amplifier EA to be too high, resulting in malfunction of the error amplifier EA. Figure 1In the example, when the power supply voltage VDD is powered on and the soft start circuit Soft Start is not turned on, the output voltage of the error amplifier EA is 0. A gate-source voltage Vgs is generated through the source follower transistor Follower, and then another gate-source voltage Vgs is generated through the transistor diode. That is, the voltage at point Y is two gate-source voltages 2Vgs. The NMOS power tube is turned on, generating a certain output current flowing through the feedback resistors R1 and R2, causing a certain voltage to be generated at the output terminal VOUT, resulting in a "step"-shaped fluctuation in the output voltage, as shown in Figure 2. Figure 2 The marked portion of the output voltage VOUT waveform is shown in FIG.

[0028] The embodiment of the present disclosure proposes an NMOS low voltage drop linear regulator. Figure 1 The voltage drop of the gate-source voltage Vgs caused by the source follower transistor Follower and the voltage drop of the gate-source voltage Vgs caused by the transistor diode are shown, thereby eliminating the "step"-shaped fluctuation in the output voltage of the NMOS low-dropout linear regulator. Figure 3 FIG. 1 shows a schematic block diagram of an NMOS low voltage dropout linear regulator 300 according to an embodiment of the present disclosure. Figure 3 As shown, the NMOS low-dropout linear regulator 300 may include: a soft start circuit 310, a switch control circuit 320, a charge pump circuit 330, an NMOS power transistor Mn0, an error amplifier EA, a buffer stage BUFFER, a first transistor M1, a first feedback resistor R1 and a second feedback resistor R2. The output terminal of the soft start circuit 310 is coupled to the non-inverting input terminal of the error amplifier EA, the output terminal of the error amplifier EA is coupled to the input terminal of the buffer stage BUFFER, the output terminal of the buffer stage BUFFER is coupled to the first electrode of the first transistor M1 and the first node N1, the control electrode of the first transistor M1 is coupled to the second electrode of the first transistor M1 and the second node N2, the switch control circuit 320 is coupled between the first node N1 and the second node N2, the output terminal of the charge pump circuit 330 is coupled to the control electrode of the NMOS power transistor Mn0 and the second node N2, the first electrode of the NMOS power transistor Mn0 is coupled to the output terminal VOUT of the NMOS low-dropout linear regulator 300 and the first end of the first feedback resistor R1, the second electrode of the NMOS power transistor Mn0 is coupled to the first voltage terminal V1, the second end of the first feedback resistor R1 is coupled to the first end of the second feedback resistor R2 and the inverting input terminal of the error amplifier EA, and the second end of the second feedback resistor R2 is coupled to the second voltage terminal V2.

[0029] The charge pump circuit 330 is configured to generate a bias voltage and provide the bias voltage to the gate electrode of the NMOS power transistor via the second node N2. The soft-start circuit 310 is further coupled to the first voltage terminal V1 and the second voltage terminal V2. After power-on, the soft-start circuit 310 controls the start signal SS to slowly increase as the power supply voltage increases until it reaches a preset voltage value, and then provides the start signal SS to the switch control circuit 320. The switch control circuit is coupled to the soft-start circuit 310, the first voltage terminal V1, the second voltage terminal V2, and the third voltage terminal V3, and uses the start signal SS to control the on / off of the first transistor M1, thereby controlling the on / off of the NMOS power transistor Mn0.

[0030] According to the NMOS low-voltage dropout linear regulator of the embodiment of the present disclosure, the start signal generated after the soft-start circuit is powered on is used to control the on and off of the NMOS power tube. When the soft-start circuit is not working, the NMOS power tube is controlled to be turned off, thereby eliminating the "step"-shaped fluctuation in the output voltage of the NMOS low-voltage dropout linear regulator.

[0031] Figure 4 FIG. 2 shows another schematic block diagram of an NMOS low voltage dropout linear regulator 300 according to an embodiment of the present disclosure. Figure 4 As shown, the soft start circuit 310 may include: a first current source I A And the first capacitor C1. Wherein, the first current source I A The first end of the first current source I A The second end of the first capacitor C1 is coupled to the first end of the first capacitor C1 and the output end of the soft-start circuit 310. The second end of the first capacitor C1 is coupled to the second voltage end V2. The charge pump circuit 330 may include a charge pump and a charge pump internal resistor R0. The output end of the charge pump is coupled to the first end of the charge pump internal resistor R0, and the second end of the charge pump internal resistor R0 is coupled to the output end of the charge pump circuit 330.

[0032] Figure 5 FIG. 1 shows a schematic block diagram of a switch control circuit 320 in an NMOS low voltage drop linear regulator 300 according to an embodiment of the present disclosure. Figure 5As shown, the switch control circuit 320 may include: a second transistor M2, a third transistor M3, a fourth transistor M4, a third resistor R3, a fourth resistor R4, a second capacitor C2, and a Schmitt trigger 210. The control electrode of the second transistor M2 is coupled to the first output terminal of the Schmitt trigger 210, the first electrode of the second transistor M2 is coupled to the third voltage terminal V3, and the second electrode of the second transistor M2 is coupled to the first end of the third resistor R3. The control electrode of the third transistor M3 is coupled to the second output terminal of the Schmitt trigger 210, the first electrode of the third transistor M3 is coupled to the first end of the third resistor R3, and the second electrode of the third transistor M3 is coupled to the second voltage terminal V2. The second end of the third resistor R3 is coupled to the first end of the second capacitor C2. The control electrode of the fourth transistor M4 is coupled to the first end of the second capacitor C2, the first electrode of the fourth transistor M4 is coupled to the first end of the fourth resistor R4, and the second electrode of the fourth transistor M4 is coupled to the second node N2. The second end of the fourth resistor R4 is coupled to the first node N1. The second terminal of the second capacitor C2 is coupled to the second voltage terminal V2 . The input terminal of the Schmitt trigger 210 is coupled to the output terminal of the soft start circuit 310 .

[0033] in addition, Figure 6 FIG. 2 shows an exemplary circuit diagram of a Schmitt trigger 210 according to an embodiment of the present disclosure. Figure 6As shown, the Schmitt trigger 210 may include: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a fifth resistor R5, and a sixth resistor R6. The control electrode of the fifth transistor M5 is coupled to the input terminal of the Schmitt trigger 210, a first electrode of the fifth transistor M5 is coupled to the first voltage terminal V1, and a second electrode of the fifth transistor M5 is coupled to the first electrode of the sixth transistor M6 and the first electrode of the ninth transistor M9. The control electrode of the sixth transistor M6 is coupled to the input terminal of the Schmitt trigger 210, a second electrode of the sixth transistor M6 is coupled to the first electrode of the seventh transistor M7 and the second output terminal VOP of the Schmitt trigger 210. The control electrode of the seventh transistor M7 is coupled to the input terminal of the Schmitt trigger 210, and a second electrode of the seventh transistor M7 is coupled to the first electrode of the eighth transistor M8 and the first electrode of the tenth transistor M10. A control electrode of the eighth transistor M8 is coupled to the input terminal of the Schmitt trigger 210, and a second electrode of the eighth transistor M8 is coupled to the second voltage terminal V2. A control electrode of the ninth transistor M9 is coupled to the second output terminal VOP of the Schmitt trigger 210, and a second electrode of the ninth transistor M9 is coupled to the first end of the sixth resistor R6. A control electrode of the tenth transistor M10 is coupled to the second output terminal VOP of the Schmitt trigger 210, and a second electrode of the tenth transistor M10 is coupled to the first end of the fifth resistor R5. A second end of the fifth resistor R5 is coupled to the first voltage terminal V1. A second end of the sixth resistor R6 is coupled to the second voltage terminal V2. A control electrode of the eleventh transistor M11 is coupled to the second output terminal VOP of the Schmitt trigger 210, a first electrode of the eleventh transistor M11 is coupled to the first voltage terminal V1, and a second electrode of the eleventh transistor M11 is coupled to the first output terminal VON of the Schmitt trigger 210. A control terminal of the twelfth transistor M12 is coupled to the second output terminal VOP of the Schmitt trigger 210 , a first terminal of the twelfth transistor M12 is coupled to the first output terminal VON of the Schmitt trigger 210 , and a second terminal of the twelfth transistor M12 is coupled to the second voltage terminal V2 .

[0034] exist Figures 3 to 6In the example, the power supply voltage signal VDD is input from the first voltage terminal V1, the second voltage terminal V2 is grounded, and the bias voltage VBIAS is input from the third voltage terminal V3. The first transistor M1, the fourth transistor M4, the seventh transistor M7, the eighth transistor M8, the tenth transistor M10, and the twelfth transistor M12 are all NMOS transistors. The second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, the ninth transistor M9, and the eleventh transistor M11 are all PMOS transistors. It should be understood by those skilled in the art that based on the above inventive concept, Figures 3 to 6 The variation of the circuit shown should also fall within the scope of protection of the present disclosure. In this variation, the above-mentioned transistor and voltage terminal may also have the same Figures 3 to 6 Examples of different setups are shown.

[0035] The following combination Figures 3 to 6 The working process of the NMOS low-dropout linear regulator 300 according to the embodiment of the present disclosure is explained with an example.

[0036] Figure 7 The following is a schematic diagram of the simulation waveforms of the soft start simulation of the NMOS low voltage drop linear regulator 300 according to the embodiment of the present disclosure. At time t1, when the power supply voltage is powered on and the start signal SS outputted from the output terminal of the soft start circuit 310 does not reach the preset voltage value, the first output terminal VON of the Schmitt trigger 210 outputs a low level, the second output terminal VOP of the Schmitt trigger 210 outputs a high level, the second transistor M2 is turned on, the third transistor M3 is turned off, and the gate terminal voltage V G_M4 is high, the fourth transistor M4 is turned on, the first transistor M1 is short-circuited, the NMOS power tube is turned off, and the output voltage VOUT is close to 0. Figure 7 The dotted line portion of the waveform of the output voltage VOUT is shown, that is, the "step" waveform of the output voltage VOUT is eliminated. At time t2, the soft start circuit 310 starts working, and the start signal SS outputted by its output terminal reaches the preset voltage value shown. The first output terminal VON of the Schmitt trigger 210 outputs a high level, and the second output terminal VOP of the Schmitt trigger 210 outputs a low level. Due to the presence of the second capacitor C2 and the fourth resistor R4, the gate voltage V G_M4 and current I M4 The voltage of the fourth transistor M4 gradually decreases, the first transistor M1 is connected to the circuit and starts working, and the NMOS power tube is slowly turned on, so that the output voltage VOUT of the NMOS low voltage difference linear regulator slowly increases to realize the soft start function.

[0037] In summary, according to the NMOS low-voltage difference linear regulator of the embodiment of the present disclosure, the start signal output by the soft-start circuit is used to control the on-off of the first transistor, thereby controlling the on-off of the NMOS power tube, eliminating the "step"-shaped fluctuation of the output voltage of the NMOS low-voltage difference linear regulator before the soft-start circuit is turned on, thereby avoiding affecting the normal operation of subsequent circuits.

[0038] An embodiment of the present disclosure further provides a chip. The chip includes an NMOS low-dropout linear regulator according to an embodiment of the present disclosure. The chip is used, for example, in a power management chip.

[0039] An embodiment of the present disclosure further provides an electronic device. The electronic device includes a chip according to an embodiment of the present disclosure. The electronic device is, for example, a smart watch, experimental equipment, a smart screen, etc.

[0040] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the apparatus and method according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0041] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0042] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present disclosure can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present disclosure.

[0043] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. An NMOS low-dropout linear regulator, characterized in that: include: A soft start circuit, a switch control circuit, a charge pump circuit, an NMOS power transistor, an error amplifier, a buffer stage, a first transistor, a first feedback resistor, and a second feedback resistor, wherein the output of the soft start circuit is coupled to the non-inverting input of the error amplifier, the output of the error amplifier is coupled to the input of the buffer stage, the output of the buffer stage is coupled to the first electrode of the first transistor and a first node, the control electrode of the first transistor is coupled to the second electrode of the first transistor and a second node, the switch control circuit is coupled between the first node and the second node, the output of the charge pump circuit is coupled to the control electrode of the NMOS power transistor and the second node, the first electrode of the NMOS power transistor is coupled to the output of the NMOS low-dropout linear regulator and the first end of the first feedback resistor, the second electrode of the NMOS power transistor is coupled to a first voltage terminal, the second end of the first feedback resistor is coupled to the first end of the second feedback resistor and the inverting input of the error amplifier, and the second end of the second feedback resistor is coupled to a second voltage terminal. The charge pump circuit is used to generate a bias voltage and provide the bias voltage to the control electrode of the NMOS power tube via the second node; The soft start circuit is used to control the start signal to rise as the power supply voltage rises until it reaches a preset voltage value after power is turned on, and provide the start signal to the switch control circuit; The switch control circuit is used to control the on / off of the first transistor using the start signal to control the on / off of the NMOS power tube. The switch control circuit includes: a second transistor, a third transistor, a fourth transistor, a third resistor, a fourth resistor, a second capacitor and a Schmitt trigger. wherein the control electrode of the second transistor is coupled to the first output terminal of the Schmitt trigger, the first electrode of the second transistor is coupled to the third voltage terminal, and the second electrode of the second transistor is coupled to the first terminal of the third resistor; A control electrode of the third transistor is coupled to the second output terminal of the Schmitt trigger, a first electrode of the third transistor is coupled to the first terminal of the third resistor, and a second electrode of the third transistor is coupled to the second voltage terminal; The second end of the third resistor is coupled to the first end of the second capacitor; A control electrode of the fourth transistor is coupled to the first end of the second capacitor, a first electrode of the fourth transistor is coupled to the first end of the fourth resistor, and a second electrode of the fourth transistor is coupled to the second node; The second end of the fourth resistor is coupled to the first node; The second terminal of the second capacitor is coupled to the second voltage terminal; The input terminal of the Schmitt trigger is coupled to the output terminal of the soft start circuit.

2. The NMOS low-dropout linear regulator according to claim 1, wherein: The soft start circuit includes: a first current source and a first capacitor, The first end of the first current source is coupled to the first voltage end, the second end of the first current source is coupled to the first end of the first capacitor and the output end of the soft start circuit, and the second end of the first capacitor is coupled to the second voltage end.

3. The NMOS low-dropout linear regulator according to claim 1, wherein: The charge pump circuit includes: a charge pump and a charge pump internal resistor, The output end of the charge pump is coupled to the first end of the charge pump internal resistor, and the second end of the charge pump internal resistor is coupled to the output end of the charge pump circuit.

4. The NMOS low-dropout linear regulator according to claim 1, wherein: The Schmitt trigger includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a fifth resistor and a sixth resistor, wherein a control electrode of the fifth transistor is coupled to the input terminal of the Schmitt trigger, a first electrode of the fifth transistor is coupled to the first voltage terminal, and a second electrode of the fifth transistor is coupled to the first electrode of the sixth transistor and the first electrode of the ninth transistor; A control electrode of the sixth transistor is coupled to the input terminal of the Schmitt trigger, and a second electrode of the sixth transistor is coupled to the first electrode of the seventh transistor and the second output terminal of the Schmitt trigger; A control electrode of the seventh transistor is coupled to the input terminal of the Schmitt trigger, and a second electrode of the seventh transistor is coupled to the first electrode of the eighth transistor and the first electrode of the tenth transistor; A control electrode of the eighth transistor is coupled to the input terminal of the Schmitt trigger, and a second electrode of the eighth transistor is coupled to the second voltage terminal; A control electrode of the ninth transistor is coupled to the second output terminal of the Schmitt trigger, and a second electrode of the ninth transistor is coupled to the first terminal of the sixth resistor; A control electrode of the tenth transistor is coupled to the second output terminal of the Schmitt trigger, and a second electrode of the tenth transistor is coupled to the first terminal of the fifth resistor; The second end of the fifth resistor is coupled to the first voltage end; The second end of the sixth resistor is coupled to the second voltage end; The control electrode of the eleventh transistor is coupled to the second output terminal of the Schmitt trigger, the first electrode of the eleventh transistor is coupled to the first voltage terminal, and the second electrode of the eleventh transistor is coupled to the first output terminal of the Schmitt trigger; A control electrode of the twelfth transistor is coupled to the second output terminal of the Schmitt trigger, a first electrode of the twelfth transistor is coupled to the first output terminal of the Schmitt trigger, and a second electrode of the twelfth transistor is coupled to the second voltage terminal.

5. The NMOS low-dropout linear regulator according to claim 4, wherein: When the start signal output by the output end of the soft start circuit does not reach the preset voltage value, the first output end of the Schmitt trigger outputs a low level and the second output end of the Schmitt trigger outputs a high level; when the start signal output by the output end of the soft start circuit reaches the preset voltage value, the first output end of the Schmitt trigger outputs a high level and the second output end of the Schmitt trigger outputs a low level.

6. The NMOS low-dropout linear regulator according to claim 5, characterized in that: When the first output terminal of the Schmitt trigger outputs a low level and the second output terminal of the Schmitt trigger outputs a high level, the fourth transistor is turned on, the first transistor is short-circuited, and the NMOS power tube is turned off.

7. The NMOS low-dropout linear regulator according to claim 5, wherein: When the first output terminal of the Schmitt trigger outputs a high level and the second output terminal of the Schmitt trigger outputs a low level, the fourth transistor is turned off, the first transistor is connected to the circuit, and the NMOS power tube is turned on.

8. A chip, characterized in that: The device comprises an NMOS low voltage dropout linear regulator according to any one of claims 1 to 7.

9. An electronic device, characterized in that: Comprising the chip according to claim 8.

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