A communication method of single-wire SPI

Abstract

The present invention belongs to the field of computer communication technology and discloses a communication method for single-wire SPI. This communication method includes a sending end and a receiving end. Since only a single wire is used for transmission, data and clock signals can be transmitted simultaneously. The receiving end can restore the clock and data signals through demodulation. The present invention uses only a single wire for transmission, but is compatible with typical SPI interfaces. There is no obvious limitation on the communication rate, and it can be used for high-speed SPI communication (50 MHz or higher). When transmitting signals in some isolated or long-distance scenarios, it can greatly reduce the transmission cost and the number of cables, and greatly improve the economic practicality.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer communication, and particularly relates to a communication method of single - wire SPI. Background Art

[0002] For basic SPI communication, at least two signals are required, one for the clock and one for the data. However, when used for isolation or long - line communication, it is very inconvenient to transmit two signals. The traditional single - wire SPI communication method only has a data signal and no clock signal, and can only be used for data transmission of specific protocols, and cannot use the standard SPI protocol, so its application scope is greatly limited.

[0003] The present invention provides a communication method of single - wire SPI, which can mix - modulate and demodulate SPI data and clock. That is, when using single - wire transmission, data and clock signals can be transmitted simultaneously, and the receiving end can restore the clock and data signals through demodulation.

[0004] Through the above analysis, the problems and defects existing in the prior art are as follows:

[0005] The traditional single - wire SPI communication method only has a data signal and no clock signal, and can only be used for data transmission of specific protocols, and cannot use the standard SPI protocol, so its application scope is greatly limited. Summary of the Invention

[0006] In view of the problems existing in the prior art, the present invention provides a communication method of single - wire SPI.

[0007] The present invention is implemented as follows. A communication method of single - wire SPI includes a sending end and a receiving end. The clock signal and data signal of the sending end are carrier - processed through an external circuit, and the clock signal and data signal are synthesized into a mixed signal, which is then transmitted to the receiving end through a data line or optical fiber, etc. The receiving end demodulates the synthesized carrier signal to restore the clock signal and data signal, changing from 2 data transmission lines to 1 transmission line without changing the user's transmission and reception protocols.

[0008] The specific principle of the sending end is as follows:

[0009] (1) The clock signal CLK will be differentiated by a resistor - capacitor, and the data signal d a t a The level offset of the differentiated clock signal is controlled by a resistor.

[0010] (2) The diode clamps the signal to reset the differentiating capacitor. The differentiated signal is finally sent to a comparator comp for signal shaping. The reference level ref of comp should be selected to match the value of the differentiated clock signal, and finally the combined signal mSPI is obtained.

[0011] (3) For high-level data, the pulse width will be equal to the clock pulse width. For low-level data, a narrow pulse will be obtained, and the pulse width depends on the differential component. In this way, the high and low levels of the data will be converted into changes in pulse width, and the pulse itself will be a clock signal.

[0012] The specific principle of the receiving end is as follows:

[0013] (1) Similar to the transmission, the synthetic signal MSPI will be differentiated by the resistor and capacitor, the diode clamps the signal, the differential capacitor is reset, and the comparator performs signal shaping;

[0014] (2) The pulse width of the comparator output will be controlled by the differential value of the resistor and capacitor. The reference level ref of COMP should be selected to match the amplitude of the differential signal. Finally, the output of COMP is a fixed pulse width, which will serve as the initial SPI clock CLK of the receiving end.

[0015] (3) When the clock jumps to a low level, the data signal level is obtained, and the CLK signal after COMP shaping is delayed. The CLK clock enters the delay circuit, which can be an RC delay gate or a logic delay IC, and finally obtains the clock signal CLK2 for transmission to the SPI chip.

[0016] Furthermore, the MSPI signal is used as a data signal. When the data is low, the MSPI signal duty cycle is small, and the falling edge of the signal is before the CLK2 signal falls. The SPI chip recognizes that the data signal is at a low level. When the data is high, the MSPI signal duty cycle reaches , and the falling edge of the signal is after the CLK2 signal falls. The SPI chip recognizes that the data signal is at a high level, and the synthesized signal MSPI is restored to a data signal and a clock signal.

[0017] Another object of the present invention is to provide a transmitting end based on the single-wire SPI communication method, wherein the transmitting end is composed of R3, R2, C1, D1 and a comparator COMP.

[0018] Furthermore, the resistance values of R2 and R3 have a relatively wide range, R2=R3, and C1 is selected according to the resistance values of R2 and R3 and the frequency, so that when there is no data input, the waveform at the R2 resistor end has an obvious ramp on the falling edge, and when there is data, the voltage at the R2 end is obviously high. The voltage is optimal when there is no data.

[0019] Furthermore, D1 needs to be a fast diode with low junction capacitance, such as IN4148.

[0020] Further, the REF reference voltage of the comparator is optimally the general value of the ramp voltage when there is no data. The comparator should be a high-speed comparator, and the rise and fall times are much smaller than the cycle times of the data and clock signals, finally obtaining the mixed signal MSPI of the data and the clock.

[0021] Another object of the present invention is to provide a receiving end based on the communication method of the single-line SPI. The receiving end is composed of C2, D2, R1 and COMP.

[0022] Further, the value range of R1 is wide. The value of C2 is optimally such that obvious harmonics are generated at the voltage at the R1 end. D2 needs to be a fast diode with a low junction capacitance, such as IN4148, etc.

[0023] Further, the REF reference voltage of the comparator is optimally half of the voltage of the ramp at the maximum duty cycle of the R1 resistor. The comparator should be a high-speed comparator, and the rise and fall times are much smaller than the cycle times of the data and clock signals.

[0024] Further, for the CLK delay part in the receiving end, it is composed of an RC and a gate circuit, and the value range is wide. It only needs to make the CLK signal have a low level corresponding to the falling edge of the CLK at the minimum duty cycle of the R1 resistor.

[0025] Combined with the above technical solutions and the solved technical problems, please analyze the advantages and positive effects of the technical solution to be protected by the present invention from the following aspects:

[0026] First, aiming at the technical problems existing in the above prior art and the difficulty of solving this problem, closely combining the technical solution to be protected by the present invention and the results and data in the R & D process, etc., analyze in detail and deeply how the technical solution of the present invention solves the technical problems and the creative technical effects brought after solving the problems. The specific description is as follows:

[0027] The present invention only uses single-line transmission, but is compatible with the typical SPI interface, does not change the communication protocol structure of the user, and there is no obvious limitation on the communication rate, and can be used for high-speed SPI communication (50 mhz or higher).

[0028] Second, regarding the technical solution as a whole or from the perspective of the product, the technical effects and advantages of the technical solution to be protected by the present invention are as follows. The specific description is as follows:

[0029] When using SPI for data transmission in some environments with limited volume, strong isolation or interference, or when transmitting signals over a long distance, using the single-line transmission of the present invention can greatly reduce the transmission cost and reduce the number of cables, improving the economic practicality.

[0030] Thirdly, as the creative supplementary evidence of the claims of the present invention, it is also reflected in the following important aspects:

[0031] The expected benefits and commercial value after the transformation of the technical solution of the present invention are as follows:

[0032] The present invention can be applied to the output of certain high-speed sensors on automobiles, which can reduce the number of data transmission lines by half, reduce the difficulty of wiring technology, save the wire cost, and its value is inestimable after mass production. Description of the Drawings

[0033] Figure 1 is the schematic diagram of the transmitter provided by the embodiment of the present invention;

[0034] Figure 2 is the schematic diagram of the receiver provided by the embodiment of the present invention;

[0035] Figure 3 is the signal schematic diagram of the transmitter provided by the embodiment of the present invention;

[0036] Figure 4 is the signal schematic diagram of the receiver provided by the embodiment of the present invention;

[0037] Figure 5 is the schematic diagram of the RC delay gate provided by the embodiment of the present invention. Detailed Description of the Invention

[0038] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0039] 1. Explanation of the embodiments. In order to enable those skilled in the art to fully understand how the present invention is specifically implemented, this part is an explanatory embodiment that expands and explains the technical solution of the claims.

[0040] As Figures 1-5 shown, the embodiment of the present invention provides a communication method of single-wire SPI, and the communication method includes: a transmitter and a receiver;

[0041] The specific principle of the transmitter is as follows:

[0042] (1) The clock signal CLK will be differentiated by a resistor-capacitor, and the data signal data controls the level offset of the differentiated clock signal through a resistor;

[0043] (2) Diode-clamped signal, reset differentiating capacitor. The differentiated signal is finally sent to comparator comp for signal shaping. The reference level ref of comp should be selected to match the value of the differentiated clock signal, and finally the combined signal mSPI is obtained;

[0044] (3) For the data high level, the pulse width will be equal to the pulse width of the clock itself. For the data low level, narrow pulses will be obtained, and the pulse width depends on the differential component. In this way, the high and low levels of the data will be converted into changes in pulse width, and the pulse itself will be the clock signal;

[0045] As Figure 2 、 Figure 5 shown, the specific principle of the receiving end is as follows:

[0046] (1) Similar to the transmitter, the combined signal MSPI will be differentiated by a resistor-capacitor, diode-clamped signal, reset differentiating capacitor, and the comparator will perform signal shaping;

[0047] (2) The pulse width output by the comparator will be controlled by the differential component of the resistor-capacitor. The reference level ref of COMP should be selected to match the amplitude value of the differentiated signal. Finally, the output of COMP is a fixed pulse width, which will be used as the preliminary clock CLK of the SPI at the receiving end;

[0048] (3) When the clock jumps to the low level, the data signal level is obtained, and the signal of CLK after being shaped by COMP is delayed. This CLK clock enters the delay circuit, which can be an RC delay gate or a logic delay IC, and finally the clock signal CLK2 for feeding to the SPI chip is obtained.

[0049] The MSPI signal is used as the data data signal. When the data is low, the duty cycle of the MSPI signal is small, and the falling edge of the signal is before the falling edge of the CLK2 signal. The SPI chip recognizes that the data signal is at the low level. When the data is high, the duty cycle of the MSPI signal is large, and the falling edge of the signal is after the falling edge of the CLK2 signal. The SPI chip recognizes that the data signal is at the high level, and a combined signal MSPI is restored to a data signal and a clock signal.

[0050] II. Application embodiments. To prove the creativity and technical value of the technical solution of the present invention, this part is an application embodiment of the technical solution of the claims on specific products or related technologies.

[0051] The present invention applies the communication method of the single-wire SPI to a transmitter, and the transmitter is composed of R3, R2, C1, D1 and comparator COMP.

[0052] The resistance values of R2 and R3 have a wide range, R2=R3, C1 is selected according to the resistance values of R2 and R3 and the frequency, so that when there is no data input, the waveform at the R2 resistance end has an obvious ramp on the falling edge, and when there is data, the voltage at the R2 end is obviously high, and the voltage is optimal when there is no data.

[0053] The D1 needs to be a fast diode with low junction capacitance, such as IN4148.

[0054] The REF reference voltage of the comparator is optimally the general value of the ramp voltage when there is no data. The comparator should be a high-speed comparator with a rise and fall time much shorter than the data and clock signal cycle time, and finally a mixed signal MSPI of data and clock is obtained.

[0055] The present invention applies the single-line SPI communication mode to a receiving end, and the receiving end is composed of C2, D2, R1 and COMP.

[0056] The value range of R1 is wide, the value of C2 is optimal when the voltage at the R1 terminal produces obvious harmonics, and D2 needs to be a fast diode with low junction capacitance, such as IN4148.

[0057] The REF reference voltage of the comparator is optimal when the duty cycle of the resistor R1 is the maximum and the voltage of the ramp is half. The comparator should be a high-speed comparator, and the rise and fall time is much shorter than the cycle time of the data and clock signals.

[0058] The CLK delay part in the receiving end is composed of RC and gate circuits, and has a wide range of values. It only needs to make the CLK signal smaller than the R1 resistor when the CLK falling edge corresponds to a low level.

[0059] It should be noted that the embodiments of the present invention can be implemented by hardware, software, or a combination of software and hardware. The hardware part can be implemented using dedicated logic; the software part can be stored in a memory and executed by an appropriate instruction execution system, such as a microprocessor or dedicated design hardware. It can be understood by a person of ordinary skill in the art that the above-mentioned devices and methods can be implemented using computer executable instructions and / or contained in a processor control code, such as a carrier medium such as a disk, CD or DVD-ROM, a programmable memory such as a read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. Such code is provided on the carrier medium. The device and its modules of the present invention can be implemented by hardware circuits such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, etc., or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., can also be implemented by software executed by various types of processors, and can also be implemented by a combination of the above-mentioned hardware circuits and software, such as firmware.

[0060] III. Evidence of the effects related to the embodiments. Some positive effects have been achieved during the research and development or use of the embodiments of the present invention, and there are indeed great advantages compared with the prior art. The following content will be described in combination with the data, charts, etc. in the test process.

[0061] Embodiment 1: In a high-power multi-channel interleaved power supply being developed, the host needs to use SPI to perform closed-loop digital information transmission to the slave, and at the same time, the SPI clock signal is used as the phase control clock signal of the slave. Therefore, other communication methods cannot be used. In order to improve the anti-interference performance of the system, optical fiber transmission is used. However, the traditional solution requires 2 optical fibers, one for data signal and one for clock signal. When the number of slaves is relatively large, such as 20 slaves, 40 optical fiber lines are needed, which poses challenges to wiring and cost. After adopting the single-line SPI solution of the present invention, only 20 optical fiber lines are needed, greatly reducing the production cost.

[0062] Embodiment 2: When developing a high-frequency power probe, SPI is needed for fast information transmission. Since the probe is in a floating ground condition of high voltage and high frequency, only the optical fiber isolation transmission solution can be used. However, the volume of the probe is very small. If the traditional SPI solution is adopted, at least 2 optical fibers are required. After adopting the single-line SPI of the present invention, only one optical fiber is needed, greatly reducing the volume of the probe.

[0063] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention shall be covered by the protection scope of the present invention.

Claims

1. A communication method for single - wire SPI, characterized in that, This communication method includes: a transmitting end and a receiving end; the clock signal and data signal of the transmitting end are carrier-processed through an external circuit, the clock signal and data signal are synthesized into a mixed signal, and then transmitted to the receiving end through a data line or optical fiber, etc. The receiving end demodulates the synthesized carrier signal to restore the clock signal and data signal, changing from 2 data transmission lines to 1 transmission line without changing the user's transmission and receiving protocols; The specific principle of the transmitting end is as follows: (1) The clock signal CLK will be differentiated by a resistor-capacitor. The data signal data controls the level offset of the differentiated clock signal through a resistor; (2) The diode clamps the signal, resets the differentiating capacitor, and the differentiated signal is finally sent to the comparator comp for signal shaping. The reference level ref of comp should be selected to match the value of the differentiated clock signal, and finally the combined signal MSPI is obtained; (3) For the data high level, the pulse width will be equal to the pulse width of the clock itself. For the data low level, a narrow pulse will be obtained, and the pulse width depends on the differential amount. In this way, the high and low levels of the data will be converted into changes in pulse width, and the pulse itself will be the clock signal; The specific principle of the receiving end is as follows: (1) Similar to the transmitting end, the synthesized signal MSPI will be differentiated by a resistor-capacitor, the diode clamps the signal, resets the differentiating capacitor, and the comparator performs signal shaping; (2) The pulse width output by the comparator will be controlled by the differential amount of the resistor-capacitor. The reference level ref of COMP should be selected to match the value of the amplitude of the differentiated signal. Finally, the output of COMP is a fixed pulse width, which will be used as the preliminary clock CLK of the receiving end's SPI; (3) When the clock jumps to the low level, the data signal level will be obtained, and the signal of CLK after being shaped by COMP will be delayed. This CLK clock enters the delay circuit, which can be an RC delay gate or a logic delay IC, and finally the clock signal CLK2 for delivering to the SPI chip is obtained.

2. The communication method of the single-wire SPI according to claim 1, wherein The MSPI signal is used as the data data signal. When the data is low, the duty cycle of the MSPI signal is small, and the falling edge of the signal is before the falling edge of the CLK2 signal. The SPI chip recognizes that the data signal is low level. When the data is high, the duty cycle of the MSPI signal is large, and the falling edge of the signal is after the falling edge of the CLK2 signal. The SPI chip recognizes that the data signal is high level, restoring a synthesized signal MSPI to a data signal and a clock signal.

3. A transmitting end based on the communication method of the single-wire SPI described in any one of claims 1-2, characterized in that, The transmitting end is composed of R3, R2, C1, D1 and the comparator COMP.

4. The communication method of the single-wire SPI according to claim 3, characterized in that The resistance values of R2 and R3 have a relatively wide range of values. R2 = R3. C1 is selected according to the resistance values of R2 and R3 and the frequency. It is best that there is an obvious ramp at the falling edge of the waveform at the R2 resistor terminal when there is no data input, and the voltage at the R2 terminal is significantly higher when there is data than when there is no data.

5. The communication method of the single-line SPI according to claim 3, wherein, D1 needs to be a fast diode with a low junction capacitance, such as IN4148, etc.

6. The communication method of the single-wire SPI according to claim 3, characterized in that, The REF reference voltage of the comparator COMP is optimally the general value of the ramp voltage when there is no data. The comparator COMP should be a high-speed comparator with rise and fall times much smaller than the data and clock signal cycle times, and finally a mixed signal MSPI of data and clock is obtained.

7. A receiving end based on the communication method of the single-wire SPI described in any one of claims 1-2, characterized in that, The receiving end consists of C2, D2, R1 and the comparator COMP.

8. The communication method of the single-wire SPI according to claim 7, characterized in that The D2 is a fast diode with low junction capacitance.

9. The communication method of the single-wire SPI according to claim 7, characterized in that, The REF reference voltage of the comparator COMP is optimally the maximum duty cycle of the R1 resistor and half of the ramp voltage. The comparator COMP should be a high-speed comparator with rise and fall times much smaller than the data and clock signal cycle times.

10. The communication method of the single-wire SPI according to claim 7, characterized in that, For the CLK delay part in the receiving end, it is composed of an RC and a gate circuit, with a wide range of values. It only needs to ensure that the CLK signal corresponds to a low level at the falling edge of CLK when the duty cycle of the R1 resistor is the smallest.

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