Delay measurement device, delay measurement system and delay measurement method

Abstract

The present application relates to a delay measurement device, a delay measurement system and a delay measurement method, and belongs to the field of integrated circuit technology. The delay measurement device includes: an adjustable delay circuit and a counter; the adjustable delay circuit includes an odd number of delay devices with adjustable delay values. When the delay time of the adjustable delay circuit is consistent with the target delay amount, and the adjustable delay circuit is connected end to end, the adjustable delay circuit is used to generate an oscillation signal related to the target delay amount; the counter is used to count the number of oscillation cycles of the oscillation signal within a period of time, wherein the counting result is used to determine the target delay amount. When the delay time of the adjustable delay circuit is consistent with the target delay amount, the oscillation signal related to the target delay amount can be generated by connecting the adjustable delay circuit end to end. After that, the counter is used to count the number of oscillation cycles of the oscillation signal within a period of time, and the target delay amount can be obtained according to the counting result, thereby quickly realizing the measurement of the target delay amount.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuit technology, and specifically relates to a delay measurement device, a delay measurement system, and a delay measurement method. Background Art

[0002] During chip production, factors such as product batches and process drift can cause deviations between the actual chip timing and the designed timing model. These deviations can lead to inconsistent chip performance and even functional errors. Because these deviations are internal to the chip, they are almost impossible to measure after the chip is manufactured. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a delay measurement device, a delay measurement system and a delay measurement method to quickly and accurately measure the target delay of the input clock signal from the input end of the chip to be tested through the internal specified path to the output end.

[0004] The embodiment of the present application is implemented as follows:

[0005] In the first aspect, an embodiment of the present application provides a delay measurement device for measuring the target delay of an input clock signal from the input end of a chip to be tested to the output end via an internal specified path, the delay measurement device comprising: an adjustable delay circuit and a counter; the adjustable delay circuit comprises an odd number of delay devices with adjustable delay values, when the delay time of the adjustable delay circuit is consistent with the target delay amount and the ends of the adjustable delay circuit are connected, the adjustable delay circuit is used to generate an oscillation signal related to the target delay amount; the counter is used to count the number of oscillation cycles of the oscillation signal within a period of time, wherein the counting result is used to determine the target delay amount.

[0006] In an embodiment of the present application, when the delay time of the adjustable delay circuit is consistent with the target delay amount, connecting the ends of the adjustable delay circuit can generate an oscillation signal related to the target delay amount. Then, a counter is used to count the number of oscillation cycles of the oscillation signal within a period of time, and the target delay amount can be obtained based on the counting result, thereby quickly realizing the measurement of the target delay amount.

[0007] In combination with a possible implementation manner of the embodiment of the first aspect, the delay device includes: multiple inverters and adjustable capacitor modules connected in series, one adjustable capacitor module is connected between the output end of each level or multiple levels of inverters and the ground, and the delay time of the delay device is adjusted by adjusting the capacitance value of the adjustable capacitor module.

[0008] In the embodiment of the present application, a delay device with this structure is adopted, so that the delay time of the delay device can be adjusted by adjusting the capacitance value of the adjustable capacitor module, thereby achieving the purpose of timing and reducing the complexity of the circuit.

[0009] In combination with a possible implementation manner of the embodiment of the first aspect, the adjustable delay circuit is also used to delay the input clock signal and output a delayed clock signal; the delay measurement device also includes: a sampling circuit, used to sample the output signal of the output end of the chip to be tested according to the delayed clock signal to obtain a sampling signal; wherein the sampling signal is used to adjust the delay time of the adjustable delay circuit so that the delay time is consistent with the target delay amount.

[0010] In an embodiment of the present application, a sampling circuit is added to sample the output signal of the output end of the chip under test according to the delayed clock signal, and then the delay time of the adjustable delay circuit can be adjusted according to the sampling signal to make the delay time consistent with the target delay amount.

[0011] In combination with a possible implementation of the embodiment of the first aspect, the sampling circuit includes a trigger, a clock input end of the trigger is connected to the output end of the adjustable delay circuit, and a data input end of the trigger is connected to the output end of the chip to be tested.

[0012] In the embodiment of the present application, a trigger is used to form a sampling circuit, which can reduce circuit costs while achieving the sampling purpose.

[0013] In combination with a possible implementation manner of the embodiment of the first aspect, the delay measurement device also includes: a controller, used to adjust the delay time of the adjustable delay circuit to delay the input clock signal according to the sampling signal, so that the delay time is consistent with the target delay amount.

[0014] In the embodiment of the present application, by adding a controller, the adjustable delay circuit can be adjusted without the help of external control logic, which further increases convenience and applicability.

[0015] In combination with a possible implementation manner of the embodiment of the first aspect, the delay measurement device also includes: a selection circuit, which is connected to the adjustable delay circuit, and the selection circuit is used to select a clock signal from the input clock signal and the delayed clock signal and input it into the adjustable delay circuit.

[0016] In the embodiment of the present application, by adding a selection circuit to select the required input signal, the test efficiency and convenience can be improved, and during the test process, there is no need to manually change the connection method of the adjustable delay circuit.

[0017] In combination with a possible implementation of the embodiment of the first aspect, the counter includes: a logic switch and a counting module, the logic switch is used to allow the oscillation signal to pass through the logic switch within a period of time; the counting module is used to count the oscillation signal passing through the logic switch.

[0018] In the second aspect, an embodiment of the present application also provides a delay measurement system, comprising: a chip to be tested and a delay measurement device provided in accordance with the above-mentioned embodiment of the first aspect and / or any one of the embodiments in combination with the above-mentioned embodiment of the first aspect, wherein the delay measurement device is used to measure the target delay amount of the input clock signal from the input end of the chip to be tested to the output end via an internal specified path.

[0019] In a third aspect, an embodiment of the present application also provides a delay measurement method for measuring the target delay of an input clock signal from the input end of a chip to be tested through an internal specified path to the output end. The method comprises: using an adjustable delay circuit to generate an oscillation signal related to the target delay, wherein the adjustable delay circuit comprises an odd number of delay devices with adjustable delay values; counting the number of oscillation cycles of the oscillation signal within a period of time, and obtaining the target delay based on the counting result.

[0020] In combination with a possible implementation manner of the third aspect embodiment, before using the adjustable delay circuit to generate an oscillation signal related to the target delay amount, the method also includes: using the adjustable delay circuit to delay the input clock signal to obtain a delayed clock signal; using a sampling circuit to sample the output signal of the output end of the chip to be tested based on the delayed clock signal; adjusting the delay time of the adjustable delay circuit for delaying the input clock signal according to the sampling signal obtained by sampling, so that the delay time is consistent with the target delay amount; when the delay time is consistent with the target delay amount, connecting the ends of the adjustable delay circuit so that the adjustable delay circuit generates the oscillation signal.

[0021] In combination with a possible implementation manner of the third aspect, the chip to be tested is a memory; the delay time of the input clock signal delayed by the adjustable delay circuit is adjusted according to the sampling signal obtained by sampling, including: adjusting the initial delay value of the adjustable delay circuit to a minimum value, gradually increasing the delay value of the adjustable delay circuit until the sampling signal changes from a low level to a high level or from a high level to a low level, and keeping the delay value adjusted for the last time unchanged.

[0022] In combination with a possible implementation manner of the third aspect embodiment, the input end of the adjustable delay circuit is also connected to the output end of the selection circuit, and the method also includes: before using the adjustable delay circuit to delay the input clock signal, controlling the selection circuit to select and output the input clock signal from the input clock signal and the delayed clock signal; when the delay time is consistent with the target delay amount, controlling the selection circuit to select and output the delayed clock signal from the input clock signal and the delayed clock signal.

[0023] In combination with a possible implementation method of the third aspect, the chip to be tested is a memory; the number of oscillation cycles of the oscillation signal within a period of time is counted, and the target delay amount is obtained according to the counting result, including: counting the number of oscillation cycles of the oscillation signal generated when the data at the output end of the memory is 1 within a period of time, and obtaining a first delay amount according to the counting result; counting the number of oscillation cycles of the oscillation signal generated when the data at the output end of the memory is 0 within a period of time, and obtaining a second delay amount according to the counting result; obtaining the target delay amount according to the first delay amount and the second delay amount.

[0024] In the embodiment of the present application, the target delay is obtained by measuring the delay of the oscillation signal generated under different states, which can improve the accuracy of the target delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. The above and other purposes, features and advantages of the present application will be more clearly shown in the accompanying drawings. The same reference numerals indicate the same parts throughout the drawings. The drawings are not intentionally scaled to actual size, and the focus is on illustrating the main purpose of the present application.

[0026] Figure 1 A schematic diagram showing the principle of connecting a delay measurement device and a memory provided in an embodiment of the present application is shown.

[0027] Figure 2 A schematic diagram showing the principle of a delay device provided in an embodiment of the present application is shown.

[0028] Figure 3 A schematic diagram of the principle of an adjustable capacitor module provided in an embodiment of the present application is shown.

[0029] Figure 4A schematic diagram showing the principle of connecting another delay measurement device provided by an embodiment of the present application with a memory.

[0030] Figure 5 A schematic diagram showing the principle of a counter provided in an embodiment of the present application is shown.

[0031] Figure 6 A schematic diagram of measurement waveforms of a delay measurement device provided in an embodiment of the present application is shown.

[0032] Figure 7 A flow chart of a delay measurement method provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0034] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in the subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "comprise a..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

[0035] This application provides a delay measurement device, a delay measurement system, and a delay measurement method for measuring the target delay of an input clock signal from the input end of a chip under test through a specified internal path to the output end. The delays of various critical paths in a chip under test are difficult to measure after the chip is fabricated. However, using the solution described in this application, the target delays of the critical paths of different chips can be measured after the chip is fabricated, playing a key role in chip failure analysis, yield analysis, chip verification, and other aspects.

[0036] The chip to be tested takes memory (but not limited to memory) as an example. Figure 1, an explanation of the principle of measuring the target delay (represented by Tcq) of the read path of the memory (the path where the dotted line in the memory is located) using the delay measurement device provided in an embodiment of the present application.

[0037] The function of CLK is to enable the memory and ensure proper operation, producing a signal output from the DO pin. The time from the rising edge of the input clock signal CLK to the output (DO) is the memory read time, Tcq. This time is easily affected by factors such as process drift and manufacturing defects in the memory array, resulting in Tcq often exhibiting deviations exceeding ±20%. For example, while Tcq = 100ps in simulation, in actual production, Tcq may fluctuate between 80ps and 120ps. Using the aforementioned delay measurement device, Tcq can be quickly and accurately measured, playing a key role in chip failure analysis, yield analysis, and chip verification.

[0038] The delay measurement device shown in the present application includes: an adjustable delay circuit, a counter, and a sampling circuit. The sampling signal sampled by the sampling circuit is used to adjust the delay time (such as Tdelay) of the adjustable delay circuit so that the delay time is consistent with the target delay amount. When the delay time of the adjustable delay circuit is consistent with the target delay amount, the end to end of the adjustable delay circuit is connected to generate an oscillation signal related to the target delay amount. The counter is then used to count the number of oscillation cycles of the oscillation signal within a period of time. The target delay amount can be obtained based on the counting result, thereby quickly achieving the measurement of the target delay amount.

[0039] Among them, when the delay time of the adjustable delay circuit is consistent with the target delay amount, and the adjustable delay circuit is connected end to end, the adjustable delay circuit is used to generate an oscillation signal related to the target delay amount. The adjustable delay circuit includes an odd number (such as 3, but not limited to this) of delay devices with adjustable delay values connected in series. When the adjustable delay circuit is connected end to end, an oscillator can be formed. The time for the adjustable delay circuit to delay the input clock signal can be adjusted by adjusting the delay value of the delay device. When the delay time of the adjustable delay circuit is consistent with the target delay amount, the adjustable delay circuit is connected end to end to generate an oscillation signal related to the target delay amount. After the oscillation signal is generated, the number of oscillation cycles of the oscillation signal within a period of time is counted using a counter, and the target delay amount can be obtained according to the counting result, thereby quickly achieving the measurement of the target delay amount.

[0040] The structures of odd-numbered delay devices can be the same, for example, they all include: multiple inverters and adjustable capacitor modules connected in series, with an adjustable capacitor module connected between the output end of each level or multiple levels (two or more levels) of inverters and the ground, and the delay time of the delay device can be adjusted by adjusting the capacitance value of the adjustable capacitor module. Optionally, the circuit schematic diagram of the delay device is as follows Figure 2 shown. Figure 2The delay device shown includes 10 inverters (but not limited to this) and 4 adjustable capacitor modules (but not limited to this).

[0041] It is understandable that the number of inverters included in the delay device can be an odd number or an even number, as long as the delayed clock signal output by the adjustable delay circuit is ultimately opposite to the input clock signal.

[0042] The adjustable capacitor module may include multiple capacitor branches connected in parallel, each capacitor branch includes a capacitor and a transistor, and the capacitance value of the capacitor in each capacitor branch may be different. The schematic diagram is as follows: Figure 3 By controlling the on / off switching of transistors, the total capacitance of the adjustable capacitor module can be adjusted, thereby changing the delay value of the delay device. For example, when all transistors in the adjustable capacitor module are off, the delay value of the delay device is minimized. The delay value of the delay device can be adjusted by controlling the on / off switching of transistors.

[0043] It is understandable that the structure of the delay device is not limited to the above Figure 2 In the structure shown, in addition to adjusting the delay value of the delay device (related to the delay time) by adjusting the capacitor, the delay value of the delay device can also be adjusted by adjusting the operating voltage of the inverter. The delay device can be any delay device with adjustable delay value on the market.

[0044] In addition, the adjustable delay circuit is also used to delay the input clock signal and output a delayed clock signal. The delayed clock signal is opposite to the input clock signal and is represented by !CLK. At this time, the sampling circuit is used to sample the output signal of the output end of the chip under test according to the delayed clock signal to obtain a sampling signal. Among them, the sampling signal is used to adjust the delay time of the adjustable delay circuit so that the delay time is consistent with the target delay amount. It can be understood that the circuit only works when the delay time of the adjustable delay circuit needs to be adjusted. After the delay time of the adjustable delay circuit is consistent with the target delay amount Tcq, it no longer works. Therefore, under an optional embodiment, the delay measurement device may not include the sampling circuit. In this case, the target delay amount may only include the adjustable delay circuit and the counter.

[0045] Optionally, the sampling circuit includes a trigger, wherein the clock input terminal (!CLK, indicating falling edge sampling) of the trigger is connected to the output terminal of the adjustable delay circuit, the data input terminal (D) of the trigger is connected to the output terminal of the chip under test, and the data output terminal (Q) of the trigger is used to output the sampling signal. Optionally, the trigger can be a D trigger or a level trigger. The D trigger can be a non-inverting D trigger or an inverting D trigger. Since the delayed clock signal is opposite to the input clock signal, in order to ensure timing consistency, the trigger is a falling edge sampling trigger.

[0046] It should be noted that Figure 1 Only one of the two input branches of the adjustable delay circuit is valid at the same time. For example, when adjusting the delay time of the adjustable delay circuit, input branch 1 (the branch where CLK is located) is valid. At this time, the end of the adjustable delay circuit is not connected. When the delay time of the adjustable delay circuit is consistent with the target delay amount, input branch 2 (the branch where RO is located) is valid, that is, the end of the adjustable delay circuit is connected. In other words, the input signal of the adjustable delay circuit is either the input clock signal or the delayed clock signal.

[0047] To facilitate selection of an input signal for the adjustable delay circuit, in one optional embodiment, the delay measurement device further includes a selection circuit connected to the adjustable delay circuit and configured to select a clock signal from the input clock signal and the delayed clock signal and input the selected clock signal into the adjustable delay circuit.

[0048] Optionally, the selection circuit may include a two-choice selector (MUX), one input end of the selector is used to receive the input clock signal, the other input end of the selector is used to receive the delayed clock signal, and the output end of the selector is connected to the input end of the adjustable delay circuit. The circuit schematic diagram is shown in FIG. Figure 4 It is understood that, in addition to the selector, the selection circuit can also use two switches to achieve similar functions.

[0049] The counter includes a logic switch and a counting module. The logic switch is used to allow the oscillation signal to pass through the logic switch within a period of time (CNT_ENB); and the counting module is used to count the oscillation signal passing through the logic switch.

[0050] Optionally, the logic switch may include an inverter and an XOR gate, wherein the inverter input is used to receive an oscillating signal, the inverter output is connected to the first input of the XOR gate, and the second input of the XOR gate is used to receive a fixed time value (CNT_ENB). For example, CNT_ENB may be 100 crystal oscillator periods (the crystal oscillator period is very fixed). When CNT_ENB is low, the output of the XOR gate is completely dependent on the signal at the first input (the inverter output signal).

[0051] It is understood that other logic gates that achieve the same function as the inverter + XOR gate can also be used. For example, the inverter + XOR gate can be replaced with a NOR gate. In this case, the logic switch includes a NOR gate, the first input of which is used to receive the oscillating signal, and the second input of the NOR gate is used to receive CNT_ENB. When CNT_ENB is low, the output of the NOR gate is completely dependent on the signal at its first input. Furthermore, the NOR gate can be replaced with a NAND gate, in which case CNT_ENB is simply switched from a low level to a high level.

[0052] The counting module includes multiple triggers connected in series, and its schematic diagram is as follows Figure 5 As shown in the figure, each time CLK oscillates, C[3:0] increments by one position, for example: 0001 > 0010 > 0011 > ................... > 1111. Ultimately, simply divide the CNT_ENB enabled time by the counter value to obtain the oscillation signal's oscillation period (denoted as Tro). The oscillation period is then divided by 2 to obtain Tcq. Tdelay = Tcq = Tro / 2. Tro = CNT_ENB enabled time / counter value.

[0053] It is understandable that the precision of the counter is not limited to C[3:0], it can support C[29:0]. When more bits are needed to ensure precision, more triggers can be connected in series. For example, when the precision is C[7:0], it is necessary to Figure 5 On this basis, 4 more triggers are connected in series.

[0054] For a better understanding, the following Figure 4 Continuing with the above example, assuming Tcq can be between 80ps and 120ps, as long as the adjustable delay circuit's adjustable range is guaranteed, it can cover the 80ps to 120ps range with a small margin. For example, the adjustable delay circuit's delay time range is 70ps to 130ps. Too large a range will result in design waste.

[0055] When the circuit is operating, input branch 1 is enabled, and CLK passes through the adjustable delay circuit and reaches the sampling circuit to sample DO. If the data stored in the memory is 1 (it can also be 0), the delay of CLK > DO is 100ps. To adjust the delay time of the adjustable delay circuit, first set the initial delay value to the minimum (assuming 70ps). Then gradually increase the delay value until the sampling signal output by the non-inverting trigger transitions from low to high (for an inverting trigger, the sampling signal transitions from high to low), maintaining the last adjusted delay value. As the delay time of the adjustable delay circuit gradually increases, when the delay time reaches 100ps, the data from DO can be sampled to the Q terminal. At this point, input branch 2 is enabled, and the adjustable delay circuit generates an oscillating signal related to the target delay value.

[0056] If the data stored in the memory is 0, the process of adjusting the delay time of the adjustable delay circuit is similar to that when the stored data is 1. For example, the initial delay value of the adjustable delay circuit is first adjusted to the minimum value (assuming it is 70ps), and then the delay value of the adjustable delay circuit is gradually increased until the sampling signal output by the in-phase trigger changes from a high level to a low level (if it is an inverting trigger, the sampling signal changes from a low level to a high level), and the delay value adjusted for the last time is kept unchanged.

[0057] The waveform diagram of the delay measurement device is as follows Figure 6 shown. Figure 6 CLK in the figure is the sampling clock of the trigger, indicating falling edge sampling. By gradually increasing the delay value of the adjustable delay circuit until DO just changes from 0 to 1, or when DO just changes from 1 to 0, the delay value of the adjustable delay circuit is stopped. For the accuracy of the test, the output values of different DOs can be measured so that the D trigger can correctly sample whether the memory stores 1 or 0. For example, the measurement is performed when DO is 1 and 0 respectively. It should be noted that Figure 6 The sampling near the left side is successful, the corresponding DO is 1, and the data stored in the memory is 1; Figure 6 The sampling near the right side is successful, the corresponding DO is 0, and the data stored in the memory is 0.

[0058] When the data at the memory output is 1, the delay time of the adjustable delay circuit is adjusted until the sampling signal output by the in-phase trigger changes from a low level to a high level, the number of oscillation cycles of the oscillation signal generated when the data at the memory output is 1 within a period of time is counted, and a first delay amount is obtained based on the counting result. When the data at the memory output is 0, the delay time of the adjustable delay circuit is adjusted until the sampling signal output by the in-phase trigger changes from a high level to a low level, the number of oscillation cycles of the oscillation signal generated when the data at the memory output is 0 within a period of time is counted, and a second delay amount is obtained based on the counting result. Thereafter, a target delay amount is obtained based on the first delay amount and the second delay amount, for example, the target delay amount = (first delay amount + second delay amount) / 2.

[0059] To facilitate adjustment of the delay value of the adjustable delay circuit, in one optional embodiment, the delay measurement device further includes a controller configured to adjust the delay time of the input clock signal by the adjustable delay circuit based on the sampling signal, so that the delay time is consistent with a target delay value. Optionally, the controller is configured to generate a control signal CTLL<4:0> for adjusting the capacitance value of the adjustable capacitor module, thereby adjusting the delay value of the adjustable delay circuit.

[0060] Based on the same inventive concept, an embodiment of the present application also provides a delay measurement system, including a chip to be tested and the above-mentioned delay measurement device, the delay measurement device is used to measure the target delay amount of the input clock signal from the input end of the chip to be tested through an internal specified path to the output end.

[0061] The chip under test may be a memory, a processor, etc. The memory may be, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc.

[0062] The processor may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor may be a microprocessor or any conventional processor.

[0063] The delay measurement device provided in the delay measurement system embodiment has the same implementation principle and technical effects as the aforementioned delay measurement device embodiment. For the sake of brief description, for matters not mentioned in the delay measurement system embodiment, reference can be made to the corresponding content in the aforementioned delay measurement device embodiment.

[0064] Based on the same inventive concept, the embodiment of the present application also provides a delay measurement method for measuring the target delay of the input clock signal from the input end of the chip to be tested to the output end through the internal specified path. Figure 7 The delay measurement method provided in the embodiment of the present application is described.

[0065] S1: Using an adjustable delay circuit to generate an oscillation signal related to the target delay amount.

[0066] Among them, the adjustable delay circuit includes an odd number of delay devices with adjustable delay values. When the delay time of the adjustable delay circuit is consistent with the target delay amount and the adjustable delay circuits are connected end to end, an oscillation signal related to the target delay amount can be generated.

[0067] Before S1, the delay measurement method also includes: using an adjustable delay circuit to delay the input clock signal to obtain a delayed clock signal; using a sampling circuit to sample the output signal of the output end of the chip to be measured based on the delayed clock signal; adjusting the delay time of the adjustable delay circuit to delay the input clock signal according to the sampling signal obtained by sampling, so that the delay time is consistent with the target delay amount; when the delay time is consistent with the target delay amount, connecting the ends of the adjustable delay circuit to make the adjustable delay circuit generate an oscillation signal.

[0068] Optionally, the chip to be tested is a memory, and the process of adjusting the delay time of the input clock signal by the adjustable delay circuit according to the sampling signal obtained by sampling includes: adjusting the initial delay value of the adjustable delay circuit to the minimum value, gradually increasing the delay value of the adjustable delay circuit until the sampling signal changes from a low level to a high level or from a high level to a low level, and keeping the delay value adjusted for the last time unchanged.

[0069] The input end of the adjustable delay circuit is also connected to the output end of the selection circuit. The delay measurement method also includes: before S1, controlling the selection circuit to select and output the input clock signal from the input clock signal and the delayed clock signal; when the delay time is consistent with the target delay amount, controlling the selection circuit to select and output the delayed clock signal from the input clock signal and the delayed clock signal.

[0070] S2: Counting the number of oscillation cycles of the oscillation signal within a period of time, and obtaining the target delay amount according to the counting result.

[0071] Optionally, the chip to be tested is a memory; the specific implementation process of S2 can be: counting the number of oscillation cycles of the oscillation signal generated when the data at the output end of the memory is 1 within a period of time, and obtaining a first delay amount according to the counting result; counting the number of oscillation cycles of the oscillation signal generated when the data at the output end of the memory is 0 within a period of time, and obtaining a second delay amount according to the counting result; obtaining a target delay amount according to the first delay amount and the second delay amount.

[0072] The implementation principle and technical effects provided by the method embodiment are the same as those of the aforementioned delay measurement device embodiment. For the sake of brief description, for matters not mentioned in the method embodiment, reference can be made to the corresponding content in the aforementioned delay measurement device embodiment.

[0073] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0074] In addition, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0075] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A delay measurement device, characterized in that: The device is used to measure the target delay of the input clock signal from the input end of the chip to be tested to the output end via the internal specified path. The delay measurement device includes: An adjustable delay circuit, comprising an odd number of delay devices with adjustable delay values, wherein when the delay time of the adjustable delay circuit is consistent with the target delay amount and the input end and the output end of the adjustable delay circuit are connected, the adjustable delay circuit is used to generate an oscillation signal related to the target delay amount; The counter is used to count the number of oscillation cycles of the oscillation signal within a period of time, wherein the counting result is used to determine the target delay amount.

2. The delay measurement device according to claim 1, characterized in that: The delay device includes: multiple inverters and adjustable capacitor modules connected in series, one adjustable capacitor module is connected between the output end of each level or multiple levels of inverters and the ground, and the delay time of the delay device is adjusted by adjusting the capacitance value of the adjustable capacitor module.

3. The delay measurement device according to claim 1, characterized in that: The adjustable delay circuit is further used to delay the input clock signal and output a delayed clock signal; The delay measurement device further includes: a sampling circuit for sampling an output signal of an output terminal of the chip to be tested according to the delayed clock signal to obtain a sampling signal; The sampling signal is used to adjust the delay time of the adjustable delay circuit so that the delay time is consistent with the target delay amount.

4. The delay measurement device according to claim 3, characterized in that: The sampling circuit includes a trigger, a clock input end of the trigger is connected to the output end of the adjustable delay circuit, and a data input end of the trigger is connected to the output end of the chip to be tested.

5. The delay measurement device according to claim 3, characterized in that: The delay measurement device further includes: a controller for adjusting a delay time of the input clock signal delayed by the adjustable delay circuit according to the sampling signal, so that the delay time is consistent with the target delay amount.

6. The delay measurement device according to claim 3, characterized in that: The delay measurement device further includes: a selection circuit connected to the adjustable delay circuit, the selection circuit being configured to select a clock signal from the input clock signal and the delayed clock signal and input the clock signal into the adjustable delay circuit.

7. The delay measurement device according to any one of claims 1 to 6, characterized in that: The counter comprises: a logic switch, configured to allow the oscillation signal to pass through the logic switch within a period of time; A counting module is used to count the oscillation signal passing through the logic switch.

8. A delay measurement system, characterized in that: include: A chip under test and a delay measurement device according to any one of claims 1 to 7, wherein the delay measurement device is used to measure a target delay amount of an input clock signal from an input end of the chip under test to an output end via an internal specified path.

9. A delay measurement method, characterized in that: The method is used to measure the target delay of an input clock signal from the input end of a chip under test to the output end via an internal specified path, and the method includes: An oscillating signal related to the target delay is generated using an adjustable delay circuit, wherein the adjustable delay circuit includes an odd number of delay devices with adjustable delay values, and when the delay time of the adjustable delay circuit is consistent with the target delay amount and the input end and output end of the adjustable delay circuit are connected, the adjustable delay circuit is used to generate the oscillating signal related to the target delay amount; The number of oscillation cycles of the oscillation signal within a period of time is counted, and the target delay amount is obtained according to the counting result.

10. The method according to claim 9, characterized in that Before using the adjustable delay circuit to generate an oscillation signal related to the target delay amount, the method further includes: Delaying the input clock signal using the adjustable delay circuit to obtain a delayed clock signal; Using a sampling circuit to sample an output signal of an output terminal of the chip under test based on the delayed clock signal; Adjusting the delay time of the input clock signal by the adjustable delay circuit according to the sampling signal obtained by sampling, so that the delay time is consistent with the target delay amount; When the delay time is consistent with the target delay amount, the input end and the output end of the adjustable delay circuit are connected to make the adjustable delay circuit generate the oscillation signal.

11. The method according to claim 10, characterized in that The chip to be tested is a memory; and adjusting the delay time of the input clock signal by the adjustable delay circuit according to the sampling signal obtained by sampling includes: The initial delay value of the adjustable delay circuit is adjusted to the minimum value, and the delay value of the adjustable delay circuit is gradually increased until the sampling signal changes from a low level to a high level or from a high level to a low level, and the delay value adjusted last time is kept unchanged.

12. The method according to claim 10, characterized in that The input end of the adjustable delay circuit is also connected to the output end of the selection circuit, and the method further includes: Before using the adjustable delay circuit to delay the input clock signal, controlling the selection circuit to select and output the input clock signal from the input clock signal and the delayed clock signal; When the delay time is consistent with the target delay amount, the selection circuit is controlled to select and output the delayed clock signal from the input clock signal and the delayed clock signal.

13. The method according to claim 9, characterized in that The chip to be tested is a memory; Counting the number of oscillation cycles of the oscillation signal within a period of time and obtaining the target delay according to the counting result includes: Counting the number of oscillation cycles of the oscillation signal generated when the data at the output end of the memory is 1 within a period of time, and obtaining a first delay amount according to the counting result; Counting the number of oscillation cycles of the oscillation signal generated when the data at the output end of the memory is 0 within a period of time, and obtaining a second delay amount according to the counting result; The target delay is obtained according to the first delay and the second delay.

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