Wafer Notch Detection Methods and Equipment
By aligning and preprocessing the template image and the measurement image, and using Fourier transform and cross-correlation matrix to calculate the offset vector, the problem of blurred or broken wafer notch edges is solved, and high-precision wafer notch detection is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI PRECISION MEASUREMENT SEMICON TECH INC
- Filing Date
- 2022-12-15
- Publication Date
- 2026-06-30
AI Technical Summary
Existing technologies struggle to extract wafer notch shapes when the wafer notch edges are clear, especially when the edges are blurred, broken, or partially missing due to etched patterns and out-of-focus image capture. This makes it difficult to accurately locate the wafer notch position.
By preparing template images, extracting the contour point set of wafer notches, preprocessing and aligning the measured images, calculating the offset vector using Fourier transform and cross-correlation matrix, adjusting the contour line of the wafer notches, and combining attention mechanism to enhance contrast and denoise processing, the wafer notches are accurately located.
This technology enables high-precision extraction of wafer notch contours under complex operating conditions, solving the detection difficulties caused by etched patterns and image defocusing, and achieving accurate positioning of wafer notch locations.
Smart Images
Figure CN116091417B_ABST
Abstract
Description
Technical Field
[0001] The embodiments of this disclosure relate to a wafer notch detection method and a wafer notch detection device. Background Technology
[0002] In the manufacturing and testing of integrated circuits, after the wafers on the machine are pre-aligned, the accuracy of the wafer center and notch angle may not meet the requirements, necessitating wafer positioning calibration. This generally includes two parts: wafer center positioning and notch positioning. Currently, the main methods for detecting wafer notches are to extract the wafer notch contour line using image segmentation or subtraction of similar region images, thereby calculating the wafer notch features (center point, centroid, etc.). When the wafer notch edge is clear, the above methods can obtain the wafer notch contour line. However, with improvements in wafer manufacturing processes, etched patterns appear around the wafer notch, causing the notch edge line to become blurred, broken, or partially missing. Due to different process designs, the notch edge line defects vary, making it impossible to repair using a uniform template algorithm. Furthermore, defocusing during image capture leading to blurred edges and low image contrast making edge extraction difficult also contribute to the difficulty in extracting the wafer notch shape and determining its location. Summary of the Invention
[0003] In view of the problems in the prior art, the purpose of this disclosure is to provide a wafer notch detection method and a wafer notch detection device.
[0004] At least one embodiment of this disclosure provides a wafer notch detection method, the method comprising: preparing a template image of the wafer notch; extracting a set of contour points of the wafer notch from the template image; acquiring a measurement image of the wafer notch; preprocessing the measurement image to obtain a processed measurement image; aligning the template image and the processed measurement image to obtain an offset vector of the processed measurement image relative to the template image; and obtaining the final contour line of the wafer notch based on the offset vector.
[0005] For example, in the wafer notch detection method provided in at least one embodiment of this disclosure, the measurement image is preprocessed, including: reassigning the pixel values of all pixels in the measurement image to increase the contrast between the wafer portion and the non-wafer portion in the measurement image.
[0006] For example, in the wafer notch detection method provided in at least one embodiment of this disclosure, reassigning the pixel values of all pixels in the measurement image includes: denoising the measurement image to obtain a first processed image; analyzing the pixel value distribution of the first processed image, wherein the pixel value distribution is the percentage of the number of pixels corresponding to each pixel value in the first processed image; obtaining a first pixel threshold and a second pixel threshold of the first processed image based on the pixel value distribution of the first processed image, and reassigning the pixel values of all pixels in the first processed image based on the first pixel threshold and the second pixel threshold, wherein the first pixel threshold corresponds to the pixel values of the non-wafer portion in the first processed image, and the second pixel threshold corresponds to the pixel values of the wafer portion in the first processed image.
[0007] For example, in the wafer notch detection method provided in at least one embodiment of this disclosure, the first pixel threshold satisfies: w is the scaling factor, k1 is the first pixel threshold, and k p1 The pixel value that corresponds to the largest proportion of the non-wafer portion in the first processed image. This represents the percentage of pixels with a pixel value of k1. The pixel value is k p1 The percentage of pixels; the second pixel threshold satisfies: w is the scaling factor, k2 is the second pixel threshold, and k p2 The pixel value that corresponds to the largest proportion of the wafer portion in the first processed image. This represents the percentage of pixels with a pixel value of k2. The pixel value is k p2 The percentage of pixels; reassigning pixel values to all pixels in the first processed image based on the first pixel threshold and the second pixel threshold, including: adjusting the pixel values of the first processed image according to the following formula to obtain the pixel values of the processed measurement image.
[0008] For example, in the wafer notch detection method provided in at least one embodiment of this disclosure, image alignment of the template image and the processed measurement image includes: performing Fourier transform on the template image and the processed measurement image respectively to obtain the frequency domain representation F of the template image. R The frequency domain representation of the processed measurement image F T ; Calculate the frequency domain representation of F R and frequency domain representation F T The cross-correlation coefficients are calculated to obtain the cross-correlation coefficient matrix; and the maximum value is searched in the cross-correlation coefficient matrix, and the coordinates of the maximum value in the cross-correlation coefficient matrix are used as the offset vector of the processed measurement image relative to the template image.
[0009] For example, in the wafer notch detection method provided in at least one embodiment of this disclosure, obtaining the final wafer notch contour point set based on the offset vector includes: translating the wafer notch contour point set in the template image based on the offset vector to obtain the wafer notch contour point set in the processed measurement image, and determining the final wafer notch contour line based on the wafer notch contour point set in the processed measurement image.
[0010] For example, in the wafer notch detection method provided in at least one embodiment of this disclosure, the final wafer notch contour line is obtained based on the offset vector, and the method further includes: after obtaining the wafer notch contour point set in the processed measurement image, adjusting the wafer notch contour point set in the processed measurement image to determine the final wafer notch contour line.
[0011] For example, in the wafer notch detection method provided in at least one embodiment of this disclosure, adjusting the contour point set of the wafer notch in the processed measurement image includes: translating each point of the contour point set of the wafer notch in the processed measurement image as the center to obtain an m×n contour point set matrix, where m and n are both integers greater than 1; calculating the score of all contour point sets in the contour point set matrix; and determining the final contour line of the wafer notch based on the contour point set corresponding to the maximum value in the score.
[0012] For example, in the wafer notch detection method provided in at least one embodiment of this disclosure, calculating the score of all contour point sets in the contour point set matrix includes: taking the sum of the pixel value differences between two adjacent pixels in each contour point set in a direction perpendicular to the contour line direction corresponding to the contour point set as the score of the contour point set.
[0013] At least one embodiment of this disclosure also provides a wafer notch detection device, including: a processor; a memory storing executable instructions of the processor, the processor being configured to perform the steps of the wafer notch detection method provided in at least one embodiment of this disclosure by executing the executable instructions.
[0014] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure.
[0015] The wafer notch detection method and equipment disclosed herein have the following beneficial effects:
[0016] This wafer notch detection method can solve the problem of difficulty in detecting wafer notch shape caused by blurred, broken or partially missing edge lines of wafer notches due to etched patterns or out-of-focus images near the wafer notch. Attached Figure Description
[0017] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.
[0018] Figure 1 A schematic flowchart illustrating a wafer notch detection method provided for at least one embodiment of this disclosure;
[0019] Figure 2 A schematic flowchart of step S103 provided for at least one embodiment of this disclosure;
[0020] Figure 3 This is a schematic diagram of a template image for a wafer notch.
[0021] Figure 4 This is a schematic diagram of a measurement image of a wafer notch;
[0022] Figure 5 A pixel value histogram of a first processed image provided for at least one embodiment of this disclosure;
[0023] Figure 6 A schematic diagram of a processed measurement image provided for at least one embodiment of this disclosure;
[0024] Figure 7 This is a schematic diagram showing the frequency domain representation of a template image of a wafer notch and the processed measurement image after Fourier transform.
[0025] Figure 8 This is a schematic diagram of a merged image obtained by aligning a template image with a processed measurement image;
[0026] Figure 9 A schematic block diagram of a wafer notch detection device provided in at least one embodiment of this disclosure;
[0027] Figure 10 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure. Detailed Implementation
[0028] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0029] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.
[0030] The flowchart shown in the attached diagram is merely an illustrative example and does not necessarily include all steps. For example, some steps may be broken down, while others may be combined or partially combined. Therefore, the actual execution order may change depending on the specific circumstances.
[0031] To address the aforementioned technical problems, this disclosure proposes a novel technical solution that aligns the template image with the measurement image based on an attention mechanism, and calculates the shape and features of the measurement image. This solution can resolve the issue of difficulty in detecting the shape and features of wafer notches caused by blurred, broken, or partially missing edge lines due to etched patterns near the wafer notch or out-of-focus image capture.
[0032] Figure 1 This is a schematic flowchart illustrating a wafer notch detection method provided for at least one embodiment of the present disclosure.
[0033] like Figure 1 As shown, the wafer notch detection method includes the following steps S101 to S104.
[0034] Step S101: Prepare a template image of the wafer notch and extract the contour point set of the wafer notch from the template image.
[0035] The template image contains a complete and clear wafer notch edge, with no etching marks on the wafer portion. The grayscale of the non-wafer portion (such as the equipment portion) has a large contrast with the grayscale of the wafer portion. Generally, the equipment portion is blackish and the wafer portion is whiter.
[0036] For example, the template image is binarized, and then the outline of the wafer notch is extracted to obtain the outline point set of the wafer notch. The outline point set is all the pixels that make up the outline.
[0037] Step S102: Obtain a measurement image of the wafer notch, preprocess the measurement image to obtain a processed measurement image.
[0038] For example, preprocessing the measurement image based on an attention mechanism can increase the distinction between non-wafer parts (e.g., equipment parts) and wafer parts in the measurement image to facilitate subsequent processing.
[0039] Step S103: Align the template image and the processed measurement image to obtain the offset vector of the processed measurement image relative to the template image.
[0040] Step S104: Obtain the final wafer notch contour based on the offset vector.
[0041] For example, in some embodiments of this disclosure, step S102 may include: reassigning pixel values to all pixels of the measurement image to increase the contrast between the wafer portion and the non-wafer portion of the measurement image.
[0042] For example, in some embodiments of this disclosure, reassigning pixel values to all pixels of a measured image may include the following steps S1 to S3.
[0043] Step S1: Denoise the measured image to obtain the first processed image.
[0044] For example, Gaussian blurring can be applied to a measurement image to remove noise.
[0045] It should be noted that Gaussian blur is just an example, and this disclosure does not limit the denoising method. For example, other methods can be selected for denoising, such as mean filtering, median filtering, and non-local means (NLM).
[0046] Step S2: Analyze the pixel value distribution of the first processed image.
[0047] For example, the pixel value distribution is the percentage of the number of pixels corresponding to each pixel value in the first processed image.
[0048] Step S3: Obtain the first pixel threshold and the second pixel threshold of the first processed image based on the pixel value distribution of the first processed image, and reassign the pixel values of all pixels in the first processed image based on the first pixel threshold and the second pixel threshold.
[0049] For example, the first pixel threshold corresponds to the pixel value of the non-wafer portion in the first processed image, and the second pixel threshold corresponds to the pixel value of the wafer portion in the first processed image.
[0050] For example, in some embodiments of this disclosure, the first pixel threshold satisfies the following formula (1):
[0051]
[0052] Where w is the scaling factor, k1 is the first pixel threshold, and k p1 The pixel value that corresponds to the largest proportion of the non-wafer portion in the first processed image. This represents the percentage of pixels with a pixel value of k1. The pixel value is k p1 The percentage of pixels.
[0053] For example, in some embodiments of this disclosure, the second pixel threshold satisfies the following formula (2):
[0054]
[0055] Where w is the scaling factor, k2 is the second pixel threshold, and k p2 The pixel value that corresponds to the largest proportion of the wafer portion in the first processed image. This represents the percentage of pixels with a pixel value of k2. The pixel value is k p2 The percentage of pixels.
[0056] For example, in some embodiments of this disclosure, the pixel values of all pixels in the first processed image can be reassigned according to the following formula (3) to obtain the pixel values of the processed measurement image:
[0057]
[0058] Where k′ is the pixel value of the processed measurement image, k is the pixel value of the first processed image, k1 is the first pixel threshold, and k2 is the second pixel threshold.
[0059] By reassigning pixel values to the first processed image, grayscale variations within a certain range in the non-wafer and wafer portions of the measured image can be eliminated, i.e., the effects of illumination, machine texture captured under out-of-focus conditions, and etching details on the wafer can be eliminated, thereby allowing attention to be focused on the integrity of the non-wafer and wafer portions and the differences between them.
[0060] Figure 2 A schematic flowchart of step S103 provided for at least one embodiment of this disclosure.
[0061] like Figure 2 As shown, step S103 includes the following steps S201 to S203.
[0062] Step S201: Perform Fourier transform on the template image and the processed measurement image respectively to obtain the frequency domain representation F of the template image. R The frequency domain representation of the processed measurement image F T .
[0063] For example, Fourier transform is performed on the template image and the processed measurement image using the following formula (4):
[0064]
[0065] Where f(x, y) represents the pixel value of pixel (x, y) in the template image or the processed measurement image, u = 0, 1, 2, ..., M-1; v = 0, 1, 2, ..., N-1; M and N represent the length and width of the template image or the processed measurement image, respectively, that is, the template image or the processed measurement image includes N rows and M columns of pixels.
[0066] Step S202: Calculate the frequency domain representation F R and frequency domain representation F T The cross-correlation coefficients are used to obtain the cross-correlation coefficient matrix.
[0067] For example, the cross-correlation matrix C is calculated using the following formula (5):
[0068] C = conjugate(F) R )*F T (5)
[0069] Among them, conjugate(F R ) represents F R The conjugate of complex numbers.
[0070] Step S203: Search for the maximum value in the cross-correlation matrix, and use the coordinates of the maximum value in the cross-correlation matrix as the offset vector of the processed measurement image relative to the template image.
[0071] For example, in some embodiments of this disclosure, step S104 may include: translating the wafer notch contour point set in the template image based on the offset vector to obtain the wafer notch contour point set in the processed measurement image, and determining the final wafer notch contour line based on the wafer notch contour point set in the processed measurement image.
[0072] For example, by superimposing the contour point set of the wafer notch in the template image with the calculated offset vector, the contour point set of the wafer notch in the processed measurement image is obtained, and the contour point set of the wafer notch in the processed measurement image constitutes the final wafer notch contour line.
[0073] For example, in some embodiments of this disclosure, step S104 may further include: after obtaining the contour point set of the wafer notch in the processed measurement image, adjusting the contour point set of the wafer notch in the processed measurement image to determine the final contour line of the wafer notch.
[0074] Since the wafer may have a slight tilt on the machine, the contour line obtained by translating the contour point set of the wafer notch in the template image based on the offset vector may have a slight deviation from the actual shape. The final notch contour line can be searched near the contour line obtained by translation to improve accuracy.
[0075] For example, in some embodiments of this disclosure, adjusting the contour point set of wafer notches in the processed measurement image may include the following steps S4 to S6.
[0076] Step S4: Translate the contour point set of the wafer notch in the processed measurement image with each point as the center to obtain an m×n contour point set matrix. m and n are both integers greater than 1.
[0077] For example, the set of contour points of the wafer notch in the processed measurement image is represented as: Where x represents the set of contour points The x-coordinate / column of the mid-pixel, y represents the set of contour points. The ordinate of a pixel per row. For example, in one embodiment, using... Centered on the target, the target is shifted 2 pixels to the left and right in the x-direction (maximum shift of 2 pixels in the x-direction), and 2 pixels up and down in the y-direction (maximum shift of 2 pixels in the y-direction). After all the translation operations are completed, a 5×5 (i.e., m=5, n=5) contour point set matrix M is obtained. con :
[0078]
[0079] The above expression represents the 25 contour point sets obtained after translation, represented by matrix M. con The set of contour points in the first row and second column of the middle For example, this contour point set is the contour point set of the wafer notch in the processed measurement image. It is obtained by shifting the entire object 1 pixel to the left in the x-direction and shifting it 2 pixels downward in the y-direction.
[0080] Step S5: Calculate the score of all contour point sets in the contour point set matrix.
[0081] For example, in some embodiments of this disclosure, calculating the score of all contour point sets in the contour point set matrix may include: taking the sum of the pixel value differences between two adjacent pixels in each contour point set in a direction perpendicular to the contour line direction corresponding to that contour point set as the score of that contour point set. The contour line direction is the overall direction of the wafer notch contour line. Figure 3 For example, the direction of the wafer notch outline in the diagram is the x-direction.
[0082] For example, the contour point set matrix M con The set of contour points corresponding to the i-th row and j-th column is represented as Contour point set S rating i，j The calculation is performed using the following formula (6):
[0083]
[0084] Where T(x, y+1)-T(x, y-1) represents the pixel (x, y) in relation to the contour point set. The pixel value difference between two adjacent pixels in the direction perpendicular to the contour line. For example, the 5×5 contour point set matrix M in step S4 can be obtained using formula (6). con The scores for each set of contour points are used to obtain a 5×5 score matrix S.
[0085] Step S6: Determine the final wafer notch contour line based on the contour point set corresponding to the maximum value in the score.
[0086] The wafer notch detection method provided in this disclosure will be illustrated by an example below.
[0087] First, prepare a template image of the wafer notch, such as... Figure 3 As shown. In Figure 3 In the image, the non-fractal areas appear blackish, while the wafer areas appear whiter. The wafer notch edges are complete and clear, and there are no etching marks on the wafer areas. The contrast between the grayscale of the non-fractal areas and the grayscale of the wafer areas is relatively large.
[0088] Then, the template image is binarized to extract the contour point set Con of the wafer notch in the template image. x，y Contour point set Con x，y All the pixels in the graph form the outline of the wafer notch.
[0089] Then, acquire a measurement image of the wafer notch, such as... Figure 4 As shown. In Figure 4 As can be seen, the contrast between the grayscale of the non-wafer area and the grayscale of the wafer area is small, the edge of the wafer notch is blurred, and there are etching marks on the wafer area. Traditional methods cannot accurately extract the outline of the wafer notch.
[0090] Then, to Figure 4 The measured image shown is Gaussian blurred to remove noise, resulting in a first processed image. For example, in this embodiment, the Gaussian convolution kernel is (11, 11), and the standard deviation σ is 2.
[0091] Then, the pixel value distribution of the first processed image is analyzed to obtain the pixel value histogram of the first processed image, such as... Figure 5 As shown. In Figure 5 In the histogram, the x-axis represents the pixel value k of the first processed image, and the y-axis represents H. k =n k / N (k = 0, 1, 2, ..., 255), where N is the total number of pixels in the first processed image, nk This represents the number of pixels with a pixel value of k in the first processed image. Figure 5 The portion enclosed by the dashed box numbered 1 corresponds to the non-wafer part, that is, the non-wafer part corresponds to the portion with low pixel values in the first processed image. Figure 5 The part enclosed by the dashed box number 2 corresponds to the wafer portion, that is, the wafer portion corresponds to the part with high pixel values in the first processed image; the wafer notch outline is located at the junction of the wafer portion and the non-wafer portion, that is, the pixel value of the pixel of the wafer notch outline in the first processed image is between the dashed boxes 1 and 2.
[0092] Then, in Figure 5 The first pixel threshold k1 and the second pixel threshold k2 of the first processed image are obtained from the pixel value histogram shown. The first pixel threshold k1 needs to satisfy the above formula (1), and the second pixel threshold k2 needs to satisfy the above formula (2). The w in formula (1) and formula (2) can be taken as 0.3 based on experience.
[0093] Then, based on the first pixel threshold k1 and the second pixel threshold k2, the pixel values of all pixels in the first processed image are reassigned according to the above formula (3) to obtain the processed measurement image, as shown in the figure. Figure 6 As shown. In Figure 6 From this, we can see that... Figure 4 compared to, Figure 6 The pixel value variations within a certain range in both the non-wafer and wafer portions were eliminated, allowing attention to be focused on the overall integrity of the non-wafer and wafer portions and the differences between them.
[0094] Then, Fourier transforms are performed on the template image and the processed measurement image according to the above formula (4) to obtain the frequency domain representation F of the template image and the processed measurement image. R and F T Visual display such as Figure 7 As shown.
[0095] Then, the frequency domain representation F is calculated using the above formula (5). R and F T The cross-correlation coefficients between the elements are used to obtain the cross-correlation coefficient matrix C. The maximum value is then searched within cross-correlation coefficient matrix C to obtain the coordinates (x, y) of the maximum value within C. s y s ), (x s y s This is the offset vector of the processed measurement image relative to the template image.
[0096] Use (x) s y s ) through formula Adjust F T get Through formula right Perform an inverse Fourier transform to obtain the image T aligned with the template image. s Image T s When concatenated with the template image, the result is as follows: Figure 8 As shown. From Figure 8 As can be seen, the alignment effect between the measurement image and the template image is very good. The alignment method provided in this disclosure can solve the problem that the measurement image and the template image are too different due to the diverse changes in the etched part above the wafer notch, thus making image alignment impossible.
[0097] Then, the wafer notch contour point set Con of the template image is... x，y With the calculated offset vector (x) s y s The points are superimposed to obtain the contour point set of the wafer notch in the processed measurement image.
[0098] Then, with A 5×5 contour point set matrix M is obtained by translating around the center (taking a maximum translation of 2 pixels in the x-direction and a maximum translation of 2 pixels in the y-direction as an example). con The contour point set matrix M is calculated using the above formula (6). con The score of all contour point sets in the dataset.
[0099] Finally, the set of contour points corresponding to the maximum value in the score is selected as the final contour line of the wafer notch.
[0100] In summary, the wafer notch detection method provided in this disclosure can solve the problem of difficulty in wafer notch shape detection caused by blurred, broken, or partially missing edge lines of wafer notches due to etched patterns or out-of-focus image capture near the wafer notch. Even under complex working conditions or poor wafer notch imaging quality, the solution of this disclosure can still complete wafer notch detection, and can extract the wafer notch contour line with high precision to accurately determine the location of the wafer notch, thus having better universality and robustness.
[0101] At least one embodiment of this disclosure also provides a wafer notch detection device, which includes a processor and a memory. The memory stores computer-executable instructions, which, when executed by the processor, can implement the wafer notch detection method provided in at least one embodiment of this disclosure.
[0102] Figure 9This is a schematic block diagram of a wafer notch detection device 900 provided for some embodiments of this disclosure. Figure 9 As shown, the wafer notch detection device 900 includes a processor 910 and a memory 920. The memory 920 stores computer-executable instructions (e.g., one or more computer program modules). The processor 910 executes the computer-executable instructions, which, when run by the processor 910, can perform one or more steps in the wafer notch detection method described above. The memory 920 and the processor 910 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).
[0103] For example, processor 910 may be a central processing unit (CPU), a graphics processing unit (GPU), or other form of processing unit with data processing and / or program execution capabilities. For example, the central processing unit (CPU) may be an x86 or ARM architecture. Processor 910 may be a general-purpose processor or a special-purpose processor, capable of controlling other components in wafer notch detection device 900 to perform desired functions.
[0104] For example, memory 920 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and processor 910 may run one or more computer program modules to implement various functions of wafer notch detection device 900. Various application programs and various data, as well as various data used and / or generated by the application programs, may also be stored in the computer-readable storage medium.
[0105] It should be noted that, in the embodiments of this disclosure, the specific functions and technical effects of the wafer notch detection device 900 can be referred to the description of the wafer notch detection method above, and will not be repeated here.
[0106] Figure 10 This is a schematic block diagram of an electronic device provided for some embodiments of this disclosure. The electronic device 1000 is, for example, suitable for implementing the wafer notch detection method provided in the embodiments of this disclosure. The electronic device 1000 may be a terminal device or a computer system, etc. It should be noted that... Figure 10The illustrated electronic device 1000 is merely an example and does not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.
[0107] like Figure 10 As shown, the electronic device 1000 may include a processing device (e.g., a central processing unit, a graphics processor, etc.) 1010, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1020 or a program loaded from a storage device 1080 into a random access memory (RAM) 1030. The RAM 1030 also stores various programs and data required for the operation of the electronic device 1000. The processing device 1010, ROM 1020, and RAM 1030 are interconnected via a bus 1040. An input / output (I / O) interface 1050 is also connected to the bus 1040.
[0108] Typically, the following devices can be connected to the I / O interface 1050: input devices 1060 including, for example, a touchscreen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 1070 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1080 including, for example, magnetic tape, hard disk, etc.; and communication devices 1090. Communication device 1090 allows electronic device 1000 to communicate wirelessly or wiredly with other electronic devices to exchange data. Although Figure 10 An electronic device 1000 with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown, and the electronic device 1000 may alternatively implement or have more or fewer devices.
[0109] For example, according to embodiments of this disclosure, the wafer notch detection method described above can be implemented as a computer software program. For instance, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program including program code for performing the wafer notch detection method described above. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 1090, or installed from a storage device 1080, or installed from a ROM 1020. When the computer program is executed by the processing device 1010, the functions defined in the wafer notch detection method provided by embodiments of this disclosure can be implemented.
[0110] The following points need to be explained:
[0111] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.
[0112] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.
[0113] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.
Claims
1. A wafer notch detection method, characterized in that, include: Prepare a template image of the wafer notch, and extract the contour point set of the wafer notch from the template image; Acquire a measurement image of the wafer notch, preprocess the measurement image to obtain a processed measurement image, including: Denoising is performed to obtain the first processed image; Analyze the pixel value distribution of the first processed image, wherein the pixel value distribution is the percentage of the number of pixels corresponding to each pixel value in the first processed image; Based on the pixel value distribution of the first processed image, a first pixel threshold and a second pixel threshold of the first processed image are obtained, and the pixel values of all pixels in the first processed image are reassigned based on the first pixel threshold and the second pixel threshold to increase the contrast between the wafer portion and the non-wafer portion in the measurement image, thereby obtaining the processed measurement image. The first pixel threshold corresponds to the pixel value of the non-wafer portion in the first processed image, and the second pixel threshold corresponds to the pixel value of the wafer portion in the first processed image. Image alignment is performed on the template image and the processed measurement image to obtain the offset vector of the processed measurement image relative to the template image; and The final wafer notch contour is obtained based on the offset vector.
2. The wafer notch detection method according to claim 1, characterized in that, The first pixel threshold satisfies: w is the scaling factor, k1 is the threshold value of the first pixel, and k p1 This refers to the pixel value with the highest proportion corresponding to the non-wafer portion in the first processed image. This represents the percentage of pixels with a pixel value of k1. The pixel value is k p1 The percentage of pixels; The second pixel threshold satisfies: w is the scaling factor, k2 is the second pixel threshold, and k p2 This refers to the pixel value with the highest proportion corresponding to the wafer portion in the first processed image. This represents the percentage of pixels with a pixel value of k2. The pixel value is k p2 The percentage of pixels; The pixel values of all pixels in the first processed image are reassigned based on the first pixel threshold and the second pixel threshold, including: The pixel values of the processed measurement image are obtained by adjusting the pixel values of the first processed image according to the following formula. .
3. The wafer notch detection method according to claim 1, characterized in that, Image alignment of the template image and the processed measurement image includes: Fourier transforming the template image and the processed measurement image to obtain a frequency domain representation F of the template image R and a frequency domain representation F of the processed measurement image T ; computing a cross-correlation coefficient of the frequency domain representation F R and the frequency domain representation F T , resulting in a cross-correlation coefficient matrix; and The maximum value is searched in the cross-correlation coefficient matrix, and the coordinates of the maximum value in the cross-correlation coefficient matrix are used as the offset vector of the processed measurement image relative to the template image.
4. The wafer notch detection method according to claim 1, characterized in that, The final set of wafer notch contour points is obtained based on the offset vector, including: The wafer notch contour point set in the template image is translated based on the offset vector to obtain the wafer notch contour point set in the processed measurement image. The final wafer notch contour line is determined based on the wafer notch contour point set in the processed measurement image.
5. The wafer notch detection method according to claim 4, characterized in that, The final wafer notch contour line is obtained based on the offset vector, and further includes: After obtaining the contour point set of the wafer notch in the processed measurement image, the contour point set of the wafer notch in the processed measurement image is adjusted to determine the final contour line of the wafer notch.
6. The wafer notch detection method according to claim 5, characterized in that, Adjusting the contour point set of the wafer notch in the processed measurement image includes: Each point in the wafer notch contour point set in the processed measurement image is used as the center to translate to obtain an m×n contour point set matrix, where m and n are both integers greater than 1; Calculate the score for all contour point sets in the contour point set matrix; and The final wafer notch contour is determined based on the set of contour points corresponding to the maximum value in the score.
7. The wafer notch detection method according to claim 6, characterized in that, Calculate the score for all contour point sets in the contour point set matrix, including: The score of a contour point set is the sum of the pixel value differences between two adjacent pixels in a direction perpendicular to the contour line direction corresponding to that contour point set.
8. A wafer notch detection device, characterized in that, include: processor; A memory in which executable instructions of the processor are stored; The processor is configured to perform the steps of the wafer notch detection method according to any one of claims 1 to 7 by executing the executable instructions.