Mram chip memory array

Abstract

The application provides an MRAM chip memory array, comprising: a plurality of memory bits arranged in an array form, each memory bit comprising an access transistor, a magnetic tunnel junction, a top interconnection structure and a bottom interconnection structure, the magnetic tunnel junction being connected with a corresponding bit line through the top interconnection structure, and the magnetic tunnel junction being connected with the access transistor through the bottom interconnection structure; wherein in the plurality of memory bits connected with the same bit line, each memory bit has different top interconnection structures and / or different bottom interconnection structures to introduce different compensation resistances from the top and / or bottom of each magnetic tunnel junction. By introducing the compensation resistances, the application can stabilize the voltage division across the magnetic tunnel junction.

Description

Technical Field

[0001] This invention relates to the field of magnetic random access memory (MRAM) technology, and more particularly to an MRAM chip storage array. Background Technology

[0002] Magnetic random access memory (MRAM) features fast read / write speeds, low power consumption, high integration density, high write / erase cycles, and the ability to be integrated with CMOS technology, making it a highly promising new type of memory.

[0003] MRAM chip memory cells consist of a magnetic tunnel junction (MTJ) and a front-end CMOS device, also known as a bit. An MRAM chip includes an array region and a logic region. The MTJ array region is integrated into the metal lines of the CMOS back-end process. The array consists of a bit matrix with several rows and columns. The number of erase / write cycles of an MTJ is related to the voltage applied across it; the higher the voltage, the lower the number of erase / write cycles. The MTJ is connected to metal bit lines.

[0004] Because the metal bit lines have inherent resistance, the longer the metal line, the greater the resistance. Furthermore, for a single bit, the metal line is connected in series with the MTJ and CMOS, and this resistance is introduced into the write circuit. Therefore, at different positions in the array, due to the varying resistances of the different metal lines, the voltage received by the MTJ at different positions is different when the power supply voltage is constant, affecting the number of erase / write cycles for each bit. Actual testing revealed that due to the different line resistances, the number of erase / write cycles differs significantly between bits near and far from the power supply due to different voltage divisions. Bits near the power supply account for approximately 50% of the total array failures. Therefore, it is necessary to improve the array structure to increase the number of erase / write cycles for magnetic random access memory (MRRAM) chips. Summary of the Invention

[0005] To address the aforementioned issues, this invention provides an MRAM chip storage array that can stabilize the voltage division across the magnetic tunnel junction and improve the erase / write cycles of the magnetic random access memory chip.

[0006] This invention provides an MRAM chip memory array, comprising:

[0007] Multiple memory bits are arranged in an array. Each memory bit includes an access transistor, a magnetic tunnel junction, a top interconnect structure, and a bottom interconnect structure. The magnetic tunnel junction is connected to a corresponding bit line through the top interconnect structure, and the magnetic tunnel junction is connected to the access transistor through the bottom interconnect structure.

[0008] In this context, among multiple memory bits connected to the same bit line, each memory bit has a different top interconnect structure and / or a different bottom interconnect structure, so as to introduce different compensation resistors from the top and / or bottom of each magnetic tunnel junction.

[0009] Optionally, the compensation resistor introduced into each memory bit is equal to or nearly equal to the sum of the parasitic resistance of the bit line between each memory bit and the corresponding bit line power supply terminal.

[0010] Optionally, the top interconnect structure includes a top electrode and a corresponding top electrode via, and each memory bit connected to the same bit line has a different top interconnect structure, including:

[0011] Each memory bit's top electrode via has a different offset distance relative to its corresponding magnetic tunnel junction. The closer the memory bit is to the power supply terminal of the bit line, the greater the offset distance and the greater the introduced compensation resistance.

[0012] Optionally, for a storage bit, if the introduced compensation resistor still cannot achieve voltage equalization when the offset distance of the top electrode via relative to the magnetic tunnel junction reaches the maximum length of the top electrode, the thickness and width of the top electrode are adjusted to introduce a larger compensation resistor.

[0013] Optionally, the thickness of the top electrode of each storage bit is between 100 and 500 angstroms.

[0014] Optionally, the bottom interconnect structure includes a bottom electrode and a corresponding bottom electrode via, and each memory bit connected to the same bit line has a different bottom interconnect structure, including:

[0015] Each storage bit has a different offset distance from its bottom electrode via relative to its corresponding magnetic tunnel junction. The closer the storage bit is to the power supply terminal of the bit line, the greater the offset distance and the greater the introduced compensation resistance.

[0016] Optionally, for a storage bit, if the introduced compensation resistor still cannot achieve voltage equalization when the offset distance of the bottom electrode via relative to the magnetic tunnel junction reaches the maximum length of the bottom electrode, the thickness and width of the bottom electrode are adjusted to introduce a larger compensation resistor.

[0017] Optionally, the thickness of the bottom electrode of each memory bit is between 100 and 500 angstroms.

[0018] Optionally, the introduced compensation resistor is between 100 and 1000 ohms.

[0019] Optionally, the top electrode and the bottom electrode are single-layer structures formed of one of Ta, TaN, Ti, and TiN materials, or multilayer structures formed of multiple of Ta, TaN, Ti, and TiN materials.

[0020] Optionally, along the bit line direction, the MRAM chip memory array is divided into N sub-arrays, and multiple memory bits in the same sub-array have the same top interconnect structure and bottom interconnect structure.

[0021] The MRAM chip memory array provided by this invention improves the top / bottom interconnect structure of the magnetic tunnel junction by introducing compensation resistors at the top and / or bottom of the magnetic tunnel junction. This reduces the voltage difference across the array's magnetic tunnel junction caused by the parasitic resistance of the metal bit lines. This array structure can stabilize the voltage division across the magnetic tunnel junction, improving the erase / write cycles of the magnetic random access memory chip. Furthermore, this invention requires no additional auxiliary circuitry; with a fixed structure, the compensation resistors of the bits can be adjusted through the fabrication process, offering flexibility and variability. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of an MRAM chip storage array according to an embodiment of the present invention;

[0023] Figure 2 for Figure 1 The equivalent circuit diagram of the array structure shown is shown.

[0024] Figure 3 This is a schematic diagram of the structure of an MRAM chip storage array according to an embodiment of the present invention;

[0025] Figure 4 for Figure 3 The equivalent circuit diagram of the array structure shown is shown.

[0026] Figure 5 This is a schematic diagram of the structure of an MRAM chip storage array according to an embodiment of the present invention;

[0027] Figure 6 for Figure 5 The equivalent circuit diagram of the array structure shown is shown.

[0028] Figure 7 This is a schematic diagram of the structure of an MRAM chip storage array according to an embodiment of the present invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0031] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0032] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0033] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0034] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0035] Example 1

[0036] This invention provides an MRAM chip memory array, which includes multiple memory bits arranged in an array. Each memory bit includes an access transistor, a magnetic tunnel junction (MTJ), a top interconnect structure, and a bottom interconnect structure. The access transistor includes a gate, a source, and a drain. The gate is used to connect to a word line, the source is used to connect to a source line, and the drain is used to connect to the magnetic tunnel junction. The top interconnect structure includes a top electrode TE and a corresponding top electrode via TV. The magnetic tunnel junction MTJ is connected to the bit line BL through the top interconnect structure. The bottom interconnect structure includes a bottom electrode BE and a corresponding bottom electrode via BV. The magnetic tunnel junction MTJ is connected to the drain of the access transistor through the bottom interconnect structure.

[0037] In this embodiment, among the multiple memory bits connected to the same bit line, each memory bit has a different top interconnect structure to introduce different compensation resistors from the top of each magnetic tunnel junction. The compensation resistor introduced by each memory bit is equal to or nearly equal to the sum of the bit line parasitic resistance between each memory bit and the corresponding bit line power supply terminal.

[0038] Figure 1 A schematic diagram of a structure of multiple storage bits connected to the same bit line based on an embodiment of the present invention is shown. For example... Figure 1 As shown, a bit line BL connects z+1 memory bits. Each memory bit includes an access transistor and a magnetic tunnel junction. The gates of the z+1 access transistors are connected to different word lines WL0, ..., WL n , ..., WL x , ..., WL z The sources of z+1 access transistors are connected to the source line SL, and the drains of z+1 access transistors are connected to the corresponding magnetic tunnel junctions. These z+1 magnetic tunnel junctions are denoted as MTJ0, ..., MTJ0. n , ..., MTJ x , ..., MTJ z The z+1 storage bits have different top interconnect structures, with different compensation resistors introduced from the top of the MTJ. As one implementation, in... Figure 1 In the structure shown, the top electrode vias TV of the z+1 memory bits have different offset distances relative to their respective magnetic tunnel junctions. The closer the memory bit is to the power supply terminal LDO, the larger the offset distance. For example, MTJ0 is closest to the LDO, therefore MTJ0 has the largest offset distance L0. z The one furthest from the LDO is the MTJ. z The offset distance L z Minimum. The following relationship exists: L0 > L. n >L x >L zThis is because, along the BL direction, the compensation resistance varies with the parasitic resistance of the metal. The farther the storage bit is from the bit line power supply terminal, the larger the bit line parasitic resistance, resulting in a smaller offset distance and a smaller introduced compensation resistance. Conversely, the closer the storage bit is to the bit line power supply terminal, the smaller the bit line parasitic resistance, resulting in a larger offset distance and a larger introduced compensation resistance. Generally, the introduced compensation resistance ranges from 100 to 1000 ohms.

[0039] In this embodiment, the bottom interconnect structure of each MTJ can be the same, similar to the prior art, therefore in Figure 1 The structure of the bottom electrode BE is not shown in the figure.

[0040] It should also be noted that for the same memory array, the thickness and width of the top electrode of each memory bit are usually the same. However, if the length of the top electrode is designed to be relatively small, for memory bits close to the bit line power supply terminal, if the offset distance of the top electrode via relative to the magnetic tunnel junction reaches the maximum length of the top electrode, the introduced compensation resistor still cannot achieve voltage equalization. In this case, the thickness and width of the bottom electrode of the memory bit can be adjusted to introduce a larger compensation resistor. The thickness of the top electrode of each memory bit is between 100 and 500 angstroms. The top and bottom electrodes are single-layer structures formed of one of the materials Ta, TaN, Ti, and TiN, or multi-layer structures formed of multiple materials Ta, TaN, Ti, and TiN.

[0041] The present invention provides an MRAM chip memory array in which each memory bit connected to the same bit line has a different top interconnect structure to introduce different compensation resistors from the top of each magnetic tunnel junction. The compensation resistor introduced by each memory bit is equal to or nearly equal to the sum of the bit line parasitic resistance between each memory bit and the corresponding bit line power supply terminal.

[0042] After introducing a compensation resistor at the top of the MTJ, the equivalent circuit diagram for multiple storage bits connected to the same bit line can be found by referring to [reference needed]. Figure 2 .like Figure 2 As shown, the compensation resistor R is introduced from the top of MTJ along the BL direction. The compensation resistance varies with the parasitic resistance of the metal. The larger the parasitic resistance, the smaller the compensation resistance.

[0043] Example 2

[0044] This invention provides an MRAM chip memory array, which includes multiple memory bits arranged in an array. Each memory bit includes an access transistor, a magnetic tunnel junction (MTJ), a top interconnect structure, and a bottom interconnect structure. The access transistor includes a gate, a source, and a drain. The gate is used to connect to a word line, the source is used to connect to a source line, and the drain is used to connect to the magnetic tunnel junction. The top interconnect structure includes a top electrode TE and a corresponding top electrode via TV. The magnetic tunnel junction MTJ is connected to the bit line BL through the top interconnect structure. The bottom interconnect structure includes a bottom electrode BE and a corresponding bottom electrode via BV. The magnetic tunnel junction MTJ is connected to the drain of the access transistor through the bottom interconnect structure.

[0045] In this embodiment, among the multiple memory bits connected to the same bit line, each memory bit has a different bottom interconnect structure to introduce different compensation resistors from the bottom of each magnetic tunnel junction. The compensation resistor introduced by each memory bit is equal to or nearly equal to the sum of the bit line parasitic resistance between each memory bit and the corresponding bit line power supply terminal.

[0046] Figure 3 A schematic diagram of a structure of multiple storage bits connected to the same bit line based on an embodiment of the present invention is shown. For example... Figure 1 As shown, a bit line BL connects z+1 memory bits. Each memory bit includes an access transistor and a magnetic tunnel junction. The gates of the z+1 access transistors are connected to different word lines WL0, ..., WL n , ..., WL x , ..., WL z The sources of z+1 access transistors are connected to the source line SL, and the drains of z+1 access transistors are connected to the corresponding magnetic tunnel junctions. These z+1 magnetic tunnel junctions are denoted as MTJ0, ..., MTJ0. n , ..., MTJ x , ..., MTJ z The z+1 memory bits have different bottom interconnect structures, with different compensation resistors introduced from the bottom of the MTJ. As one implementation, in... Figure 3 In the structure shown, the bottom electrode vias BV of the z+1 storage bits have different offset distances relative to their respective magnetic tunnel junctions. The closer the storage bit is to the bit-to-power line terminal LDO, the larger the offset distance. For example, MTJ0 is closest to the LDO, therefore MTJ0 has the largest offset distance L0. z The one furthest from the LDO is the MTJ. z The offset distance L z Minimum. The following relationship exists: L0 > L. n >L x >L zThis is because along the BL direction, the compensation resistance varies with the parasitic resistance of the metal. The farther the storage bit is from the bit line power supply terminal, the larger the bit line parasitic resistance, and therefore the smaller the offset distance and the smaller the introduced compensation resistance. Generally, the introduced compensation resistance is between 100 and 1000 ohms.

[0047] In this embodiment, the top interconnect structure of each MTJ can be the same, similar to the prior art, therefore in Figure 3 The structure of the top electrode TE is not shown in the figure.

[0048] It should also be noted that for the same memory array, the thickness and width of the bottom electrode of each memory bit are usually the same. However, if the length of the bottom electrode is designed to be relatively small, for memory bits that are close to the bit line power supply terminal, if the offset distance of the bottom electrode via relative to the magnetic tunnel junction reaches the maximum length of the bottom electrode, the introduced compensation resistor still cannot achieve voltage equalization. In this case, the thickness and width of the bottom electrode of the memory bit can be adjusted to introduce a larger compensation resistor. The thickness of the bottom electrode of each memory bit is between 100 and 500 angstroms. The top and bottom electrodes are single-layer structures formed of one of the materials Ta, TaN, Ti, and TiN, or multilayer structures formed of multiple materials Ta, TaN, Ti, and TiN.

[0049] The present invention provides an MRAM chip memory array in which each memory bit has a different bottom interconnect structure in multiple memory bits connected to the same bit line, so as to introduce different compensation resistors from the bottom of each magnetic tunnel junction. The compensation resistor introduced by each memory bit is equal to or nearly equal to the sum of the bit line parasitic resistance between each memory bit and the power supply terminal of the corresponding bit line.

[0050] After introducing a compensation resistor at the bottom of the MTJ, the equivalent circuit diagram for multiple storage bits connected to the same bit line can be found by referring to [reference needed]. Figure 4 .like Figure 4 As shown, the compensation resistor R is introduced from the bottom of MTJ along the BL direction. The compensation resistance varies with the parasitic resistance of the metal. The larger the parasitic resistance, the smaller the compensation resistance.

[0051] Example 3

[0052] This invention provides an MRAM chip memory array, which includes multiple memory bits arranged in an array. Each memory bit includes an access transistor, a magnetic tunnel junction (MTJ), a top interconnect structure, and a bottom interconnect structure. The access transistor includes a gate, a source, and a drain. The gate is used to connect to a word line, the source is used to connect to a source line, and the drain is used to connect to the magnetic tunnel junction. The top interconnect structure includes a top electrode TE and a corresponding top electrode via TV. The magnetic tunnel junction MTJ is connected to the bit line BL through the top interconnect structure. The bottom interconnect structure includes a bottom electrode BE and a corresponding bottom electrode via BV. The magnetic tunnel junction MTJ is connected to the drain of the access transistor through the bottom interconnect structure.

[0053] In this embodiment, among the multiple memory bits connected to the same bit line, each memory bit has a different top interconnect structure and a different bottom interconnect structure, so as to introduce different compensation resistors from the top and bottom of each magnetic tunnel junction simultaneously. The compensation resistor introduced by each memory bit is equal to or nearly equal to the sum of the bit line parasitic resistance between each memory bit and the corresponding bit line power supply terminal.

[0054] Figure 5 A schematic diagram of a structure of multiple storage bits connected to the same bit line based on an embodiment of the present invention is shown. For example... Figure 5 As shown, a bit line BL connects z+1 memory bits. Each memory bit includes an access transistor and a magnetic tunnel junction. The gates of the z+1 access transistors are connected to different word lines WL0, ..., WL n , ..., WL x , ..., WL z The sources of z+1 access transistors are connected to the source line SL, and the drains of z+1 access transistors are connected to the corresponding magnetic tunnel junctions. These z+1 magnetic tunnel junctions are denoted as MTJ0, ..., MTJ0. n , ..., MTJ x , ..., MTJ z The z+1 memory bits have different top interconnect structures and different bottom interconnect structures, with compensation resistors introduced simultaneously from both the top and bottom of the MTJ. As one implementation, in... Figure 5 In the structure shown, the top electrode vias TV of the z+1 storage bits have different offset distances relative to their respective magnetic tunnel junctions. Simultaneously, the bottom electrode vias BV of the z+1 storage bits also have different offset distances relative to their respective magnetic tunnel junctions.

[0055] In this case, the closer the storage bit is to the LDO (Lower Disk Controller) power supply terminal, the greater the offset distance. For example, if MTJ0 is closest to the LDO, then MTJ0 has the largest offset distance L0. z The one furthest from the LDO is the MTJ. zThe offset distance L z Minimum. The following relationship exists: L0 > L. n >L x >L z This is because along the BL direction, the compensation resistance varies with the parasitic resistance of the metal. The farther the storage bit is from the bit line power supply terminal, the larger the bit line parasitic resistance, and therefore the smaller the offset distance and the smaller the introduced compensation resistance. Generally, the introduced compensation resistance is between 100 and 1000 ohms.

[0056] Additionally, referring to the above embodiments, when adjusting the offset distance cannot meet the compensation requirements, the thickness and width of the top and bottom electrodes of the memory bit can also be adjusted, which can also introduce a larger compensation resistance from the top and bottom of the magnetic tunnel junction. The thickness of the top and bottom electrodes of each memory bit is between 100 and 500 angstroms. The top and bottom electrodes are a single-layer structure formed of one of Ta, TaN, Ti, and TiN materials, or a stacked structure formed of multiple materials of Ta, TaN, Ti, and TiN.

[0057] The present invention provides an MRAM chip memory array in which each memory bit connected to the same bit line has a different top interconnect structure and a different bottom interconnect structure, so as to introduce different compensation resistors from the top and bottom of each magnetic tunnel junction. The compensation resistor introduced by each memory bit is equal to or nearly equal to the sum of the bit line parasitic resistance between each memory bit and the corresponding bit line power supply terminal.

[0058] With compensation resistors introduced at both the top and bottom of the MTJ, the equivalent circuit diagram for multiple storage bits connected to the same bit line can be found by referring to [reference needed]. Figure 6 .like Figure 6 As shown, the compensation resistor R is introduced simultaneously from the top and bottom of the MTJ. Along the BL direction, the compensation resistor varies with the parasitic resistance of the metal. The larger the parasitic resistance, the smaller the compensation resistor.

[0059] It should be noted that the compensation resistance of the bottom / top electrode is determined by the thickness of the bottom / top electrode material and the effective number of blocks of the offset distance. The sheet resistance of the bottom / top electrode material is 10 to 400 ohm / sq.

[0060] The three embodiments given above illustrate three ways to introduce compensation resistors into memory bits: introducing compensation resistors from the top of the MTJ, introducing compensation resistors from the bottom of the MTJ, and introducing compensation resistors from both the top and bottom of the MTJ simultaneously.

[0061] The above embodiments primarily illustrate the structure of multiple storage bits connected to the same bit line. When extended to the entire array, refer to... Figure 7 , Figure 7The diagram shows multiple bit lines BL0, BLn, and BLx. Along the bit line direction, the array is divided into N subarrays, with the number of subarrays ranging from 1 to N, where N is the number of memory bits along the bit line direction. Multiple memory bits within the same subarray have the same top and bottom interconnect structures. Memory bits in different subarrays have different top and bottom interconnect structures.

[0062] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An MRAM chip storage array, characterized in that, include: Multiple memory bits are arranged in an array. Each memory bit includes an access transistor, a magnetic tunnel junction, a top interconnect structure, and a bottom interconnect structure. The magnetic tunnel junction is connected to a corresponding bit line through the top interconnect structure, and the magnetic tunnel junction is connected to the access transistor through the bottom interconnect structure. Among the multiple memory bits connected to the same bit line, each memory bit has a different top interconnect structure and / or a different bottom interconnect structure to introduce different compensation resistors from the top and / or bottom of each magnetic tunnel junction. The compensation resistor introduced by each memory bit is equal to or nearly equal to the sum of the bit line parasitic resistance between each memory bit and the corresponding bit line power supply terminal. Each memory bit connected to the same bit line has a different top interconnect structure, including the following implementation: the top interconnect structure includes a top electrode and a corresponding top electrode via. The top electrode via of each memory bit has a different offset distance relative to its corresponding magnetic tunnel junction. The closer the memory bit is to the power supply terminal of the bit line, the larger the offset distance and the larger the introduced compensation resistance. Each memory bit connected to the same bit line has a different bottom interconnect structure, including the following implementation: the bottom interconnect structure includes a bottom electrode and a corresponding bottom electrode via. The bottom electrode via of each memory bit has a different offset distance relative to its corresponding magnetic tunnel junction. The closer the memory bit is to the power supply terminal of the bit line, the larger the offset distance and the larger the introduced compensation resistor.

2. The MRAM chip storage array according to claim 1, characterized in that, For a storage bit, if the offset distance of the top electrode via relative to the magnetic tunnel junction reaches the maximum length of the top electrode, and the introduced compensation resistor still cannot achieve voltage equalization, then the thickness and width of the top electrode are adjusted to introduce a larger compensation resistor.

3. The MRAM chip storage array according to claim 1, characterized in that, The thickness of the top electrode of each memory bit is between 100 and 500 angstroms.

4. The MRAM chip storage array according to claim 1, characterized in that, For a storage bit, if the offset distance of the bottom electrode via relative to the magnetic tunnel junction reaches the maximum length of the bottom electrode, and the introduced compensation resistor still cannot achieve voltage equalization, then the thickness and width of the bottom electrode are adjusted to introduce a larger compensation resistor.

5. The MRAM chip storage array according to claim 1, characterized in that, The thickness of the bottom electrode of each memory bit is between 100 and 500 angstroms.

6. The MRAM chip storage array according to claim 1, characterized in that, The introduced compensation resistor has a value between 100 and 1000 ohms.

7. The MRAM chip storage array according to claim 1, characterized in that, Along the bit line direction, the MRAM chip memory array is divided into N sub-arrays, and multiple memory bits in the same sub-array have the same top interconnect structure and bottom interconnect structure.

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