Method of processing dynamic random access memory

Abstract

Methods of forming DRAM bit lines to improve line edge roughness (LER) and reduce resistance are described. The methods include the steps of implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size, the second grain size being smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and the amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.

Description

Technical Field

[0001] Several embodiments of the present invention relate to the field of electronic device manufacturing. More specifically, several embodiments relate to methods for a dynamic random access memory (DRAM) bit line stacking process. Background Technology

[0002] Integrated circuits have evolved into complex devices that can include millions of transistors, capacitors, and resistors on a single chip. In the development of integrated circuits, functional density (i.e., the number of interconnects per chip region) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased.

[0003] Reducing the size of integrated circuits (ICs) leads to improved performance, increased capacity, and / or lower costs. Each reduction in size requires more sophisticated techniques to form the IC. For example, smaller transistor sizes allow for the integration of more memory or logic devices onto a single chip, facilitating the manufacture of higher-capacity products. However, the perpetual pursuit of capacity is not without its problems. The need to optimize the performance of individual devices becomes increasingly important.

[0004] Non-volatile memory is a type of integrated circuit in which memory cells or elements do not lose their state after the power supply to the device is turned off. Early computer memories made of ferrite rings that could be magnetized in two directions were non-volatile. As semiconductor technology advanced to higher levels of miniaturization, ferrite devices were abandoned due to the more common volatile memories such as DRAM (Dynamic Random Access Memory) and SRAM (Static RAM). As used herein, the term "Dynamic Random Access Memory" or "DRAM" refers to a memory cell that stores data bits by storing packets of charge (i.e., binary 1) or no charge (i.e., binary 0) on a capacitor. The charge is gated onto the capacitor by an access transistor and detected by turning on the same transistor and observing the voltage disturbance caused by dumping the charge packet onto the interconnect line on the transistor output. Thus, a single DRAM cell is made of one transistor and one capacitor. Arrays of DRAM cells form DRAM devices. Rows on the access transistors are linked by word lines, and transistor inputs / outputs are linked by bit lines. Historically, DRAM capacitors have evolved from planar polysilicon-oxide-slab plate capacitors to 3D structures, which have been divided into "stacked" capacitors (both plates are located on top of the substrate) and "trench" capacitors (using etched cavities in the substrate as common plates). In such DRAM devices, it is difficult to form DRAM bit lines that simultaneously have low resistance and good line edge roughness.

[0005] Therefore, there is a need for a method to manufacture DRAM devices with bit lines that simultaneously have low resistance and good line edge roughness. Summary of the Invention

[0006] One or more embodiments of this disclosure relate to a method for forming DRAM bit lines, the method comprising the steps of: implanting inert substances into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size; depositing a film stack on the amorphized bit line metal layer; etching the film stack and the amorphized bit line metal layer to form a patterned film stack on a substrate; and thermally annealing the patterned film stack on the substrate.

[0007] One or more embodiments of this disclosure relate to a clustering tool for performing dynamic random access memory (DRAM) bit line stacking processes. In one embodiment, the clustering tool includes: a central transport station configured to receive a substrate having polysilicon plugs formed on the substrate, and the central transport station configured to transport the substrate to and from a plurality of process chambers, each of the plurality of process chambers being independently connected to the central transport station to perform one of a plurality of DRAM bit line processes on the substrate, the plurality of process chambers including: a pre-cleaning chamber configured to remove native oxide from the surface of the substrate; a barrier layer deposition chamber configured to deposit a barrier layer on the surface of the substrate; a bit line metal deposition chamber configured to deposit a bit line metal layer on the surface of the substrate; and a hard mold deposition chamber configured to deposit a hard mold layer on the surface of the substrate.

[0008] One or more embodiments of this disclosure relate to a non-transitory computer-readable medium comprising instructions that, when executed by a controller of a process chamber, cause the process chamber to perform the following operations: controlling the injection of an inert material into a bit line metal layer having a first grain size on a substrate to form an amorphous bit line metal layer having a second grain size, wherein the second grain size is smaller than the first grain size; controlling the deposition of a film stack on the amorphous bit line metal layer; receiving data for a third structure to control the etching of the film stack and the amorphous bit line metal layer to form a patterned film stack on a substrate; and controlling the thermal annealing of the patterned film stack on the substrate. Attached Figure Description

[0009] Therefore, in order to understand in detail the above-described features of this disclosure, a more specific description of the disclosure briefly summarized above can be obtained by referring to various embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only show a few typical embodiments of this disclosure and should not be considered as limiting the scope of this disclosure, as this disclosure may allow for many other equivalent embodiments.

[0010] Figure 1 A flowchart depicting a method according to several embodiments described herein;

[0011] Figure 2 Depicting an electronic device according to one or more embodiments;

[0012] Figure 3 Depicting an electronic device according to one or more embodiments;

[0013] Figure 4A Depicting an electronic device according to one or more embodiments;

[0014] Figure 4BDepicting an electronic device according to one or more embodiments;

[0015] Figure 4C Depicting an electronic device according to one or more embodiments; and

[0016] Figure 5 A block diagram depicting a clustering tool system according to one or more embodiments of this disclosure. Detailed Implementation

[0017] Before describing several exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the details of the structures or processing steps set forth in the following description. This disclosure can have many other embodiments and can be practiced or performed in various ways.

[0018] As used in this specification and the appended claims, the term "substrate" refers to a surface, or a portion of a surface, on which the processing is performed. Those skilled in the art to which this application pertains will also understand that, unless the context clearly indicates otherwise, reference to substrate may refer only to a portion of a substrate. Furthermore, reference to deposition on a substrate may refer to both a bare substrate and a substrate having one or more films or structures deposited or formed on it.

[0019] As used herein, "substrate" refers to any substrate or material surface formed on a substrate, on which a film treatment is performed during a manufacturing process. For example, depending on the application, substrate surfaces that can be treated include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials (such as metals, metal nitrides, metal alloys, and other conductive materials). Substrates may include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes such as polishing, etching, reduction, oxidation, hydroxylation, annealing, UV curing, electron beam curing, and / or baking of the substrate surface. In addition to performing film treatments directly on the surface of the substrate itself, any of the film treatment steps disclosed herein (disclosed in more detail below) may also be performed on an underlayer formed on the substrate, and the term "substrate surface" is intended to include such an underlayer as referred to herein. Therefore, for example, when a film / layer or part of a film / layer has been deposited onto the substrate surface, the exposed surface of the newly deposited film / layer is the substrate surface.

[0020] As used in this specification and the appended claims, the terms “precursor,” “reactant,” “reactive gas,” and similar terms are used interchangeably to refer to any gaseous substance that can react with the substrate surface.

[0021] As used herein, the term "Dynamic Random Access Memory" or "DRAM" refers to a memory cell that stores data bits by storing data packets of charge (i.e., binary 1) or no charge (i.e., binary 0) on a capacitor. The charge is gated onto the capacitor by an access transistor and detected by activating the same transistor and observing the voltage disturbance generated when a charge packet is applied to the interconnect at the transistor output. Therefore, a single DRAM cell is made of one transistor and one capacitor. Arrays of DRAM cells form DRAM devices. Rows on the access transistors are linked by word lines, and transistor inputs / outputs are linked by bit lines. Historically, DRAM capacitors have evolved from planar polysilicon-oxide-slab plate capacitors to 3-D structures, which have been divided into "stacked" capacitors (both plates are located on top of a substrate) and "trench" capacitors (using etched cavities in the substrate as a common plate).

[0022] This document describes several exemplary embodiments with reference to multiple cross-sectional views, which are schematic diagrams of several exemplary embodiments (and intermediate structures). Therefore, variations in the illustrated shapes are expected, for example, due to manufacturing techniques and / or tolerances. Consequently, the exemplary embodiments should not be construed as limited to a specific shape within the areas shown herein, but may include, for example, shape deviations caused by manufacturing processes.

[0023] Several embodiments of this disclosure relate to methods for processing DRAM bit lines to advantageously improve line edge roughness (LER) and reduce resistance.

[0024] Figure 1 A flowchart depicting one or more embodiments of method 10 according to this disclosure is provided. (See also...) Figure 1 Method 10 begins at operation 20 by injecting an inert material into the line metal layer. At operation 30, a film stack is deposited. At operation 40, the film stack is etched to form a patterned film stack. At operation 50, the patterned film stack is thermally annealed.

[0025] Figures 2 to 4CA cross-sectional view of an electronic device 100 according to one or more embodiments is depicted. Referring to Figures 2 and 3, an inert material 112 is implanted into a bit line metal layer 107 having a first grain size on a substrate 102 to form an amorphous bit line metal layer 108 having a second grain size smaller than the first grain size. In one or more embodiments, the bit line metal layer 107 is deposited using any suitable technique known to those skilled in the art to which this invention pertains, and the bit line metal layer 107 is any suitable material known to those skilled in the art to which this invention pertains. In one or more embodiments, the bit line metal layer 107 comprises ruthenium and has the first grain size. In one or more embodiments, the amorphous bit line metal layer 108 comprises amorphous ruthenium and has a second grain size smaller than the first grain size.

[0026] In one or more embodiments, the first grain size, measured by atomic force microscopy (AFM), is approximately... to approximately Within a certain range. In one or more embodiments, the second grain size, measured by atomic force microscopy (AFM), is approximately... to approximately Within a certain range. In one or more embodiments, the third grain size, measured by atomic force microscopy (AFM), is approximately... to approximately Within the range.

[0027] In one or more embodiments, the inert material 112 comprises one or more of the following: argon (Ar), helium (He), neon (Ne), krypton (Kr), xenon (Xe), or radon (Rn). In one or more embodiments, the dose of the inert material 112 injected into the in-line metal layer 107 is greater than 1 x 10⁻⁶. 15 atoms / cm 2 In one or more embodiments, the inert material 112 is injected via beamline implantation or plasma implantation (PLAD).

[0028] In some embodiments, the method further includes the step of depositing a capping layer 110 on the bit line metal layer 107 prior to the injection of the inert material 112. The capping layer 110 can be deposited by any method known to those skilled in the art to which this application pertains, including, but not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). In one or more embodiments, the thickness of the capping layer is approximately... to approximately Within the scope, including approximately to approximately or about to approximately In one or more embodiments, the cover layer 110 has approximately or about or about or about or about or about or about or about or about The thickness of the capping layer 110. In one or more embodiments, the capping layer 110 comprises one or more of nitrides or oxides. In one or more embodiments, the capping layer 110 comprises one or more of silicon nitride (SiN) or silicon oxide (SiO).

[0029] In one or more embodiments, the substrate 102 has a surface comprising a first surface material 103 and a second surface material 104. In one or more embodiments, the first surface material 103 comprises an oxide. In one or more embodiments, the second surface material 104 comprises polysilicon. In one or more embodiments, the substrate 102 comprises a polysilicon plug (polysilicon plug) previously manufactured on the substrate as the second surface material 104.

[0030] In one or more embodiments, the substrate 102 includes a barrier layer 106 located on the top surface of the substrate 102. In one or more embodiments, the barrier layer includes a barrier material. In one or more embodiments, the barrier layer 106 includes one or more of the following: tantalum (Ta), titanium (Ti), tungsten (W), tantalum nitride (TaN), titanium nitride (TiN), or tungsten nitride (WN).

[0031] Reference Figure 3 A film stack 113 is deposited on an amorphous bit-line metal layer 108. In one or more embodiments, the film stack 113 comprises one or more layers selected from a nitride layer, an oxide layer, a carbon hard-mode layer, or an oxynitride layer. Figure 3 In the depicted embodiment, the film stack 113 includes a nitride layer 114, an oxide layer 116, a carbon hard mold layer 118, and an oxynitride layer 120.

[0032] Reference Figures 4A to 4C The film stack 113 and the amorphous bit line metal layer 108 are etched to form a patterned film stack on the substrate 102.

[0033] Reference Figure 4AThe substrate is etched, resulting in the etching of the film stack 113 and the amorphous bit line metal layer 108. In one or more embodiments, one or more of the barrier layer 106 or the second surface material 104 are etched. See also... Figure 4B The barrier layer 106 is etched. (See reference...) Figure 4C In one or more embodiments, the second surface material 104 is etched. Because the second grain size is small, it helps to improve etching uniformity and thus reduce the line edge roughness of the bit lines.

[0034] In one or more embodiments, a patterned film stack is then thermally annealed on the substrate. In one or more embodiments, the thermal annealing of the substrate includes exposing the substrate to a temperature ranging from about 500°C to about 900°C. In one or more embodiments, the thermal annealing of the substrate increases the grain size of the amorphous bit line metal layer 108 from a second grain size to a third grain size larger than the second grain size, and therefore, the larger grain size helps to reduce the bit line contact resistance Rc and the sheet resistance Rs. In one or more embodiments, the third grain size, measured by atomic force microscopy (AFM), is approximately... to approximately Within the range.

[0035] In one or more embodiments, devices manufactured according to the various embodiments described herein have reduced bit line edge roughness compared to devices not manufactured according to the methods described herein. Furthermore, in one or more embodiments, the bit line resistance, Rc, and Rs of devices manufactured according to the methods described herein are lower than the bit line resistance of devices not manufactured according to the methods described herein. In one or more embodiments, the bit edge roughness can be measured by metrology or SEM, and the resistances Rc and Rs can be measured by the electrical performance of a DRAM or bit line test module for the bit line resistances Rc and Rs.

[0036] According to one or more embodiments, the substrate is processed before and / or after the formation of the layer. This processing can be performed in the same chamber or in one or more separate process chambers. In some embodiments, the substrate is moved from a first chamber to a separate second chamber for further processing. The substrate can be moved directly from the first chamber to a separate process chamber, or the substrate can be moved from the first chamber to one or more transfer chambers and then to a separate process chamber. Thus, the process apparatus can include multiple chambers communicating with transfer stations. This type of apparatus may be referred to as a "clustertool" or "clustered system" and similar terms.

[0037] Reference Figure 5Additional embodiments of this disclosure relate to a processing system 900 for performing the methods described herein. Figure 5 A system 900 for processing substrates according to one or more embodiments of this disclosure is illustrated. System 900 may refer to a clustering tool. System 900 includes a central transfer station 910, in which a robotic arm 912 is located. The robotic arm 912 is illustrated as a single-blade robotic arm; however, those skilled in the art to which this disclosure pertains will recognize that other robotic arm 912 configurations may fall within the scope of this disclosure. The robotic arm 912 is configured to move one or more substrates between chambers connected to the central transfer station 910.

[0038] At least one pre-cleaning / buffer chamber 920 is connected to the central transfer station 910. The pre-cleaning / buffer chamber 920 may include one or more of a heater, a radical source, or a plasma source. The pre-cleaning / buffer chamber 920 may serve as a holding area for individual semiconductor substrates or as a holding area for chip cassettes for processing. The pre-cleaning / buffer chamber 920 may perform a pre-cleaning process, preheat substrates for processing, or simply serve as a staging area for a processing sequence. In some embodiments, two pre-cleaning / buffer chambers 920 are connected to the central transfer station 910.

[0039] exist Figure 5 In the illustrated embodiment, the pre-cleaning chamber 920 can serve as a pass-through chamber between the factory interface 905 and the central transfer station 910. The factory interface 905 may include one or more robotic arms 906 to move substrates from a cassette to the pre-cleaning / buffering chamber 920. The robotic arm 912 may then move the substrates from the pre-cleaning / buffering chamber 920 to other chambers within the system 900. In one or more embodiments, the pre-cleaning chamber 920 is configured to remove native oxides from the surface of the substrate.

[0040] The first process chamber 930 can be connected to the central transfer station 910. The first process chamber 930 can be configured as an inert material injection chamber, configured to inject one or more inert materials onto the bit line metal layer. The substrate can be moved back and forth to the process chamber 930 via a robotic arm 912 through an isolation valve 914.

[0041] Process chamber 940 may also be connected to central transfer station 910. In some embodiments, process chamber 940 includes a barrier layer deposition chamber configured to deposit a barrier layer on the surface of a substrate and in fluid communication with one or more reactive gas sources to provide a flow of reactive gas to process chamber 940 to deposit the barrier layer on the substrate. The substrate can be moved back and forth to process chamber 940 via robotic arm 912 through isolation valve 914.

[0042] Process chamber 945 may also be connected to central transfer station 910. In some embodiments, process chamber 945 is of the same type as process chamber 940 and is configured to perform the same process as process chamber 940. Such a configuration may be advantageous when the process performed in process chamber 940 takes longer than the process in process chamber 930.

[0043] In several other embodiments, the process chamber 940 includes a bit line metal deposition chamber configured to deposit a bit line metal layer on the surface of a substrate.

[0044] In some embodiments, process chambers 930, 940, 945, and 960 are configured to perform different parts of a processing method. For example, process chamber 930 may be configured to inject one or more inert substances into a bitline metal layer, process chamber 940 may be configured to deposit a bitline metal layer onto the surface of a substrate, process chamber 945 may be configured as a metering station or to perform purification of the process chamber, and process chamber 960 may be configured to perform a second purification process. Those skilled in the art will recognize that the number and arrangement of the various process chambers on the tool can be varied, and Figure 5 The embodiments shown are only one possible structure.

[0045] In some implementations, the processing system 900 includes one or more metering stations. For example, the metering station may be located within a pre-cleaning / buffer chamber 920, within a central transfer station 910, or within any separate process chamber. The metering station can be located anywhere within the system 900, a location that allows for the measurement of recess distances without exposing the substrate to an oxidizing environment.

[0046] At least one controller 950 is coupled to one or more of the central transfer station 910, pre-cleaning / buffer chamber 920, and process chambers 930, 940, 945, or 960. In some embodiments, more than one controller 950 is connected to individual chambers or stations, and a main control processor is coupled to each individual processor to control system 900. The controller 950 can be any type of general-purpose computer processor, microcontroller, microprocessor, etc., and can be used in industrial environments to control various chambers and subprocessors.

[0047] At least one controller 950 may have a processor 952, a memory 954 coupled to the processor 952, an input / output device 956 coupled to the processor 952, and support circuitry 958 for communication between different electronic components. The memory 954 may include one or more of transient temporary memory (e.g., random access memory) and non-transient memory (e.g., storage device).

[0048] The processor's memory 954 or computer-readable medium can be one or more readily available memories, such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of digital storage device, whether local or remote. Memory 954 may hold an instruction set that can be operated by processor 952 to control the parameters and components of system 900. Support circuitry 958 is coupled to processor 952 to support the processor using conventional methods. This circuitry may include, for example, cache, power supply, clock circuitry, input / output circuitry, subsystems, and similar circuitry.

[0049] Typically, the process can be stored in memory as a software routine, which, when executed by a processor, causes the process chamber to perform the process of this disclosure. The software routine can also be stored and / or executed by a remote second processor (not shown) located in processor-controlled hardware. Some or all of the methods of this disclosure can also be executed in hardware. Thus, the process can be implemented in software and executed using a computer system, implemented in hardware as, for example, an application-specific integrated circuit or other type of hardware, or as a combination of software and hardware. When executed by a processor, the software routine transforms a general-purpose computer into a dedicated computer (controller) that controls the operation of the process chamber to perform the processing.

[0050] In some embodiments, the controller 950 has one or more configurations to perform individual processes or subprocesses to perform the method. The controller 950 may be connected to and configured to operate intermediate components to perform the functions of the method. For example, the controller 950 may be connected to and configured to control one or more of a gas valve, actuator, motor, slit valve, vacuum control, etc.

[0051] The controller 950 in some embodiments has one or more structures selected from: structures that move a substrate on a robotic arm between multiple process chambers and metering stations; structures that load a substrate and / or remove a substrate from the system; structures that expose a substrate to a metal-organic precursor; structures that expose a substrate to an oxidant to react with a metal-organic precursor; structures that purify a process chamber of metal-organic precursors; structures that purify a process chamber of oxidants; and structures that repeat the cycle.

[0052] One or more embodiments relate to a clustering tool for performing dynamic random access memory (DRAM) bit line stacking processes. In one or more embodiments, the clustering tool includes: a central transport station configured to receive a substrate having polysilicon plugs formed on the substrate, and the central transport station configured to transport the substrate to and from a plurality of process chambers, each of the plurality of process chambers being independently connected to the central transport station to perform one of a plurality of DRAM bit line processes on the substrate, the plurality of process chambers including: a pre-cleaning chamber configured to remove native oxide from the surface of the substrate; an injection chamber configured to inject one or more inert materials onto a bit line metal layer; a barrier layer deposition chamber configured to deposit a barrier layer onto the surface of the substrate; a bit line metal deposition chamber configured to deposit a bit line metal layer onto the surface of the substrate; and a hard mold deposition chamber configured to deposit a hard mold layer onto the surface of the substrate. In one or more embodiments, the bit line metal layer comprises ruthenium. In one or more embodiments, the injection chamber is configured to inject an inert material into the surface of the bit line metal layer.

[0053] In one or more embodiments, the clustering tool further includes: an annealing chamber configured to perform an annealing process on a substrate; and a capping chamber configured to deposit a capping layer on the surface of the substrate. In one or more embodiments, the clustering tool further includes: a controller configured to control a plurality of process chambers.

[0054] One or more embodiments relate to a non-transitory computer-readable medium comprising instructions that, when executed by a controller of a process chamber, cause the process chamber to perform the following operations: control the injection of an inert material into a bit line metal layer having a first grain size on a substrate to form an amorphous bit line metal layer having a second grain size, wherein the second grain size is smaller than the first grain size; control the deposition of a film stack on the amorphous bit line metal layer; receive data for a third structure to control the etching of the film stack and the amorphous bit line metal layer to form a patterned film stack on a substrate; and control the thermal annealing of the patterned film stack on the substrate.

[0055] In one or more embodiments, an inert material is implanted into the bit line metal layer 107 using a bundled wire implantation process. In this embodiment, the substrate is transported out and then placed in a bundled wire implantation tool to perform bundled wire implantation, after which the substrate is transported back to the cluster system for the deposition of the remaining film stack.

[0056] Throughout this specification, references to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" mean that a specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of this disclosure. Therefore, phrases appearing in various places throughout this specification, such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment," do not necessarily refer to the same embodiment of this disclosure. Furthermore, in one or more embodiments, specific features, structures, materials, or characteristics can be combined in any manner.

[0057] Although the disclosure herein has been described with reference to several specific embodiments, those skilled in the art to which this application pertains will understand that these embodiments are merely illustrative of the principles and applications of this disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of this disclosure without departing from the spirit and scope of this disclosure. Therefore, this disclosure can include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method for forming DRAM bit lines, the method comprising the following steps: An inert material is implanted into a bit line metal layer with a first grain size on a substrate to form an amorphous bit line metal layer with a second grain size smaller than the first grain size. The film stack is deposited on the amorphous bit line metal layer; The film stack and the amorphized bit line metal layer are etched to form a patterned film stack on the substrate; and The patterned film stack on the substrate is thermally annealed to form a third grain size of the amorphous bit line metal layer, wherein the third grain size is larger than the second grain size.

2. The method of claim 1, wherein the substrate has a surface and a barrier layer, the surface comprising a first surface material and a second surface material, the barrier layer being on the surface of the substrate, the first surface material comprising an oxide, and the second surface material comprising polysilicon.

3. The method of claim 2, wherein the barrier layer comprises a barrier metal.

4. The method of claim 1, wherein the injection comprises one or more of the following: bundled wire injection of inert material or plasma injection.

5. The method of claim 4, wherein the inert material comprises one or more of the following: argon (Ar), helium (He), neon (Ne), krypton (Kr), xenon (Xe), or radon (Rn).

6. The method of claim 4, wherein the dose of the inert material implanted into the bit line metal layer is greater than 1 x 10⁻⁶. 15 atoms / cm 2 .

7. The method of claim 1, further comprising the step of: depositing a capping layer on the bit line metal layer prior to injecting the inert material.

8. The method of claim 7, wherein the covering layer has a thickness in the range of about 20 Å to about 100 Å.

9. The method of claim 7, wherein the coating layer comprises one or more of a nitride or an oxide.

10. The method of claim 1, wherein the film stack comprises one or more layers selected from nitride layers, oxide layers, carbon hardening layers, or oxynitride layers.

11. The method of claim 2, further comprising the step of: etching one or more of the barrier layer or the second surface material.

12. The method of claim 1, wherein thermal annealing of the substrate comprises the step of exposing the substrate to a temperature in the range of about 500°C to about 900°C.

13. The method of claim 1, wherein thermal annealing of the substrate increases the grain size of the amorphous bit line metal layer from the second grain size to a third grain size greater than the second grain size.

14. The method of claim 13, wherein the third grain size is in the range of about 5 Å to about 2000 Å.

15. The method of claim 1, wherein the bit line metal layer comprises ruthenium.

16. A clustering tool for performing a dynamic random access memory (DRAM) bit-line stacking process, the clustering tool comprising: A central transfer station is configured to receive a substrate having polysilicon plugs formed on the substrate, and the central transfer station is configured to transfer the substrate to and from a plurality of process chambers, each of the plurality of process chambers being independently connected to the central transfer station to perform one of a plurality of DRAM bit-line processes on the substrate, the plurality of process chambers comprising: A pre-cleaning chamber configured to remove native oxides from the surface of the substrate; A barrier layer deposition chamber configured to deposit a barrier layer on the surface of the substrate; Bit line metal deposition chamber, configured to deposit a bit line metal layer having a first grain size on the surface of the substrate; An injection chamber is configured to inject an inert material into the bit line metal layer to form an amorphous bit line metal layer with a second grain size smaller than the first grain size; A hard mold deposition chamber configured to deposit a hard mold layer on the surface of the substrate; An annealing chamber is configured to perform an annealing process on the substrate to thermally anneal the amorphized bit line metal layer on the substrate to form a third grain size of the amorphized bit line metal layer, wherein the third grain size is larger than the second grain size; and A cover chamber is configured to deposit a cover layer on the surface of the substrate.

17. The clustering tool of claim 16, wherein the plurality of process chambers further comprises: an injection chamber configured to inject an inert material into the surface of the bitline metal layer.

18. The clustering tool of claim 16, further comprising: a controller configured to control the plurality of process chambers.

19. A non-transitory computer-readable medium comprising a plurality of instructions, which, when executed by a controller of a process chamber, cause the process chamber to perform the following operations: The inert material is controlled to be injected into a bit line metal layer with a first grain size on a substrate to form an amorphous bit line metal layer with a second grain size smaller than the first grain size. Control the deposition of the film stack onto the amorphous bit line metal layer; Receive data for a third structure to control the etching of the film stack and the amorphous bit line metal layer to form a patterned film stack on the substrate; and The patterned film stack on the substrate is controlled to undergo thermal annealing to form a third grain size of the amorphous bit line metal layer, wherein the third grain size is larger than the second grain size.

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