Memory circuits with selectively coupled sampling amplifiers on access lines and methods for operating these

Abstract

A memory circuit comprises: a first memory cell configured to store a first data bit; a second memory cell configured to store a second data bit; a sampling amplifier coupled to the first and second memory cells, respectively, via a data bit line and a reference bit line; a first switch; and a second switch. The first switch is selectively coupled between the data bit line and a first input node of the sampling amplifier, and the second switch is selectively coupled between the reference bit line and a second input node of the sampling amplifier.

Description

REFERENCE TO RELATED REGISTRATION

[0001] This application claims the priority and benefit of the preliminary U.S. application No. 63 / 719,851, filed on November 13, 2024, which is incorporated herein by reference in its entirety for all purposes. BACKGROUND

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density stems from repeated reductions in the minimum component size, allowing more components to be integrated into a given area. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood from the detailed description below, when read together with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows an example block diagram of a memory circuit, according to some embodiments. Fig. Figure 2 shows an example circuit diagram of a memory cell of the memory circuit of Fig. 1, according to some embodiments. Fig. Figure 3 shows an example circuit diagram of a section of the storage circuit of Fig. 1, according to some embodiments. Fig. Figure 4 shows waveforms of different signals during the operation of the storage circuit of Fig. 1, according to some embodiments. Fig. 5, Fig. 6 and Fig. Figure 7 shows example circuit diagrams of switches in the storage circuit of Fig. 1, according to some embodiments. Fig. Figure 8 shows another example circuit diagram of a section of the storage circuit of Fig. 1, according to some embodiments. Fig. Figure 9 shows an alternative circuit diagram of a sampling amplifier for the storage circuit of Fig. 1, according to some embodiments. Fig. Figure 10 shows another alternative circuit diagram of a sampling amplifier for the storage circuit of Fig. 1, according to some embodiments. Fig. Figure 11 shows an example flowchart of a procedure for operating the memory circuit of Fig. 1, according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments, or examples, for implementing various features of the present subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the sake of simplicity and clarity and does not, in itself, prescribe any relationship between the various designs and / or configurations discussed.

[0005] Furthermore, terms relating to spatial relativity, such as "below," "under," "lower," "above," "upper," "above," "below," and the like, may be used herein for the convenience of discussion to describe the relationship of one element or feature to another element or feature (or other elements or features), as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the apparatus used or operated in addition to the orientation illustrated in the figures. The apparatus may be oriented in a different way (rotated by 90 degrees or otherwise), and the terms relating to spatial relativity used herein may likewise be interpreted accordingly.

[0006] Many modern electronic devices incorporate electronic storage devices designed to store data. An electronic storage device is typically either volatile or non-volatile. Volatile storage devices retain data while powered, while non-volatile storage devices retain data even when power is lost. A resistive random-access memory (RRAM) device is a promising candidate for next-generation non-volatile memory technology. RRAM devices feature a simple structure, a small cell area, low switching voltage and fast switching times, and compatibility with CMOS (complementary metal-oxide semiconductor) fabrication processes.

[0007] The RRAM device features a variable-resistance dielectric layer sandwiched between conductive electrodes and is designed to operate based on a reversible switching process between resistance states. This reversible switching is enabled by the selective formation of a conductive filament through the variable-resistance dielectric layer. For example, the normally insulating variable-resistance dielectric layer can be made conductive by applying a voltage across the conductive electrodes to form a conductive filament extending through the layer. An RRAM cell can have a first resistance state (e.g., a high-resistance state) corresponding to a first data state (e.g., a logic '0') and a second resistance state (e.g., a high-resistance state).exhibit a low-resistance state that corresponds to a second data state (e.g., a logical '1').

[0008] Scaling existing RRAM circuits can be limited due to a deterioration in performance and reliability characteristics. For example, if the size of an RRAM cell (typically implemented in the back-end-of-line network) decreases in proportion to the number of transistors (typically implemented in the front-end-of-line network), parasitic capacitance at various terminals (e.g., C) tends to increase. gdThe transistors are used accordingly. The data state stored by an RRAM cell is typically determined by a sampling amplifier formed from some of these transistors in the front-end-of-line network. In existing RRAM circuits, data lines (e.g., bit lines) of the RRAM cell are directly coupled to input nodes of the sampling amplifier. Such coupling to the input nodes has the disadvantage of narrowing the read window of the RRAM cell. This problem becomes increasingly critical as parasitic capacitance increases with scaling. Therefore, existing RRAM circuits are not entirely satisfactory in certain aspects.

[0009] The present disclosure provides various embodiments of a memory circuit comprising a sampling amplifier whose input nodes are selectively coupled to data lines of one or more corresponding memory cells. In some embodiments, the memory cell of the disclosed memory circuit may be an RRAM cell. However, it is understood that the memory cell may be any of various other non-volatile memory cells, e.g., a magnetoresistive random-access memory cell (MRAM cell), a spintronic memory cell, a one-time programmable memory cell (OTP cell), etc., or volatile memory cells, e.g., a static random-access memory cell (SRAM cell), while still remaining within the scope of the present disclosure. The sampling amplifier may comprise a pair of cross-coupled inverters with two input nodes, each selectively coupled to a pair of access lines (e.g.,a data line and a reference line). For example, during an evaluation phase, the input nodes are coupled to the access lines, while the input nodes are decoupled from the cross-coupled inverters; and during a latch phase, the input nodes are decoupled from the access lines, while the input nodes are coupled to the cross-coupled inverters. By selectively coupling the input nodes to the access lines, a data bit stored in the input node(s) can advantageously be protected from contamination by any parasitic capacitance. Consequently, the disclosed memory circuit cannot exhibit the aforementioned problems, even if it follows the trend toward miniaturizing transistor dimensions.

[0010] Fig. Figure 1 shows an example block diagram of a memory circuit 100, according to various embodiments of the present disclosure. As shown, the memory circuit 100 comprises one or more memory arrays 110, a word line driver (WL driver) 120, an input / output circuit (I / O circuit) 130, and a memory controller 140. It is understood that the block diagram of Fig. 1 has been simplified for illustrative purposes, and therefore the memory circuit 100 may include any number of different other components, e.g. a sinker, a source line driver (SL driver), a preload circuit, etc., while remaining within the scope of the present disclosure.

[0011] The memory array 110 comprises multiple first memory circuits or first memory cells 115 and multiple second memory circuits of second memory cells 117, which may be arranged in two-dimensional or three-dimensional arrays. In some embodiments, each of the first memory cells 115 and the second memory cells 117 comprises an RRAM cell. However, each of the first / second memory cells 115 / 117 may comprise any of various other configurations of memory cells while remaining within the scope of this disclosure. For example, each of the first / second memory cells 115 / 117 may comprise an MRAM cell, a spintronic memory cell, an OTP memory cell, or an SRAM cell.

[0012] As below in Fig. As shown in Figure 2, each of the first / second memory (RRAM) cells 115 / 117 can be implemented as a 1-transistor-1-resistor structure (1T1R structure), e.g., a resistor with a variable resistor connected in series with a transistor. Each of the first / second memory cells 115 / 117 of the memory array 110 can be coupled to a corresponding word line WL and a corresponding bit line BL. For example, the memory array 110 has a number of word lines WLs, e.g., WL <0> , WL <1> ...WL <n-1>The memory array 110 also has a number of bit lines BLs, e.g., BL1. <0> , BL <1> ...BL <k-1>, which are arranged in multiple lines. The number "K" can be any integer. Each of the bit lines BLs can extend in a second direction perpendicular to the first direction.

[0013] In some embodiments, the first memory cells 115 are each configured to store a data bit corresponding to either a high-resistance state or a low-resistance state, while the second memory cells 117 are each configured to provide a reference resistance between the high resistance and the low resistance. The first memory cell 115 and the second memory cell 117 are sometimes referred to as "data cell 115" and "reference cell 117," respectively. As will be discussed below, each of the data cells 115, with a corresponding reference cell 117, is coupled to a sampling amplifier (the I / O circuit 130), the corresponding reference cell 117 being configured to provide a reference signal (e.g.,to provide voltage, current) for the sampling amplifier to identify or otherwise determine the logical state of a data bit stored by data cell 115. In some embodiments, the second memory cells 117 may be arranged along one or more of the K columns (sometimes referred to as "reference columns"), while the first memory cells 115 may be arranged along the remaining K columns (sometimes referred to as "data columns").

[0014] The memory controller 140 is a hardware component that can control (e.g., read) operations of the memory array 110 via the WL controller 120 and / or the I / O circuit 130. The WL driver circuit 120 and the I / O circuit 130 can each be implemented as one or more logic circuits, one or more analog circuits, or a combination thereof. In some embodiments, the WL driver circuit 120 is a circuit that can supply a voltage or current (e.g., a WL activation signal with one or more pulses) across an activated word line WL of the memory array 110, and the I / O circuit 130 is a circuit that can supply or sample a voltage or current across one or more bit lines BLs of the memory array 110. As will be discussed in more detail below, the I / O circuit 130 can include a number of sampling amplifiers.Each of the sampling amplifiers can be coupled to a reference cell 117 and a data cell 115 via a pair of bit lines BLs (sometimes referred to as a "reference bit line RBL" and a "data bit line DBL," respectively), wherein the sampling amplifier has a pair of input nodes that are selectively coupled to the reference bit line RBL and the data bit line DBL, respectively, via a first switch and a second switch. In some other embodiments, the memory circuit 100 may have more, fewer, or different components than in . Fig. Figure 1 shows. For example, the memory circuit 100 can also have a timing control that can provide control signals or clock signals to synchronize operations of the WL driver circuit 120 and the I / O circuit 130.

[0015] Fig. Figure 2 shows an example circuit diagram of a memory cell (hereinafter referred to as "memory cell 200") of the memory array 110, according to some embodiments of the present disclosure. Fig. 2 The memory cell 200, which has a transistor and a variable resistor connected in series (1T1R), can represent an embodiment of the data cell 115 and / or the reference cell 117 in some embodiments. However, it is understood that the circuit diagram of Fig. 2 is provided for illustrative purposes only and is not intended to limit the scope of the present disclosure.

[0016] As shown, memory cell 200 has a variable resistor 210 and an access transistor 220 connected in series. The variable resistor 210 can represent a resistance state that can be switched between a low-resistance state (LRS) and a high-resistance state (HRS). The resistance state indicates a data value (e.g., a logic "1" or a logic "0") stored within memory cell 200. Furthermore, a first terminal of the variable resistor 210 is connected to a bit line BL, a second terminal of the variable resistor 210 is connected to a first source / drain terminal of the access transistor 220, a gate terminal of the access transistor 220 is connected to a word line WL, and a second source / drain terminal of the access transistor 220 is connected to a source line SL, which is typically connected to ground.In this configuration, the access transistor 220 can be activated (e.g., switched on) by activating the word line WL, for example by applying a signal with a logic 1 to the gate terminal of the access transistor 220. After activation, another signal can be applied to the bit line BL to read or write the variable resistor 210.

[0017] In some embodiments, the access transistor 220 can be formed in the front-end-of-line network, while the variable resistor 210 can be formed in the back-end-of-line network. In some embodiments, both the access transistor 220 and the variable resistor 210 can be formed in the back-end-of-line network. Generally, the front-end-of-line network refers to structures formed along the main surface of a semiconductor substrate, and the back-end-of-line network refers to structures formed in metallization layers arranged above the main surface of the semiconductor substrate.

[0018] The variable resistor 210 typically features a resistive switching element / dielectric layer with variable resistance arranged between an upper electrode and a lower electrode. In some embodiments, the upper electrode contains titanium (Ti) and tantalum nitride (TaN), the lower electrode contains titanium nitride (TiN), and the dielectric layer with variable resistance contains, for example, nickel oxide (NiO), titanium oxide (TiO), hafnium oxide (HfO), zirconium oxide (ZrO), zinc oxide (ZnO), tungsten oxide (WO3), aluminum oxide (Al2O3), tantalum oxide (TaO), molybdenum oxide (MoO), or copper oxide (CuO). In some embodiments, the lower electrode can be formed in a lower of the metallization layers, and the upper electrode can be formed in a higher of the metallization layers.Furthermore, an upper electrode via (TEVA) can be formed above the upper electrode, and a lower electrode via (BEVA) can be formed below the lower electrode, which allows the variable resistor 210 to be connected to other structures / components, such as the access transistor 220, the bit line BL, etc.

[0019] Fig. Figure 3 shows an example circuit diagram of a section of the storage circuit 100, according to some embodiments of the present disclosure. For example, the circuit diagram of Fig. 3 one of the sampling amplifiers of the I / O circuit 130 (hereinafter referred to as "sampling amplifier 310"), which is coupled to one of the data cells of the memory array 110 (hereinafter referred to as "data cell 320") and one of the reference cells of the memory array 110 (hereinafter referred to as "reference cell 322").

[0020] Each of the data cell 320 and the reference cell 322 can be similar to memory cell 200 ( Fig. 2) be formed, for example, by having a 1T1R configuration. However, data cell 320, similar to data cell 115, can be programmed with an HRS (e.g., a logic 0) or an LRS (e.g., a logic 1), while reference cell 322, similar to reference cell 117, is configured to be programmed with a constant resistance state that lies between the HRS and the LRS. In other words, data cell 320 can conduct a relatively low current when programmed with the HRS and a relatively high current when programmed with the LRS, while reference cell 322 can conduct a constant current between the relatively high and the relatively low current.

[0021] As shown, the sampling amplifier 310 is coupled to the data cell 320 and the reference cell 322, respectively, via a data bit line DBL 330 and a reference bit line RBL 332. The sampling amplifier 310 is coupled to the data bit line DBL 330 and the reference bit line RBL 332, respectively, via a first switch 340 and a second switch 342. Furthermore, in some embodiments, the data bit line DBL 330 is selectively coupled to a first input node “Qi” of the sampling amplifier 310 via the first switch 340, and the reference bit line RBL 332 is selectively coupled to a second input node “QBi” of the sampling amplifier 310 via the second switch 342. When the first switch 340 is activated, the input node Qi is connected to the data bit line DBL 330. and when the first switch 340 is deactivated, the input node Qi is disconnected from the data bit line DBL 330.Similarly, when the second switch 342 is enabled, the input node QBi is connected to the reference bit line RBL 332; and when the second switch 342 is disabled, the input node QBi is disconnected from the reference bit line RBL 332. As will be discussed below, both the first switch 340 and the second switch 342 can be enabled / disabled by a common switch enable signal (SWEN signal), which can transition from a first logical state to a second logical state based on a signal (QB signal) present on the reference bit line RBL 332.

[0022] The sampling amplifier 310, as disclosed herein, can comprise transistors M1, M2, M3, M4, M5, M6, M7, and M8. Transistors M1 through M4 can each be implemented as a p-type metal-oxide-semiconductor transistor (p-MOS transistor), and transistors M5 through M8 can each be implemented as an n-type MOSFET transistor. It is understood that transistors M1 through M8 can be implemented as any of several other types of transistors while still remaining within the scope of this disclosure. In some embodiments, transistors M1, M2, M7, and M8 can conditionally form a pair of cross-coupled inverters when transistors M3 through M6 are activated (or switched on). Transistors M3 through M6 may sometimes be referred to as input transistors, with transistors M3 and M5 forming a first pair of input transistors and transistors M4 and M5 forming a second pair of input transistors.

[0023] When transistors M3 to M6 are enabled, each transistor can form a conduction path between its source / drain terminals. For example, when transistor M3 is enabled, both its first and second source / drain terminals, forming a short circuit (or first conduction path), are connected to input node Qi; and when transistor M3 is disabled, the first and second source / drain terminals are disconnected, with the first source / drain terminal connected to transistor M1 and the second source / drain terminal connected to input node Qi.When transistor M4 is enabled, both its first and second source / drain terminals, forming a short circuit (or a second conduction path), are connected to input node QBi; and when transistor M4 is disabled, the first and second source / drain terminals are disconnected, with the first source / drain terminal connected to transistor M2 and the second source / drain terminal connected to input node QBi. When transistor M5 is enabled, both its first and second source / drain terminals, forming a short circuit (or a third conduction path), are connected to input node Qi; and when transistor M5 is disabled, the first and second source / drain terminals are disconnected, with the second source / drain terminal connected to transistor M7 and the first source / drain terminal connected to input node Qi.When transistor M6 is enabled, both its first and second source / drain terminals, forming a short circuit (or a fourth conduction path), are connected to input node QBi; and when transistor M6 is disabled, the first and second source / drain terminals are separated, with the second source / drain terminal connected to transistor M8 and the first source / drain terminal connected to input node QBi.

[0024] A first source / drain terminal of transistor M1 is connected to VDD, and a second source / drain terminal of transistor M1 can be coupled to input node Qi via the first conduction path formed by the activated transistor M3; a first source / drain terminal of transistor M2 is connected to VDD, and a second source / drain terminal of transistor M2 can be coupled to input node QBi via the second conduction path formed by the activated transistor M4; a first source / drain terminal of transistor M7 is connected to VSS, and a second source / drain terminal of transistor M7 can be coupled to input node Qi via the third conduction path formed by the activated transistor M5;and a first source / drain terminal of transistor M8 is connected to VSS, and a second source / drain terminal of transistor M8 can be coupled to input node QBi via the fourth path formed by the activated transistor M6. Furthermore, the respective gate terminals of transistors M1 and M7 are connected to each other and also coupled to input node QBi; and the respective gate terminals of transistors M2 and M8 are connected to each other and also coupled to input node Qi. Therefore, a first inverter formed by transistors M1 and M7 and a second inverter formed by transistors M2 and M8 can be cross-coupled. The first inverter can have an input at input node QBi and an output at input node Qi; and the second inverter can have an input at input node Qi and an output at input node QBi.

[0025] In some embodiments, transistors M3 and M4 can be switched on / off by a first activation signal (ENB signal), with, for example, their gate terminals configured to receive the ENB signal; and transistors M5 and M6 can be switched on / off by a second activation signal (EN signal), with, for example, their gate terminals configured to receive the EN signal. The EN and ENB signals are logically inversely related, and therefore the pair of transistors M3 and M4 and the pair of transistors M5 and M6 can be switched on alternately. As will be discussed below, the EN / ENB signal can transition from a first logic state to a second logic state based on a signal (QB signal) present on the reference bit line RBL 332.

[0026] As also in Fig. As shown in Figure 3, the memory circuit 100 also includes transistors M9, M10, and M11, which serve operationally as a pre-load circuit. Transistors M9 to M11 can each be implemented as a p-MOS transistor, with their gate terminals configured to receive a pre-load signal (PCB signal). When activated by the PCB signal (e.g., during a pre-load phase), transistor M11 can act as an equalizer, and transistors M9 and M10 can each load the signal present on data bit line DBL 330 (Q signal) or the signal present on reference bit line RBL 332 (QB signal), respectively, onto VDD (or a logic 1). As will be discussed below, such a pre-load phase of the memory circuit 100 can occur before an evaluation phase of the memory circuit 100.

[0027] Fig. Figure 4 shows example waveforms of some of the signals identified above, which change over time, for operating the memory circuit 100 ( Fig. 1) or the sampling amplifier 310 ( Fig. 3) according to some embodiments of the present disclosure. For example, the waveforms of the PCB signal, the SWEN signal, the Q signal, the QB signal, a QB_DET signal, the EN signal, a signal present at input node Qi (hereinafter referred to as the “Qi signal”), and a signal present at input node QBi (hereinafter referred to as the “QBi signal”) are shown. In general, the waveforms shown in Fig. The 4 waveforms shown represent three different operating phases of the storage circuit 100, for example a pre-charge phase (PCH phase), an evaluation phase (EVA phase) and a latch phase (LAT phase).

[0028] During the PCH phase, the PCB signal, the SWEN signal, and the EN signal are each provided at logic 0, logic 1, and logic 0, respectively. Therefore, transistors M9 to M11 (of the pre-charge circuit) can be switched on, so that both the Q signal and the QB signal are pre-charged (or charged) to VDD (or a logic 1). In some embodiments, the QB_DET signal can remain at logic 0 as long as the QB signal drops to a certain voltage level. Since the EN signal is at logic 0 (and the ENB signal is at logic 1), transistors M3 to M6 are all switched off; and since the SWEN signal is at logic 1, switches 320 and 342 are activated. Accordingly, the input nodes Qi and QBi can each be coupled to the data bit line DBL 330 and the reference bit line RBL 332 respectively, while remaining isolated, since no conduction path is formed via the source / drain terminals of any of the transistors M3.

[0029] During the EVA phase, the PCB signal, SWEN signal, and EN signal are each provided with a logic 1, a logic 1, and a logic 0, respectively. Therefore, transistors M9 to M11 (of the pre-charge circuit) can be switched off, thus decoupling the data bit line DBL 330 and the reference bit line RBL 332 from VDD. Since the EN signal is at logic 0 (and the ENB signal is at logic 1), transistors M3 to M6 are all switched off; and the SWEN signal is at logic 1, switches 320 and 342 are activated. Accordingly, input nodes Qi and QBi can be coupled to the data bit line DBL 330 and the reference bit line RBL 332, respectively. In other words, the signals present at input node Qi and on data bit line DBL 330 are the same, and the signals present at input node QBi and on reference bit line RBL 332 are the same.In some embodiments, the input nodes Qi and QBi can be considered isolated, since no conduction path is formed via the source / drain terminals of any of the transistors M3 to M6. This can advantageously solve the problems of parasitic coupling from one or more of the transistors M1, M2, M7, and M8. Since the data bit line DBL 330 and the reference bit line RBL 332 are each decoupled from VDD, the Q signal (equal to the Qi signal) and the QB signal (equal to the QBi signal) can discharge from VDD (or a logic 1), with their respective discharge rates based on the currents flowing through the data cell 320 and the reference cell 322, respectively.

[0030] During the LAT phase, the PCB signal, the SWEN signal, and the EN signal are each provided at logic 1, logic 0, and logic 1, respectively. Therefore, transistors M9 to M11 (of the pre-charge circuit) can be switched off, thus decoupling the data bit line DBL 330 and the reference bit line RBL 332 from VDD. Since the EN signal is at logic 1 (and the ENB signal is at logic 0), transistors M3 to M6 can be switched on in some embodiments, causing each of transistors M3 to M6 to form a transmission path. Accordingly, transistors M1, M2, M7, and M8 can operationally form a pair of cross-coupled inverters. Since the SWEN signal is at a logical 0, switches 320 and 342 are deactivated, which means that the input nodes Qi and QBi are decoupled from the data bit line DBL 330 and the reference bit line RBL 332, respectively.The cross-coupled inverters can therefore buffer and amplify the difference between the Qi signal and the QBi signal (evaluated in the EVA phase). In some embodiments, the QB_DET signal can transition from logic 0 to logic 1 when the QB signal drops to a sufficiently low voltage level, e.g., VDD / 2 (as indicated by symbolic arrow 401); when the QB_DET signal switches to logic 1, the SWEN signal can also transition to logic 1, and the EN signal can transition to logic 1 as well (as indicated by symbolic arrows 403 and 405, respectively).

[0031] Fig. 5, Fig. 6 and Fig. Figure 7 shows example circuit diagrams of the first switch 340 and the second switch 342, respectively, according to some embodiments of the present disclosure. It is understood that the circuit diagrams of Fig. Figures 5 to 7 are provided for illustrative purposes only and are not intended to limit the scope of the present disclosure.

[0032] In Fig. Each of the first switch 340 and the second switch 342 can be implemented as a transmission gate 510. For example, the transmission gate 510 has a p-transistor 520 and an n-transistor 530, with their first source / drain terminals connected together and their second source / drain terminals connected together. The first source / drain terminals can be connected to the data bit line DBL 330 (or the reference bit line RBL 332), and the second source / drain terminals can be connected to the input node Qi (or the input node QBi). The gate terminals of the n-transistor 530 and the p-transistor 520 are configured to receive the SWEN signal and a logically inverted version of the SWEN signal (SWENB signal), respectively.

[0033] In Fig. Each of the first switch 340 and the second switch 342 can be implemented as a p-transistor 610. A first source / drain terminal of the transistor 610 can be connected to the data bit line DBL 330 (or the reference bit line RBL 332), and a second source / drain terminal of the transistor 610 can be connected to the input node Qi (or the input node QBi). A gate terminal of the transistor 610 is configured to receive a logically inverted version of the SWEN signal (SWENB signal).

[0034] In Fig. Each of the first switch 340 and the second switch 342 can be implemented as an n-type transistor 710. A first source / drain terminal of the transistor 710 can be connected to the data bit line DBL 330 (or the reference bit line RBL 332), and a second source / drain terminal of the transistor 710 can be connected to the input node Qi (or the input node QBi). A gate terminal of the transistor 710 is configured to receive the SWEN signal.

[0035] Fig. Figure 8 shows another example circuit diagram of a section of the storage circuit 100, according to some embodiments of the present disclosure. For example, the circuit diagram of Fig. 8 the circuit diagram of Fig. 3 essentially similar, except that the circuit diagram of Fig. 8 has a first trim circuit 810 and a second trim circuit 820. Accordingly, the following discussion focuses on the difference and the reference symbols of Fig. 3 will be reused.

[0036] As shown, the trimming circuit 810 is coupled between the data bit line DBL 330 and the data cell 320, and the trimming circuit 820 is coupled between the reference bit line RBL 332 and the reference cell 330. The trimming circuit 810 can adjust the level of the signal present on the data bit line DBL 330 by activating one or more of its transistors, and the trimming circuit 820 can adjust the level of the signal present on the reference bit line RBL 332 by activating one or more of its transistors. For example, the trimming circuit 810 can have transistors M12 and one or more transistors M13, each of the one or more transistors M13 being coupled to a respective switch 812. and the trimming circuit 820 can include transistors M14, and one or more transistors M15, each of the one or more transistors M15 being coupled to a respective switch 822.The gate terminals of all transistors in the 810 and 820 trim circuits can be connected to a common signal. However, one or more transistors M13 can each selectively provide a current flowing through the data bit line DBL 330, and one or more transistors M15 can each selectively provide a current flowing through the reference bit line RBL 332.

[0037] Fig. 9 and Fig. Figure 10 shows different example circuit diagrams 910 and 1010 of the sampling amplifier of the I / O circuit 130 (hereinafter "sampling amplifier 910" and "sampling amplifier 1010"), according to some embodiments of the present disclosure. Each of the sampling amplifiers 910-1010 is the one described in Figure 10. Fig. The sampling amplifier 310 shown in Figure 3 is essentially similar, except that the sampling amplifier 910 has only p-input transistors, and the sampling amplifier 1010 has only n-input transistors. Accordingly, the following discussion focuses on the difference and some of the reference symbols of Fig. 3 will be reused.

[0038] In Fig. In addition to transistors M1-M2 and M7-M8, which operate as a pair of cross-coupled inverters, the sampling amplifier 910 has only the p-input transistors M3-M4. Therefore, input node Qi, while selectively coupled to the data bit line DBL 330 via switch 340, is connected to the second source / drain terminal of transistor M3 and directly to the first source / drain terminal of transistor M7; and input node QBi, while selectively coupled to the reference bit line RBL 332 via switch 342, is connected to the second source / drain terminal of transistor M4 and directly to the first source / drain terminal of transistor M8.

[0039] In Fig. In addition to the transistors M1-M2 and M7-M8, which operate as a pair of cross-coupled inverters, the sampling amplifier 1010 has only the n-input transistors M5-M6. Therefore, the input node Qi, while selectively coupled to the data bit line DBL 330 via switch 340, is directly connected to the second source / drain terminal of transistor M1 and to the first source / drain terminal of transistor M5; and the input node QBi, while selectively coupled to the reference bit line RBL 332 via switch 342, is directly connected to the second source / drain terminal of transistor M2 and to the first source / drain terminal of transistor M6.

[0040] Fig. Figure 11 shows a flowchart of an example method 1100 for operating a memory circuit, according to some embodiments of the present disclosure. For example, at least some of the operations (or steps) of method 1100 can be used to operate a memory circuit 100 through the data cell 115 ( Fig. 1) to read a stored data bit. The data bit can be read (or determined) by any of the disclosed sampling amplifiers, e.g., sampling amplifier 310. It should be noted that method 1100 is merely an example and is not intended to limit the scope of this disclosure. Accordingly, it is understood that additional operations before, during, and / or after method 1100 are not to be considered. Fig. 11 can be provided, and some other processes can only be briefly described here.

[0041] Method 110 begins with step 1110 of preloading a data bitline and a reference bitline to a first logical state, wherein the data bitline and the reference bitline are each coupled to a first input node and a second input node of a sampling amplifier, respectively. In some embodiments, the data bitline is coupled to a data cell, while the reference line is coupled to a reference bit cell. Using the memory circuit 100 (and one of its in Fig. In the implementations shown (3), as a non-limiting example, both the data bitline DBL 330 and the reference bitline RBL 332 are pre-charged to VDD (e.g., a logic 1) by the pre-load circuit, which is operationally formed by transistors M9 to M11, before comparing the respective signals (Q and QB signals) present on the data bitline DBL 330 and the reference bitline RBL 332. During such a pre-load phase, switches 340 and 342 are activated simultaneously, and therefore the data bitline DBL 330 and the reference bitline RBL 332 can each be simultaneously coupled to the input nodes Qi and QBi, respectively, of the sampling amplifier 310.

[0042] Procedure 1100 continues with step 1120, in which the data line and the reference line are discharged, with the first input node and the second input node remaining coupled to the data line and the reference line, respectively, and the first input node and the second input node each being decoupled from every transistor. To continue with the preceding example, after the data bit line DBL 330 and the reference bit line RBL 332 have been preloaded to VDD, transistors M9 to M11 (of the preload circuit) are switched off, transistors M3 to M6 of the sampling amplifier 310 are switched off, and switches 340-342 remain enabled. Accordingly, the input nodes Qi and Qbi of the sampling amplifier 310 are isolated from the transistors M1-M2 and M7-M8, but remain coupled to the data cell 320 and the reference cell 322 respectively via the data bit line DBL 330 and the reference bit line RBL 332.Since switches 340 and 342 remain activated, the Q signal is the same as the Qi signal, and the QB signal is the same as the QBi signal.

[0043] The Q signal can correspond to the logical state of a first data bit stored in data cell 320, and the QB signal can correspond to the logical state of a second data bit stored in reference cell 322. In various embodiments, the first data bit is configured to be programmed with a first logical state, e.g., HRS, or a second logical state, e.g., LRS, while the second data bit is configured to be programmed to a constant resistance state between the first and second logical states, e.g., (HRS+LRS) / 2. Therefore, the Q signal and the QB signal can represent respective voltage levels dropped from VDD by different amounts. These voltage amounts can correspond to the different resistance states stored by data cell 320 and reference cell 322, respectively.For example, if the first data bit is programmed with the HRS and the second data bit is set to (HRS+LRS) / 2, the Q signal can decay at a slower VDD rate compared to the QB signal. Conversely, if the first data bit is programmed with the LRS and the second data bit is set to (HRS+LRS) / 2, the Q signal can decay at a faster VDD rate compared to the QB signal.

[0044] Method 1100 continues with step 1130, in which a data bit stored by the data cell is temporarily stored, with the first and second input nodes being decoupled from the data line and the reference line, respectively. Continuing with the preceding example, after the QB signal (present on the reference bit line RBL 332) drops to a sufficiently low voltage level, e.g., VDD / 2, transistors M3 to M6 can be switched on by the EN signal, which is further triggered by the QB_DET signal. In some embodiments, the QB_DET signal can transition from logic 0 to logic 1 when the QB signal drops to a level around VDD / 2. Simultaneously with the transition of the QB_DET signal to logic 1, switches 340 and 342 can be deactivated, e.g., by the SWEN signal. Consequently, the input nodes Qi and QBi of the sampling amplifier 310 are each connected to the data bit line 330 and QBi, respectively.The reference bit line RBL 332 is decoupled, and the transistors M1-M2 and M7-M8, which operate as a pair of cross-coupled inverters, can hold and amplify the Q signal.

[0045] In one aspect of the present disclosure, a memory circuit is disclosed. The memory circuit comprises: a first memory cell configured to store a first data bit; a second memory cell configured to store a second data bit; a sampling amplifier coupled to the first memory cell and the second memory cell, respectively, via a data bit line and a reference bit line; a first switch; and a second switch. The first switch is selectively coupled between the data bit line and a first input node of the sampling amplifier, and the second switch is selectively coupled between the reference bit line and a second input node of the sampling amplifier.

[0046] In another aspect of the present disclosure, a memory circuit is disclosed. The memory circuit comprises: a sampling amplifier configured to identify a data bit stored by a first memory cell based on a comparison of a first signal present on a data bit line connecting the first memory cell to the sampling amplifier and a second signal present on a reference bit line connecting a second memory cell to the sampling amplifier; a first switch configured to selectively couple the data bit line to a first input node of the sampling amplifier based on an activation signal; and a second switch configured to selectively couple the reference bit line to a second input node of the sampling amplifier based on the activation signal.

[0047] In a further aspect of the present disclosure, a method for operating memory circuits is disclosed. The method comprises preloading a data bitline and a reference bitline to a first logical state, wherein the data bitline and the reference bitline are each coupled to a first input node and a second input node of a sampling amplifier, respectively, the data bitline being coupled to a data cell and the reference bitline being coupled to a reference cell. The method comprises discharging the data bitline and the reference bitline, wherein the first input node and the second input node remain coupled to the data bitline and the reference bitline, respectively, and wherein the first input node and the second input node are each decoupled from every transistor.The method includes an intermediate storage of a data bit stored by the data cell, wherein the first input node and the second input node are decoupled from the data bit line and the reference bit line, respectively.

[0048] As used here, the terms "approximately" and "about" generally indicate the value of a given quantity, which may vary based on a specific technology node associated with the semiconductor device in question. Based on that specific technology node, the term "approximately" may indicate a value of a given quantity that varies, for example, within 10 to 30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0049] The foregoing outlines features of several embodiments so that a person skilled in the art can better understand the aspects of the present disclosure. A person skilled in the art should recognize that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to accomplish the same tasks and / or achieve the same advantages as the embodiments presented herein. A person skilled in the art should also understand that such equivalent embodiments do not deviate from the inventive concept and scope of the present disclosure, and that they can make various changes, substitutions, and modifications here without deviating from the inventive concept and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 719,851

[0001]

Claims

[1] Memory circuit comprising: a first memory cell that is set up to store a first data bit, a second memory cell configured to store a second data bit, a sampling amplifier that is coupled to the first memory cell and the second memory cell respectively via a data bit line and a reference bit line, a first switch, and a second switch wherein the first switch is selectively coupled between the data bit line and a first input node of the sampling amplifier, and the second switch is selectively coupled between the reference bit line and a second input node of the sampling amplifier. [2] Memory circuit according to claim 1, wherein the first data bit represents either a logical high state or a logical low state, and the second data bit is associated with a constant logical state between the logical high state and the logical low state. [3] Memory circuit according to claim 1 or 2, wherein the first and second switches each comprise a transmission gate, a p-transistor, or an n-transistor. [4] Memory circuit according to one of claims 1 to 3, wherein the sampling amplifier further comprises: a first p-type transistor, a second p-type transistor, a third p-type transistor, a fourth p-type transistor, a fifth n-type transistor, a sixth n-type transistor, a seventh n-type transistor, and an eighth n-type transistor. [5] Memory circuit according to claim 4, wherein the first, third, fifth and seventh transistors are connected in series between a supply voltage and a ground voltage, and the second, fourth, sixth and eighth transistors are connected in series between the supply voltage and the ground voltage. [6] Memory circuit according to claim 5, wherein the gate terminals of the first and seventh transistors are connected to the second input node, and the gate terminals of the second and eighth transistors are connected to the first input node. [7] Memory circuit according to claim 5, wherein the gate terminals of the third and fourth transistors are configured to receive a first control signal together, and the gate terminals of the fifth and sixth transistors are configured to receive a second control signal that is logically opposite to the first control signal together. [8] Memory circuit according to claim 5, wherein first source / drain terminals of the third and fifth transistors are connected to each other at the first input node, and first source / drain terminals of the fourth and sixth transistors are connected to each other at the second input node. [9] Memory circuit according to claim 5, wherein during an evaluation phase of the sampling amplifier the third to sixth transistors are switched off, and the first, second, seventh and eighth transistors are switched on, wherein the first and second switches are activated, whereby the data bit line is coupled to the first input node and the reference bit line is coupled to the second input node. [10] Memory circuit according to claim 5, wherein during a latch phase of the sampling amplifier the first to eighth transistors are switched on, wherein the first and second switches are deactivated, thereby decoupling the first input node from the data bit line and decoupling the second input node from the reference bit line. [11] Memory circuit according to any one of claims 1 to 10, wherein the first memory cell and the second memory cell each comprise a non-volatile memory cell. [12] Memory circuit comprising: a sampling amplifier configured to identify a data bit stored by a first memory cell based on a comparison of a first signal present on a data bit line connecting the first memory cell to the sampling amplifier and a second signal present on a reference bit line connecting a second memory cell to the sampling amplifier, a first switch configured to selectively couple the data bit line to a first input node of the sampling amplifier based on an activation signal, and a second switch configured to selectively couple the reference bit line to a second input node of the sampling amplifier based on the activation signal. [13] Memory circuit according to claim 12, wherein the first memory cell and the second memory cell each comprise a non-volatile memory cell. [14] Memory circuit according to claim 12 or 13, wherein the first signal corresponds to a logic high state or a logic low state, while the second signal corresponds to a logic state between the logic high state and the logic low state. [15] Memory circuit according to one of claims 12 to 14, wherein the sampling amplifier further comprises: a first p-type transistor, a second p-type transistor, a third p-type transistor, a fourth p-type transistor, a fifth n-type transistor, a sixth n-type transistor, a seventh n-type transistor, and an eighth n-type transistor. [16] Memory circuit according to claim 15, wherein the first, third, fifth and seventh transistors are connected in series between a supply voltage and a ground voltage, and the second, fourth, sixth and eighth transistors are connected in series between the supply voltage and the ground voltage. [17] Memory circuit according to claim 16, wherein during an evaluation phase of the sampling amplifier the third to sixth transistors are switched off, and the first, second, seventh and eighth transistors are switched on, wherein the first and second switches are activated, whereby the data bit line is coupled to the first input node and the reference bit line is coupled to the second input node. [18] Method for operating a storage circuit, comprising: Preloading a data bitline and a reference bitline to a first logical state, wherein the data bitline and the reference bitline are each coupled to a first input node and a second input node of a sampling amplifier respectively, wherein the data bitline is coupled to a data cell, while the reference bitline is coupled to a reference cell. Discharge of the data bitline and the reference bitline, wherein the first input node and the second input node remain coupled to the data bitline and the reference bitline respectively, and wherein the first input node and the second input node are decoupled from each transistor, and Temporarily storing a data bit stored by the data cell, wherein the first input node and the second input node are each decoupled from the data bit line and the reference bit line, respectively. [19] Method according to claim 18, wherein the data cell and the reference cell each comprise a non-volatile memory cell. [20] Method according to claim 18 or 19, further comprising: Simultaneous activation of a first switch to couple the first input node to the data bit line, and activation of a second switch to couple the second input node to the reference bit line, or Simultaneously disabling the first switch to decouple the first input node from the data bit line, and disabling the second switch to decouple the second input node from the reference bit line.

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