Controller and control method for pseudostatic random access memory

Abstract

The present disclosure provides a controller and a control method for pseudo-static random memory. The controller comprises a digital controller and a physical layer interface, the input end of the physical layer interface is connected with the digital controller, the output end is connected with a pseudo-static random memory (PSRAM) interface, the digital controller is used for receiving an operation request and generating a PSRAM transmission signal adapted to the type of an eight-way serial input / output interface based on the operation request; the input end of the physical layer interface is connected with the digital controller, the output end is connected with the PSRAM interface, and the physical layer interface is used for generating a PSRAM interface signal adapted to the type of the PSRAM interface based on the PSRAM transmission signal. The controller provided by the embodiment of the present disclosure can support different PSRAM chips and improve the flexibility of PSRAM chip selection.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a controller and control method for pseudo-static random access memory. Background Technology

[0002] Pseudo-static random access memory (PSRAM) is a type of random access memory (RAM) that uses the same technology and processes as dynamic random access memory (DRAM) to achieve a similar functionality to static random access memory (SRAM).

[0003] The PSRAM interface is obtained by modifying the DRAM interface and changing the refresh circuit to a self-refresh circuit. It is compatible with SRAM and has similar characteristics to SRAM in terms of access timing. The PSRAM interface has the advantages of DRAM interface such as low cost, low power consumption, high memory density and SRAM interface such as simplicity. Summary of the Invention

[0004] This disclosure provides a PSRAM controller and control method.

[0005] In a first aspect, this disclosure provides a controller for a pseudo-static random access memory (PSRAM), comprising: a digital controller and a physical layer interface, wherein the input terminal of the physical layer interface is connected to the digital controller, and the output terminal is connected to the PSRAM interface, wherein:

[0006] The digital controller is used to receive operation requests and generate PSRAM transmission signals adapted to the type of the eight-channel serial input / output interface based on the operation requests.

[0007] The physical layer interface is used to generate PSRAM interface signals that are compatible with the type of the PSRAM interface based on the PSRAM transmission signals.

[0008] Secondly, this disclosure provides a control method for a controller for a pseudo-static random access memory based on any one of the claims provided in this disclosure, comprising:

[0009] Receive operation requests;

[0010] Based on the operation request, a pseudo-static random access memory (PSRAM) transmission signal adapted to the type of the eight-channel serial input / output interface is generated.

[0011] Used to generate PSRAM interface signals that are compatible with the type of the PSRAM interface based on the PSRAM transmission signals.

[0012] The controller for pseudo-static random access memory (PSRAM) provided in this embodiment includes a digital controller and a physical layer interface. The digital controller generates PSRAM transmission signals adapted to the type of the eight-channel serial input / output interface based on an operation request, enabling the PSRAM transmission signals to be applicable to different PSRAM interfaces. The physical layer interface generates PSRAM interface signals adapted to the type of the PSRAM interface based on the PSRAM transmission signals. Since the PSRAM interface signals are generated according to the type of PSRAM interface, the generated PSRAM interface signals can be compatible with different types of PSRAM interfaces and transmission protocols, allowing the controller to support different PSRAM chips and improving the flexibility of PSRAM chip selection.

[0013] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0014] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0015] Figure 1 This is a schematic diagram of the structure of the PSRAM controller provided in an embodiment of the present disclosure;

[0016] Figure 2 This is a schematic diagram of the structure of a digital controller provided in an embodiment of the present disclosure;

[0017] Figure 3 This is a schematic diagram of the structure of a transmission module provided in an embodiment of the present disclosure;

[0018] Figure 4 A schematic diagram of a state machine in a data shifter provided in an embodiment of this disclosure;

[0019] Figure 5 This is a flowchart illustrating the state machine of the register module during a write operation in an embodiment of this disclosure.

[0020] Figure 6 This is a flowchart illustrating the state machine of the register module when performing a read operation in an embodiment of this disclosure.

[0021] Figure 7 This is a flowchart illustrating the state machine's operation during a write operation in an embodiment of this disclosure.

[0022] Figure 8 This is a flowchart illustrating the state machine during a read operation in an embodiment of this disclosure.

[0023] Figure 9 This is a flowchart illustrating the state machine during the semi-sleep operation in an embodiment of this disclosure.

[0024] Figure 10 This is a flowchart illustrating the process of the state machine exiting semi-sleep mode in an embodiment of this disclosure.

[0025] Figure 11 This is a schematic diagram of the structure of a physical layer interface provided in an embodiment of the present disclosure;

[0026] Figure 12 A flowchart of a control method for a pseudo-static random access memory provided in an embodiment of this disclosure. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0028] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0029] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0031] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0032] Each manufacturer has its own PSRAM interface specification, such as the HyperBus Interface, APM OPI, and Xccela OPI. These interface protocols all use OPI (Octal SPI, eight-channel serial input / output) and DDR (Double Data Rate), but they differ significantly in the number and function of control signals, read / write transmission protocols, access to internal chip register modules, and entry and exit from half-sleep / deep power-down modes. However, these PSRAM interfaces cannot be flexibly configured according to the PSRAM chip, resulting in PSRAM interfaces supporting only one type of interface and failing to meet the practical need for compatibility with multiple PSRAM interfaces.

[0033] Figure 1 This is a schematic diagram of the PSRAM controller provided in an embodiment of this disclosure. (See also...) Figure 1 The PSRAM controller includes a digital controller 1 and a physical layer interface 2. The digital controller 1 is configured to receive access requests (including but not limited to read and write requests) and to provide compatibility and control for different PSRAM chips. The input terminal of the physical layer interface 2 is connected to the digital controller 1, and the output terminal is connected to the PSRAM interface. It is used to generate PSRAM interface signals adapted to the type of the PSRAM interface based on the PSRAM transmission signals, thereby enabling information exchange with different PSRAM chips.

[0034] It should be noted that, in this embodiment of the disclosure, the digital controller 1 may have multiple input terminals and multiple output terminals, and the number of input terminals and output terminals can be set as needed; this embodiment of the disclosure does not limit this. The physical layer interface 2 may have multiple input terminals and multiple output terminals, and the number of input terminals and output terminals can be set as needed; this embodiment of the disclosure does not limit this.

[0035] In some embodiments, the digital controller 1 receives operation requests and generates pseudo-static random access memory (PSRAM) transfer signals adapted to the type of the eight-channel serial input / output interface based on the operation requests. In this embodiment, the digital controller 1 includes two input terminals connected to the APB bus and the AHB bus, respectively. Operation requests can be transmitted to the controller via the APB bus and the AHB bus, and include, but are not limited to, read / write requests and register module access requests. The PSRAM transfer signals are signals that the PSRAM can recognize. The PSRAM transfer signals include transfer signals corresponding to various transfer states in read / write commands, entering / exiting semi-sleep (hybrid sleep), and entering / exiting deep power-down operations.

[0036] In some embodiments, the input terminal of the physical layer interface 2 is connected to the digital controller 1, and the output terminal is connected to the PSRAM interface, for generating PSRAM interface signals that are compatible with the type of the PSRAM interface based on the PSRAM transmission signals. The PSRAM interface includes, but is not limited to, the interface corresponding to AP 8M (APS6408L-OBMx DDR OPI Xccela PSRAM), the interface corresponding to AP 4M (APS3208K-OTx OPI DDR PSRAM), the interface corresponding to WB 8M (W956D8MBYA), and the interface corresponding to WB 4M (W955D8MBYA) (hereinafter referred to as AP 8M interface, AP 4M interface, WB 8M interface, and WB 4M interface, respectively, for ease of description).

[0037] In this embodiment, the input terminal of the physical layer interface 2 is connected to the digital controller 1, and the output terminal is connected to the PSRAM interface. It is used to generate PSRAM interface signals adapted to the type of the PSRAM interface based on the PSRAM transmission signals, and to transmit timing signals together with the digital controller 1. In this embodiment, the physical layer interface 2 can be compatible with various PSRAM interfaces, such as AP 8M, AP 4M, WB 8M, and WB 4M interfaces.

[0038] In some embodiments, the digital controller 1 has two interfaces at its input (system side): an Advanced Peripheral Bus (APB) interface and an Advanced High Performance Bus (AHB-Lite) interface. The APB interface is used to access the Control and Status Register (CSR) module within the digital controller 1. The AHB-Lite interface is used for writing / reading the memory array and mode register module in the PSRAM memory device based on the CSR settings. The output of the digital controller 1 is connected to the input of the physical layer interface 2.

[0039] In some embodiments, the memory controller clock mem_clk_0 and the phase-shift memory controller clock mem_clk_90 are input to the digital controller 1 and the physical layer interface 2. The memory controller clock mem_clk_90 has the same frequency as the phase-shift memory controller clock mem_clk_0, but the phase lags by 90 degrees.

[0040] Figure 2 This is a structural block diagram of a digital controller provided in an embodiment of this disclosure. Figure 2 As shown, the digital controller 1 includes a register module 11, an AHB slave control module 12, a read / write transaction transmission module 13, a first synchronizer 14, and a second synchronizer 15. The register module 11 is signal-connected to the AHB slave control module 12 and the read / write transaction transmission module 13, and the AHB slave control module 12 is signal-connected to the register module 11 and the read / write transaction transmission module 13.

[0041] Register module 11 acts as a slave device of the APB and is connected to the APB interface signal. Register module 11 includes control and status register modules, which receive APB write transactions and output control signals and timing parameters to the AHB slave control module 12 and the read / write transaction transmission module 13. Register module 11 is also used to receive and store status signals.

[0042] In some embodiments, the register module 11 is used to generate APB control signals and timing parameters based on the received APB operation request, and to receive and store transmission status signals.

[0043] The APB operation request includes one or more of the following: APB read request and APB write request. Transmission status signals include, but are not limited to, PSRAM access transmission status, such as the Data Strobe clock (DQS) timeout signal, DPD / HALF SLEEP entry / exit, and GLOBAL RESET instruction completion signal.

[0044] The AHB slave control module 12 is used to respond to received AHB operation requests, obtain AHB instruction information based on APB control signals and timing parameters, and transmit the received PSRAM transmission status information to the AHB master. The AHB operation request includes one or more of the following: an AHB read request and an AHB write request.

[0045] For example, the AHB slave control module 12 parses AHB read / write transactions and outputs transmission parameters (transmission type, read / write length, transmission size), read / write address, and write data. The AHB slave control module 12 includes an asynchronous first-in-first-out (FIFO) module (not shown in the figure) for cross-clock domain synchronization and buffering of command addresses and data between the AHB slave controller clock ahb_clk and the storage controller clock mem_clk_0. The AHB slave control module 12 also receives the timeout signal of the data strobe clock to provide feedback on the transmission status to the AHB master.

[0046] The read / write transaction transmission module 13 is used to generate PSRAM transmission signals based on APB control signals and AHB instruction information, and to receive PSRAM read data and clock signals from physical layer interface 2, sample operation requests based on clock signals, and transmit the sampling results to the AHB slave control module; and to receive transmission status signals.

[0047] The AHB instruction information includes, but is not limited to, transmission parameters (transmission type, read / write length, transmission size), read / write address, and read / write data.

[0048] The read / write transaction transmission module 13 is used to implement read / write transaction transmission between the PSRAM storage and register modules. The read / write transaction transmission module 13 receives control signals from the register module 11 and command addresses and write data from the AHB slave control module 12, generating PSRAM transmission signals to the physical layer interface 2; and receives read data and clock signals from the physical layer interface 2, samples them, and outputs them to the AHB slave control module 12. The read / write transaction transmission module 13 also outputs multiple status indication signals, including a data strobe clock (DQS) timeout signal and a transmission completion signal. The DQS timeout signal indicates whether the DQS returned a timeout, and the transmission completion signal indicates the completion status of each instruction.

[0049] In some embodiments, the read / write transaction transmission module 13 includes a command processing (INSTRN_HANDLER) module 131, a transmit (TX_PATH) module 132, and a receive (RX_PATH) module 133. The command processing module 131 processes various instructions from the register module 11, such as performing edge detection on the received APB control signal and outputting an APB control valid signal and an APB transmission signal. In some embodiments, the instructions output by the register module 11 include, but are not limited to, read / write transmission, half-sleep entry / exit, deep power-down entry / exit, and PSRAM reset. After edge detection of the instruction signal, an instruction valid signal is output to the transmit module 132.

[0050] The transmission module 132 is used to generate PSRAM transmission signals based on each transmission state when transmitting APB control signals and AHB instruction information.

[0051] The receiving and transmitting module 133 is used to transmit data across clock domains based on the data returned by the physical layer interface, and outputs the data of the physical layer interface when the preset conditions are met, and outputs a timeout indication signal when the data strobe signal times out according to the timing parameters.

[0052] In some embodiments, the receiving and transmitting module 133 further includes an asynchronous FIFO module (not shown) for receiving data across clock domains from the data strobe clock DQS to the memory controller clock mem_clk_0. Data is sampled and read using both edges of the received data strobe clock DQS and written to the asynchronous FIFO module. Data is read and output when the asynchronous FIFO module is not empty. The receiving and transmitting module 133 is also used to detect whether DQS has timed out based on timing parameters and output an indication signal.

[0053] In some embodiments, see Figure 3 The transmission module 132 includes a data shifter 321, which generates PSRAM transmission signals according to various commands, addresses, and data in different states during access to the register module, read / write memory, and half-sleep / deep power-off operations. The data shifter 321 has an independent state machine (FSM) designed for various serial input / output (OPI) interfaces to support multiple interfaces and transmission protocols.

[0054] In some embodiments, the data shifter 321 includes a plurality of state machines, each state machine corresponding to an eight-channel serial input / output interface type, and each state machine generates a PSRAM transmission signal based on each transmission state for the corresponding eight-channel serial input / output interface type.

[0055] For example, see Figure 4The data shifter is configured with three state machines (FSMs) 41a, 41b, and 41c. Each state machine 41a, 41b, and 41c is connected to a pseudo-static memory type multiplexer 42. The pseudo-static memory type multiplexer 42 receives the PSRAM type (PSRAM_type) transmission signal and selects the corresponding state machine 41a, 41b, and 41c according to the PSRAM type. The state machines 41a, 41b, and 41c generate PSRAM transmission signals and transmit the PSRAM transmission signals to the physical layer interface.

[0056] The data shifter provided in this embodiment has multiple state machines, each of which can correspond to one or more similar eight-channel serial input / output interfaces. This avoids the cumbersome process of using a single state machine to accommodate multiple eight-channel serial input / output interfaces. When a fault occurs in one of the eight-channel serial input / output interfaces, the state machine can quickly locate the faulty interface. Furthermore, when adding other eight-channel serial input / output interfaces, only the corresponding state machine needs to be added, without affecting the existing state machines.

[0057] refer to Figure 3 The transmission module 132 further includes a timing check module 322 and a write boundary check module 323. The timing check module 322 generates a first indication signal based on timing parameters and transmits the first indication signal to the data shifter 321. For example, the timing check module 322 times the time according to timing parameters (such as CS low time, exit time of half-sleep / deep power-off, etc.) and outputs an indication signal to the data shifter 321 after the time is reached.

[0058] The write boundary check (wr_pg_bndry_checker) module 323 outputs a second indication signal when it determines that the boundary of a memory page has been reached based on the page size parameters and the memory address. For example, the write boundary check module 323 determines whether the write address has reached the boundary based on the page size parameter and the write address and outputs an indication signal to the data shift register 321. The data shift register module 321 responds to the first and second indication signals to transmit APB control signals and AHB instruction information.

[0059] In some embodiments, see Figure 2 The digital controller 1 also includes a first synchronizer 14 and a second synchronizer 15, both of which can be two-stage synchronizers.

[0060] The first synchronizer 14 is used to transmit the timeout signal across clock domains from the clock signal of the digital controller to the clock signal of the AHB. For example, the first synchronizer 14 transmits the timeout signal of the data strobe clock output by the read / write transaction transmission module 13 across clock domains from the memory controller clock mem_clk_0 to the AHB slave controller clock ahb_clk.

[0061] The second synchronizer 15 is used for cross-clock domain transmission of the transmission completion signal from the clock signal of the digital controller to the clock signal of the APB. For example, the second synchronizer 15 transmits the transmission completion signal output by the read / write transaction transmission module 13 across clock domains from the memory controller clock mem_clk_0 to the APB clock apb_clk (the APB clock used for CSR).

[0062] Figure 5 This is a flowchart illustrating the state machine process of the register module during a write operation in an embodiment of this disclosure. (See also...) Figure 5 For example, state machine 41a receives PSRAM type transmission signals from the AP 8M interface.

[0063] Step S501: The state machine is in the idle state (IDLE).

[0064] In step S502, after the register module access request is valid (reg_xfer_valid = 1), the state machine transitions from the idle state to the send command state (SEND_CMD).

[0065] In step S503, within one clock cycle (cmd_cycle_cnt = 1), the state machine transitions from the command sending state to the address sending state (ADDR).

[0066] Step S504: After two clock cycles (wr_rd = 1, addr_cycle_cnt = 2), the system jumps to the transmit delay state (TX_LATENCY).

[0067] Step S505: After the timer satisfies the waiting clock cycle (wait_expired), the process jumps to the data transmission state (TX_DATA).

[0068] In step S506, the data transmission of the register module is fixed at one clock cycle. After one clock cycle (wdata_avalid=0), the state machine jumps to the waiting transmission completion state (WAIT_TR_EXPIRY). After the transmission clock cycle is completed (twc_expired=1), it returns to the idle state.

[0069] It should be noted that when the eight-channel serial input / output interface is WB 8M or WB 4M interface, no delay is required. Therefore, you can jump directly from step S503 to step S505.

[0070] Through the above steps S501 to S506, the register module write operation can be realized.

[0071] Figure 6 This is a flowchart illustrating the state machine process of the register module during a read operation in an embodiment of this disclosure. (See also...) Figure 6 For example, state machine 41a receives the transmission signal from the AP 8M interface.

[0072] Step S601: The state machine is in the idle state (IDLE).

[0073] In step S602, when the access request of the register module is valid (reg_xfer_valid = 1), the state machine transitions from the idle state to the send command state (SEND_CMD).

[0074] In step S603, within one clock cycle (cmd_cycle_cnt = 1), the state machine transitions from the command sending state to the address sending state (ADDR).

[0075] Step S604: After two clock cycles (wr_rd = 0, addr_cycle_cnt = 2), jump to the data reading state (RD_DATA).

[0076] Step S605: After reading the required address length (rd_done = 1), jump to the FIFO refresh state (FIFO_FLUSH) to refresh the FIFO and avoid affecting the next read.

[0077] Step S606: After the FIFO refresh is completed (fifo_flush_done=1), the system jumps to the waiting state for transmission completion (WAIT_TR_EXPIRY). After reading the clock cycle (trc_expired=1), the system returns to the idle state.

[0078] Through the above steps S601 to S606, the read operation of the register module can be realized.

[0079] Figure 7 This is a flowchart illustrating the state machine's operation during a write operation in an embodiment of this disclosure. See also... Figure 7 For example, state machine 41a receives the transmission signal from the AP 8M interface.

[0080] Step S701: The state machine is in the idle state (IDLE).

[0081] In step S702, when the storage access request is valid (mem_xfer_valid = 1), the state machine transitions from the idle state to the send command state (SEND_CMD).

[0082] In step S703, within one clock cycle (cmd_cycle_cnt = 1), the state machine transitions from the command sending state to the address sending state (ADDR).

[0083] Step S704: After two clock cycles (wr_rd = 1, addr_cycle_cnt = 2), the system jumps to the transmit delay state (TX_LATENCY).

[0084] Step S705: After the timer satisfies the wait clock cycle (wait_expired), the process jumps to the data transmission state (TX_DATA).

[0085] In step S705, if the address reaches the page boundary, data is sent up to the boundary; otherwise, all data is sent.

[0086] Step S706: After the data transmission is completed, jump to the waiting for transmission completion state (WAIT_TR_EXPIRY).

[0087] Step S707: Determine if the address has reached the boundary (wr_pg_bndy = 1). If yes, jump to step S702 and start another write operation from the address after the boundary (steps S702 to S706). If no, it means that the address has not reached the boundary after the transmission is completed (twc_expired = 1). Jump to step S701 and return to the idle state.

[0088] The storage write operation can be achieved through the above steps S701 to S707.

[0089] Through the above steps S601 to S606, the read operation of the register module can be realized.

[0090] Figure 8 This is a flowchart illustrating the state machine's operation during a read operation in an embodiment of this disclosure. (See also...) Figure 8 For example, state machine 41a receives the transmission signal from the AP 8M interface.

[0091] Step S801: The state machine is in the idle state (IDLE).

[0092] In step S802, after the storage access request is valid (reg_xfer_valid=1), the process transitions from the idle state to the command sending state (SEND_CMD).

[0093] In step S803, within one clock cycle (cmd_cycle_cnt = 1), the state machine transitions from the command sending state to the address sending state (ADDR).

[0094] Step S804: After two clock cycles (wr_rd = 1, addr_cycle_cnt = 2), jump to the data read state (RD_DATA).

[0095] Step S805: Determine whether the data strobe clock (DQS_time_out = 1) has timed out. If yes, proceed to step S806; otherwise, proceed to step S808.

[0096] In step S806, the state machine transitions to the read error state (RD_ERROR). After waiting for a preset time period, it transitions to step S809.

[0097] In step S807, after the state machine reads the required address length (rd_done = 1), it jumps to the FIFO refresh state (FIFO_FLUSH) to avoid affecting the next read.

[0098] In step S808, after the FIFO refresh is completed (fifo_flush_done=1), it jumps to the waiting for transmission completion state (WAIT_TR_EXPIRY) and returns to the idle state after the read cycle is completed (trc_expired=1).

[0099] The storage read operation can be achieved through the above steps S801 to S808.

[0100] Figure 9 This is a flowchart illustrating the state machine's operation during the semi-sleep phase in an embodiment of this disclosure. See also... Figure 9 For example, state machine 41a receives the transmission signal from the AP 8M interface.

[0101] Step S901: The state machine is in the idle state (IDLE).

[0102] In step S902, when the semi-sleep access request is valid (hs_xfer_valid=1), the state machine transitions from the idle state to the send command state (SEND_CMD).

[0103] In step S903, within one clock cycle (cmd_cycle_cnt = 1), the state machine transitions from the command sending state to the address sending state (ADDR).

[0104] Step S904: After two clock cycles (wr_rd = 1, addr_cycle_cnt = 2), the system jumps to the transmit delay state (TX_LATENCY).

[0105] Step S905: After the timer satisfies the waiting clock cycle (wait_expired), the process jumps to the data transmission state (TX_DATA).

[0106] In step S906, the half-sleep data transmission is fixed at one clock cycle. After one clock cycle (wdata_avalid=0), the state machine jumps to the waiting transmission completion state (WAIT_TR_EXPIRY). After the transmission clock cycle is completed (twc_expired=1), it returns to the idle state.

[0107] Through the above steps S901 to S906, a semi-sleep operation can be achieved.

[0108] Figure 10 This is a flowchart illustrating the process of the state machine exiting semi-sleep mode in an embodiment of this disclosure. See also... Figure 10 The steps to exit a semi-sleep state include:

[0109] Step S1001: The state machine is in the idle state (IDLE).

[0110] Step S1002: When the exit semi-sleep command is valid (hs_exit_valid=1), jump from the idle state to the semi-sleep exit state (HS EXIT).

[0111] In step S1002, the half-sleep state is exited by pulling the chip select (CE) signal low. After the pull-low time is sufficient and the PSRAM exits the half-sleep state to the time when it can receive the next command (ce_low_expired=1, txhs_expired=1), it returns to the idle state.

[0112] It should be noted that the entry and exit operations for deep power-off are similar to those for semi-sleep, and the state machine processes are not described in detail here. It should also be noted that in this embodiment, semi-sleep and hybrid sleep are merely different ways of describing the same thing; the commands and state machine workflows are identical when performing the entry / exit operations.

[0113] Figure 11 This is a schematic diagram of a physical layer interface provided in an embodiment of this disclosure. (See also...) Figure 11The physical layer interface is used to generate memory interface signals and is compatible with different PSRAM interfaces, including but not limited to the AP8M / 4M and WB 8M / 4M interfaces. The AP 8M interface uses a single-ended clock, while the AP 4M and WB 8M / 4M interfaces use differential clocks. The AP 8M's DQS_DM has two functions: a data strobe clock during reads (DQS) and a data mask during writes (DM). The AP 4M includes both DQS and DM signals, and the DQS signal is also required during write operations. The WB8M / 4M interface's read / write data strobe signal (RWDS) is similar to the AP 8M interface's DQS_DM signal; during the command address phase of the serial input / output bus, the WB 8M / 4M interface determines whether additional delay is needed. The physical layer interface provided in this embodiment can output various related signals, which can then be connected as needed for each type of PSRAM.

[0114] The clock gating processing (SCLK_GATE_INST) module 21 is used to generate clock signals SCLK and SCLKN for PSRAM based on the phase shift memory controller clock and clock enable.

[0115] For example, the clock gating processing module 21 generates clock signals SCLK and SCLKN for the PSRAM based on the phase shift memory controller clock mem_clk_90 and the clock enable sclk_en. SCLKN and SCLK are a set of differential clocks, meaning they are completely complementary, and N represents the opposite of the clock signal SCLK.

[0116] The Data Input / Output Selection Processing (DQ_OUT_MUX_INST) module 22 is used to split the data input / output into two parts based on the high and low levels of the memory controller clock, such as the low byte and high byte of the data input / output.

[0117] For example, the data input / output selection processing module 22 splits the data input / output dq_out_ip[15:0] into two parts, data input / output dq_out[7:0], according to the high or low level of the storage controller clock mem_clk_0.

[0118] In some embodiments, after splitting the data input / output dq_out_ip[15:0], the data input / output dq_out[7:0] and the data input / output enable dq_oe_ip are processed through a tri-state gate to obtain a high-impedance state other than high level and low level.

[0119] The data mask output selection processing (DM_OUT_MUX_INST) module 23 is used to split the data mask into two parts, such as the low byte and high byte of the data mask, according to the high and low levels of the storage controller clock when the data mask output enable is enabled.

[0120] For example, the data mask output selection processing module 23 is used to split the data mask dm_ip[1:0] into a data mask DM for two clock cycles based on the data mask output enable dm_oe_ip when the storage controller clock mem_clk_0 is at a high or low level.

[0121] In some embodiments, DQS not only needs to be used as the DQ strobe, but also needs to be kept at 0 at certain stages of the OPI bus. Therefore, the data strobe clock output enable dqs_oe_ip is designed to be 2 bits wide.

[0122] The Data Strob Clock Output Selection Processing (DQS_OUT_MUX_INST) module 24 is used to generate a data strobe clock output dqs_out that is compatible with different PSRAM interfaces based on the clock signal, data mask, PSRAM type, and data strobe clock output enable.

[0123] In some embodiments, the data strobe clock output selection processing module 24 is used to generate a data strobe clock output dqs_out compatible with different PSRAM interfaces based on the clock signal SCLK, data mask DM, PSRAM type, and data strobe clock output enable dqs_oe_ip, wherein the data strobe clock output dqs_out includes the DQS_DM / RWDS signal.

[0124] For example, when dqs_oe_ip is 2, the dqs_out output by the data strobe clock output selection processing module 24 is 0; when dqs_oe_ip is 1 and psram_type is AP 4M, the dqs_out output by the data strobe clock output selection processing module 24 is SCLK; when dqs_oe_ip is 1 and psram_type is not AP 4M, the dqs_out output by the data strobe clock output selection processing module 24 is DM; when dqs_oe_ip is 0, the dqs_out output by the data strobe clock output selection processing module 24 is high impedance. This ensures that the data strobe clock data mask DQS_DM under the AP 4M interface does not have the function of DM.

[0125] The data gating clock gating processing (DQS_GATE_INST) module 25 is used to gate the input data gating clock data mask DQS_DM based on the data gating clock output enable dqs_oe_ip[1:0] to obtain the data gating clock input signal dqs_in. In some embodiments, during the non-data phase, dqs_in remains 0 to avoid interference with the sampling of the read data.

[0126] In some embodiments, because the DQS_DM of the WB 8M / 4M interface indicates whether additional delay is required during the OPI bus command address stage, the physical layer interface additionally outputs the data strobe clock initial value dqs_initial, which has not been processed by the data strobe clock gating processing module 25, and outputs dqs_initial to the digital controller.

[0127] The Data Gating Clock Selection Operation Completion Delay (DQS_MUXED_DELAY) module 26 is used to physically delay the data strobe clock input signal (dqs_in) so that the data returned by the PSRAM lags behind the data strobe clock, in order to meet the trigger setup time required for sampling.

[0128] In this embodiment of the disclosure, the data gating clock selection operation completion delay module 26 physically delays the data gating clock input signal (dqs_in), so that the data returned by the PSRAM lags behind the data gating clock, in order to meet the trigger setup time required for sampling, thereby ensuring successful sampling.

[0129] In some embodiments, because the data input / output returned by the PSRAM lags behind the data strobe clock (e.g., a few tenths of a nanosecond), and considering that the time the data input / output returned by the PSRAM lags behind the data strobe clock varies at different SCLK frequencies, the data strobe clock selection operation completion delay module 26 employs a multi-level delay.

[0130] In some embodiments, the data strobe clock selection operation completion delay module 26 includes a physical control register module, which is used to select the delay level, with each delay level corresponding to a different delay time.

[0131] For example, the number of delay stages can be selected via the physical control register module phy_ctrl_reg0, and each delay stage uses an input / output buffer (IOBUF). The chip select low active ce_n_ip can be directly used as the CE_N output.

[0132] The controller for pseudo-static random access memory (PSRAM) provided in this embodiment includes a digital controller and a physical layer interface. The digital controller generates PSRAM transfer signals adapted to the type of an eight-channel serial input / output interface based on an operation request, enabling the PSRAM transfer signals to be applicable to different PSRAM interfaces. The physical layer interface generates PSRAM interface signals adapted to the type of the PSRAM interface based on the PSRAM transfer signals. Since the PSRAM interface signals are generated according to the type of PSRAM interface, the generated PSRAM interface signals are compatible with different types of PSRAM interfaces and transmission protocols, allowing the controller to support different PSRAM chips and improving the flexibility of PSRAM chip selection.

[0133] This disclosure also provides a control method for a pseudo-static random access memory (PSRAM). This control method is based on a controller for PPSRAM provided in this disclosure. To save space, the controller for PPSRAM provided in this disclosure is cited in its entirety here.

[0134] Figure 12 A flowchart illustrating a control method for a pseudo-static random access memory (PSRAM) provided in this disclosure. See also... Figure 12 The control methods include:

[0135] Step S1201: Receive operation request.

[0136] Operation requests can be transmitted to the controller via the APB bus and AHB bus. These operation requests include, but are not limited to, storage read / write requests and register module access requests. For example, an operation request can be a read / write request or a read / write request from either the APB or AHB bus.

[0137] Step S1202: Generate a pseudo-static random access memory (PSRAM) transfer signal that is compatible with the type of the eight-channel serial input / output interface based on the operation request.

[0138] In some embodiments, the PSRAM transmission signals include transmission signals corresponding to each state in read / write commands, entering / exiting semi-sleep (hybrid sleep), and entering / exiting deep power-off operations.

[0139] Step S1203 is used to generate a PSRAM interface signal that is compatible with the type of PSRAM interface based on the PSRAM transmission signal.

[0140] The control method for pseudo-static random access memory (PSRAM) provided in this disclosure generates a PSRAM transmission signal adapted to the type of an eight-channel serial input / output interface based on an operation request, so that the PSRAM transmission signal is applicable to different PSRAM interfaces; and generates a PSRAM interface signal adapted to the type of PSRAM interface based on the PSRAM transmission signal. Since the PSRAM interface signal is generated according to the type of PSRAM interface, the generated PSRAM interface signal can be compatible with different types of PSRAM interfaces and transmission protocols, enabling the controller to support different PSRAM chips and improving the flexibility of PSRAM chip selection.

[0141] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0142] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A controller for a pseudo-static random access memory, characterized in that, The digital controller and a physical layer interface, an input end of the physical layer interface being connected with the digital controller, and an output end of the physical layer interface being connected with a pseudo-static random access memory (PSRAM) interface, wherein: The digital controller is configured to receive an operation request and generate a PSRAM transmission signal adapted to a type of an eight-way serial input / output interface based on the operation request; The physical layer interface is configured to generate a PSRAM interface signal adapted to a type of the PSRAM interface based on the PSRAM transmission signal; The operation request comprises an advanced peripheral bus (APB) operation request and an advanced high-performance bus (AHB) operation request; The digital controller comprises: a register module configured to generate an APB control signal and a timing parameter based on the received APB operation request, and to receive a transmission state signal and store the transmission state signal; an AHB slave control module configured to obtain AHB instruction information based on the APB control signal and the timing parameter in response to the received AHB operation request, and to transmit the transmission state information of the PSRAM received to an AHB master; a read / write transaction transmission module configured to generate the PSRAM transmission signal based on the APB control signal and the AHB instruction information, and to receive an operation request and a clock signal from the physical layer interface, sample the operation request based on the clock signal, and transmit a sampling result to the AHB slave control module.

2. The controller of claim 1, wherein, The read / write transaction transmission module comprises: a command processing module configured to perform edge detection on the received APB control signal, and output an APB control valid signal and an APB transmission signal; a receiving transmission module configured to perform cross-clock domain transmission based on data returned by the physical layer interface, output data of the physical layer interface when a preset condition is met, and output a timeout indication signal when a data strobe signal is determined to be timed out according to a timing parameter; a sending transmission module configured to generate the PSRAM transmission signal based on each transmission state when transmitting the APB control signal and the AHB instruction information.

3. The controller of claim 2, wherein, The sending transmission module comprises a data shift register module, and the data shift register module comprises a plurality of state machines, each of the state machines corresponding to a type of one of the eight-way serial input / output interfaces, and each of the state machines generating the PSRAM transmission signal based on each transmission state for the type of the eight-way serial input / output interface corresponding to the state machine.

4. The controller of claim 3, wherein, The sending transmission module further comprises: a timing check module configured to generate a first indication signal based on the timing parameter; a write boundary check module configured to output a second indication signal when a boundary of a storage page is reached based on a parameter of the storage page and a storage address; The data shift register module transmits the APB control signal and the AHB instruction information in response to the first indication signal and the second indication signal.

5. The controller of claim 1, wherein, The digital controller further comprises: a first synchronizer configured to perform cross-clock domain transmission of a timeout signal from a clock signal of the digital controller to a clock signal of the AHB. A second synchronizer is configured to perform cross-clock-domain transmission of the transmission completion signal from the clock signal of the digital controller to the clock signal of the APB.

6. The controller of claim 1, wherein, The APB operation request comprises one or more of an APB read request and an APB write request. The AHB operation request comprises one or more of an AHB read request and an AHB write request.

7. The controller of claim 1, wherein, The physical layer interface comprises: A clock gating processing module is configured to generate a clock signal SCLK and SCLKN for the PSRAM according to a phase shift storage controller clock and a clock enable; A data input / output selection processing module is configured to split the data input / output into two parts according to the high and low levels of the storage controller clock; A data mask output selection processing module is configured to split the data mask into two parts according to the data mask output enable at the high and low levels of the storage controller clock; A data strobe clock output selection processing module is configured to generate a data strobe clock output compatible with different PSRAM interfaces based on the clock signal, the data mask, the PSRAM type, and the data strobe clock output enable; A data strobe clock gating processing module is configured to gate the input data strobe clock data mask based on the data strobe clock output enable to obtain a data strobe clock input signal; A data strobe clock selection operation completion delay module is configured to physically delay the data strobe clock input signal so that the data returned by the PSRAM lags behind the data strobe clock.

8. The controller of claim 7, wherein, The data strobe clock selection operation completion delay module comprises a physical control register module configured to select a delay order, each delay order corresponding to a different delay time.

9. A control method for a controller for a pseudo-static random access memory according to any one of claims 1 to 8, characterized by, The method comprises: receiving an operation request; generating a pseudo-static random memory (PSRAM) transmission signal compatible with the type of the eight-way serial input / output interface based on the operation request; and generating a PSRAM interface signal compatible with the type of the PSRAM interface based on the PSRAM transmission signal.

10. The control method according to claim 9, characterized by The PSRAM transmission signal comprises transmission signals corresponding to respective transmission states of read / write commands, entering / exiting semi-sleep, and entering / exiting deep power-off operations.

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