Base chip, memory system, and semiconductor structure

Abstract

An embodiment of the present application provides a basic chip, a storage system, and a semiconductor structure. The basic chip is configured to receive first data and first encoded data during a write phase. The first encoded data is obtained by performing a first error correction code encoding process on the first data, and perform a second error correction code encoding process on the first sub-data to generate second encoded data. During the write phase, the basic chip transmits second data to the storage chip. The second data includes the first sub-data, the second sub-data, the first encoded data, and the second encoded data. Among them, the first sub-data and the second sub-data together constitute the first data. The basic chip is further configured to receive the second data from the storage chip during a read phase, perform a first error detection and correction process on the first sub-data and the second encoded data, and transmit third data during the read phase. The third data includes the second sub-data, the first encoded data, and the first sub-data after the first error detection and correction process.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular, to a basic chip, a storage system, and a semiconductor structure. Background Art

[0002] Semiconductor storage can be divided into non-volatile storage and volatile storage. As volatile storage, Dynamic Random Access Memory (DRAM) has advantages such as high storage density and fast read / write speed, and is widely used in various electronic systems.

[0003] As the manufacturing process of DRAM becomes more advanced and the storage density becomes higher, the stored data in DRAM may be incorrect, seriously affecting the performance of DRAM. Therefore, Error Checking and Correction (ECC) technology is usually adopted in DRAM to detect or correct errors in the stored data. Summary of the Invention

[0004] The embodiments of the present application provide a basic chip, a storage system, and a semiconductor structure, which are at least beneficial to solving the problem of tight area of the controller or the storage chip.

[0005] According to some embodiments of the present application, on the one hand, a basic chip applied to a storage system is provided, including: the basic chip is configured to receive first data and first encoded data in a write stage, the first encoded data is obtained by performing first error correction code encoding processing on the first data, and perform second error correction code encoding processing on first sub-data to generate second encoded data, and transmit second data to a storage chip in the write stage, the second data includes the first sub-data, second sub-data, the first encoded data, and the second encoded data, wherein the first sub-data and the second sub-data together constitute the first data; the basic chip is further configured to receive the second data from the storage chip in a read stage, perform first error detection and correction processing on the first sub-data and the second encoded data, and transmit third data in the read stage, the third data includes the second sub-data, the first encoded data, and the first sub-data after the first error detection and correction processing.

[0006] In addition, the base chip includes: a second encoding module configured to receive the first sub-data during the writing stage and perform second error correction code encoding processing to generate the second encoded data; a first error detection and correction module configured to receive the first sub-data and the second encoded data during the reading stage and perform the first error detection and correction processing.

[0007] In addition, the number of bits of the first sub-data is the same as that of the second sub-data.

[0008] In addition, the base chip is further configured to generate a first error detection flag signal during the first error detection and correction processing, and record the error conditions of the first sub-data and the second encoded data during transmission based on the first error detection flag signal.

[0009] In addition, the base chip further includes: a first storage buffer module configured to store the error conditions of the first sub-data and the second encoded data during transmission; a first command module that receives a first polling instruction and generates a first command signal and a first clock signal; the first storage buffer module is further configured to output a first characterization signal based on the first command signal and the first clock signal, and the first characterization signal characterizes the error conditions of the first sub-data and the second encoded data during transmission.

[0010] In addition, the first storage buffer module includes a first-in, first-out register.

[0011] In addition, the first error correction code encoding processing and the second error correction code encoding processing are performed using different encoding algorithms.

[0012] According to some embodiments of the present application, on the other hand, an embodiment of the present application further provides a storage system, including a controller, a base chip, and a storage chip; the controller is configured to perform a first error correction code encoding process on first data during a write phase to generate first encoded data, and transmit first sub-data, second sub-data, and the first encoded data to the base chip, wherein the first sub-data and the second sub-data together constitute the first data; the base chip is configured to receive the first data and the first encoded data during the write phase, perform a second error correction code encoding process on the first sub-data to generate second encoded data, transmit second data to the storage chip during the write phase, the second data including the first sub-data, the second sub-data, the first encoded data, and the second encoded data, receive the second data from the storage chip during a read phase, perform a first error detection and correction process on the first sub-data and the second encoded data, and transmit third data to the controller during the read phase, the third data including the second sub-data, the first encoded data, and the first sub-data after the first error detection and correction process; the storage chip is configured to receive the second data and store the second data during the write phase, and transmit the second data to the base chip during the read phase; the controller is further configured to receive the third data from the base chip during the read phase, perform a second error detection and correction process on the third data to obtain the first data after the second error detection and correction process.

[0013] In addition, the controller includes: a first encoding module configured to perform the first error correction code encoding process on the first data during the write phase to generate the first encoded data; a second error detection and correction module configured to receive the third data during the read phase and perform the second error detection and correction process on the third data.

[0014] In addition, the base chip includes: a second encoding module configured to receive the first sub-data and perform the second error correction code encoding process on the first sub-data to generate the second encoded data during the write phase; a first error detection and correction module configured to receive the first sub-data and the second encoded data and perform the first error detection and correction process during the read phase.

[0015] In addition, the number of data transmission channels between the controller and the base chip is M, and the number of data transmission channels between the base chip and the storage chip is N; where M and N are both positive integers greater than 1, and N is greater than M.

[0016] Optionally, the storage chip includes: a first storage module configured to store the first data; a second storage module configured to store the first encoded data; and a third storage module configured to store the second encoded data.

[0017] Optionally, the first error correction code encoding process and the second error detection and correction process are performed using a first compilation algorithm, the second error correction code encoding process and the first error detection and correction process are performed using a second compilation algorithm, and the first compilation algorithm is different from the second compilation algorithm.

[0018] In addition, the base chip is further configured to generate a first error detection flag signal during the first error detection and correction process, and record the error conditions of the first sub-data and the second encoded data during transmission based on the first error detection flag signal; the storage system further includes: a first register configured to store the error conditions of the first sub-data and the second encoded data during transmission.

[0019] In addition, the base chip includes: a first storage buffer module configured to store the error conditions of the first sub-data and the second encoded data during transmission; a first command module that receives a first polling instruction and generates a first command signal and a first clock signal; the first storage buffer module is further configured to output a first characterization signal to the first register based on the first command signal and the first clock signal, and the first characterization signal characterizes the error conditions of the first sub-data and the second encoded data during transmission.

[0020] In addition, the controller is further configured to generate a second error detection flag signal during the second error detection and correction process, and record the error conditions of the first data and the first encoded data during transmission based on the second error detection flag signal; the storage system further includes: a second register configured to store the error conditions of the first data and the first encoded data during transmission.

[0021] In addition, the controller includes: a second storage buffer module configured to store the first data and the error conditions during the transmission of the first encoded data; a second command module that receives a second polling instruction and generates a second command signal and a second clock signal; the second storage buffer module is further configured to output a second characterization signal to the second register based on the second command signal and the second clock signal, where the second characterization signal characterizes the error conditions of the first sub-data and the first encoded data during the transmission

[0022] According to some embodiments of the present application, on the other hand, an embodiment of the present application further provides a semiconductor structure, including: a carrier substrate; the above storage system, and both the controller and the base chip are located on the surface of the carrier substrate, and the storage chip is located on the surface of the base chip away from the carrier substrate.

[0023] The technical solution provided by the embodiment of the present application has the following advantages:

[0024] In the technical solution of the base chip provided by the embodiment of the present application, after receiving the first data and the first encoded data in the writing stage, the base chip can transmit both the first data, the first encoded data, and the second encoded data into the storage chip; in the reading stage, the first data, the first encoded data, and the second encoded data transmitted from the storage chip are transmitted to the base chip, and the base chip can perform a first error detection and correction process on the first sub-data and the second encoded data, and transmit the first sub-data after the first error detection and correction process to the controller, and the base chip also transmits the second sub-data and the first encoded data to the controller. That is to say, in the storage stage, the base chip can perform error detection and correction processing on some of the first data, that is, the base chip can share the encoding processing function and the error detection and correction function of the controller, which is beneficial to alleviating the problem of the tight chip area of the controller. In addition, compared with the scheme in which the base chip performs error detection and correction on all the first data, the base chip only performs error detection and correction on the first sub-data, which is beneficial to improving the data transmission efficiency. In addition, since some of the first data transmitted to the controller has been subjected to an error detection and correction process once, the accuracy of the first data after the error detection and correction process by the controller again is improved, which is beneficial to improving the performance of the storage system. Description of the Drawings

[0025] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplary illustrations do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the drawings in the drawings do not constitute a proportional limitation.

[0026] Figure 1 It is a structural schematic diagram of a semiconductor structure;

[0027] Figure 2 For Figure 1 The schematic diagram of data transmission in the provided semiconductor structure;

[0028] Figures 3 to 5 The schematic diagram of the structure of the base chip provided by the embodiment of the present application;

[0029] Figures 6 to 8 The schematic diagram of the structure of the storage system provided by the embodiment of the present application;

[0030] Figure 9 The schematic cross-sectional structure diagram of the semiconductor structure provided by the embodiment of the present application. Detailed implementation manners

[0031] Figure 1 It is a schematic diagram of the structure of a semiconductor structure, Figure 2 For Figure 1 The schematic diagram of data transmission in the provided semiconductor structure.

[0032] Referring to Figure 1 , the semiconductor structure may include: a substrate 11; a base die 12 and a processor 13 respectively located on the surface of the substrate 11; a plurality of core dies 14 are stacked on the base die 12, and the core die 14 may be a DRAM chip. Referring to Figure 2 , in the data transmission process of the semiconductor structure, it includes: in the writing stage, the controller 13 transmits data to the base die 12, and the base die 12 transmits the data into the core die 14. Before transmitting the data, the controller 13 may first perform error correction code encoding processing on the data; in the reading stage, the core die 14 transmits the data to the base die 12, and then the base die 12 transmits the data to the controller 13. The controller 13 receives the data and performs error correction code decoding processing to detect and correct errors in the data.

[0033] It is not difficult to find that in the above semiconductor structure, the base die 12 does not participate in the error detection and correction process, that is, there is no error correction code encoding function and corresponding error detection and correction function in the base die 12. It is necessary for the controller 13 or the core die 14 to complete the error detection and correction, which makes the chip areas of the controller 13 and the core die 14, where the chip area is already tight, even more tense. Therefore, the performance of the controller 13 and the core die 14 is affected, and further the storage performance of the entire semiconductor structure needs to be improved.

[0034] The present application provides a basic chip, a storage system, and a semiconductor structure. The basic chip has an error detection and correction function. To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present application, many technical details are provided to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0035] Figure 3 FIG. 4 is a first schematic structural diagram of the basic chip provided by the embodiment of the present application. Figure 4 FIG. 5 is a second schematic structural diagram of the basic chip provided by the embodiment of the present application. Figure 5 FIG. 6 is a third schematic structural diagram of the basic chip provided by the embodiment of the present application.

[0036] The basic chip provided by the embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0037] Referring to Figure 3 , the basic chip 100 is applied to a storage system. In the write stage, the basic chip 100 is configured to receive a first data data1 and a first encoded data ecc1. The first encoded data ecc1 is obtained by performing a first error correction code encoding process on the first data data1, and perform a second error correction code encoding process on a first sub-data d1 to generate a second encoded data ecc2. In the write stage, the basic chip 100 transmits a second data data2 to the storage chip. The second data data2 includes the first sub-data d1, a second sub-data d2, the first encoded data ecc1, and the second encoded data ecc2. The first sub-data d1 and the second sub-data d2 together constitute the first data data1. The basic chip 100 is further configured to receive the second data from the storage chip in the read stage, perform a first error detection and correction process on the first sub-data d1 and the second encoded data ecc2, and transmit a third data data3 in the read stage. The third data data3 includes the second sub-data d2, the first encoded data ecc1, and the first sub-data d1 after the first error detection and correction process.

[0038] In the embodiments of the present application, the basic chip 100 participates in error correction code encoding processing and error detection and correction processing during data transmission. Specifically, after receiving the first data data1 and the first encoded data ecc1 during the write stage, the basic chip 100 can transmit both the first data data1, the first encoded data ecc1, and the second encoded data ecc2 into the storage chip; during the read stage, the first data data1, the first encoded data ecc1, and the second encoded data ecc2 transmitted from the storage chip are transmitted to the basic chip 100. The basic chip can perform the first error detection and correction processing on the first sub-data d1 and the second encoded data ecc2, and transmit the first sub-data d1 after the first error detection and correction processing to the controller. Moreover, the basic chip 100 also transmits the second sub-data d2 and the first encoded data ecc1 to the controller. That is to say, during the storage stage, the basic chip 100 can perform error detection and correction processing on part of the first data data1, that is, the basic chip 100 can share the encoding processing function and the error detection and correction function of the controller, which is beneficial to alleviating the problem of the tight chip area of the controller, and can make full use of the relatively sufficient chip area of the basic chip 100. In addition, since part of the first data data1 transmitted to the controller has been subjected to error detection and correction processing once, the accuracy of the first data data1 after being subjected to error detection and correction processing again by the controller is improved, which is beneficial to improving the RAS performance of the storage system, that is, improving the reliability, availability, and serviceability of the storage system.

[0039] In addition, the basic chip 100 only performs ECC error detection and correction on part of the first data data1, so that the storage system can balance efficiency and accuracy, and at the same time alleviate the problem of tight chip area.

[0040] In some embodiments, the basic chip 100 can be connected between the first port A and the second port B. Among them, the first port A is connected to the data transmission port of the controller of the storage system, and the second port B is connected to the data transmission port of the storage chip of the storage system. It can be understood that the first port A and the second port B are general terms. The first port A includes multiple data transmission ports, and the second port B includes multiple data transmission ports. Among them, the number of data transmission ports is related to the number of data to be transmitted by the basic chip 100. For example, the number of data transmission ports can be the same as the number of data to be transmitted by the basic chip 100, and one data can be transmitted via one data transmission port.

[0041] Both the error correction code encoding process and the error detection and correction process are used to implement ECC error detection and correction, so as to detect and locate the errors occurring in the first data transmission process and correct the errors. In some embodiments, the ECC error detection and correction can adopt the error correction mechanism of Reed Solomon Code (RS), correspondingly, the error correction code encoding process can adopt the RS encoding algorithm to generate encoded data, and the decoding process in the error detection and correction process can adopt the RS decoding algorithm. In other embodiments, the ECC error detection and correction can adopt the error correction mechanism of Hamming Code, correspondingly, the error correction code encoding process can adopt the Hamming code encoding algorithm to generate encoded data, and the decoding process in the error detection and correction process can adopt the Hamming code decoding algorithm.

[0042] In some embodiments, the first data data1 can be data of 256 bits (bit), correspondingly, the first encoded data ecc1 can be data of 16 bits. It can be understood that in other embodiments, due to the difference in the specific encoding algorithm adopted by the first error correction code encoding process, the number of bits of the first encoded data can also be different accordingly. In addition, the number of bits of the first data data1 can also be other quantities, such as 128, 512, etc.

[0043] In some embodiments, the number of bits of the first sub-data d1 is the same as the number of bits of the second sub-data d2, that is, the number of bits of both the first sub-data d1 and the second sub-data d2 is half of the number of bits of the first data data1. The time required for the basic chip 100 to transmit the second sub-data d2 and the first encoded data ecc1 to the storage chip is the first duration, and the time required for the basic chip 100 to transmit the first sub-data d1 and the second encoded data ecc2 to the storage chip is the second duration. Since the number of bits of the first sub-data d1 is the same as that of the second sub-data d2, the first duration is close to the second duration, and even it can be considered that the first duration is the same as the second duration, thereby shortening the time difference required for the transmission paths of different data to the storage chip. Similarly, the time difference required for the transmission paths of different data read by the basic chip 100 from the storage chip in the reading stage is shortened, improving the storage performance of the storage system, such as improving the RAS performance of the storage system. It can be understood that the transmission paths of different data here mainly refer to the transmission paths of the first sub-data d1 and the second encoded data ecc2, and the transmission paths of the second sub-data d2 and the first encoded data ecc1.

[0044] Combined with the foregoing analysis, it is not difficult to find that in some embodiments, the number of bits of the first encoded data ecc1 and the number of bits of the second encoded data ecc2 may be the same, which is conducive to further shortening the data transmission time difference and further improving the storage performance of the storage system. For example, if the first data data1 is 256-bit data, then the first sub-data d1 is 128-bit data, the second sub-data d2 is 128-bit data, the first encoded data ecc1 is 16-bit data, and the second encoded data ecc2 is 16-bit data.

[0045] In other embodiments, the number of bits of the first sub-data and the number of bits of the second sub-data may also be different.

[0046] In some embodiments, the first error correction code encoding process and the second error correction code encoding process may adopt different encoding algorithms. Correspondingly, the decoding algorithms adopted by the first error detection and correction process and the second error detection and correction process performed by the controller are also different. The encoding algorithm and the corresponding decoding algorithm are collectively referred to as the compilation algorithm. In this way, using different compilation algorithms for error detection and correction is conducive to further improving the correct rate of data error correction, improving the data error detection and correction ability, improving the reliability and security, and reducing the difficulty for the basic chip 100 to identify different encoded data. For example, the first data data1 is 256-bit data, the first encoded data ecc1 is 16-bit data, the first sub-data d1 is 128-bit data, and the second encoded data ecc2 is also 16-bit data.

[0047] It should be noted that in other embodiments, the first error correction code encoding process and the second error correction code encoding process may also adopt the same encoding algorithm. In addition, the encoding algorithm adopted by the second error correction code encoding process corresponds to the decoding algorithm adopted by the first error detection and correction process.

[0048] Figure 4 This is the second structural schematic diagram of the basic chip provided by the embodiment of the present application. Refer to Figure 4 , in some embodiments, the basic chip 100 may include: a second encoding module 110, which is configured to receive the first sub-data d1 and perform a second error correction code encoding process during the writing stage to generate the second encoded data ecc2; a first error detection and correction module 120, which is configured to receive the first sub-data d1 and the second encoded data ecc2 and perform a first error detection and correction process during the reading stage.

[0049] The second encoding module 110 is connected between the data transmission port of the controller and the data transmission port of the storage chip, and the first sub-data d1 is transmitted to the second encoding module 110.

[0050] The first error detection and correction module 120 is connected between the data transmission port of the controller and the data transmission port of the storage chip. The first error detection and correction module 120 performs first error detection and correction processing on the first sub-data d1 and the second encoded data ecc2. Specifically, the paths where the first error detection and correction module 120 can detect data errors include: the transmission path from the second encoding module 110 to the storage chip, and the transmission path from the storage chip to the first error detection and correction module 120.

[0051] It should be noted that the "first", "second", and "third" in the embodiments of the present application are only for descriptive distinction, and there is no special limitation on the sequence of appearance of the corresponding features.

[0052] The following will be combined with Figure 4 to describe in detail the working principle of the basic chip 100:

[0053] In the writing stage, the first sub-data d1 in the first data data1 from the controller is transmitted to the second encoding module 110. The second encoding module 110 performs second error correction code encoding processing on the first sub-data d1 to generate the second encoded data ecc2. Then, the first sub-data d1 and the second encoded data ecc2 are written into the storage chip. In addition, the basic chip 100 also writes the second sub-data d2 and the first encoded data ecc1 into the storage chip. For example, the first data data1 is 256 bit, the first encoded data ecc1 is 16 bit, 128-bit first sub-data d1 is transmitted to the second encoding module 110 and the generated second encoded data ecc2 is 16 bit. The 128-bit first sub-data d1 and the 16-bit second encoded data ecc2 are stored in the storage chip, and the 128-bit second sub-data d2 and the 16-bit first encoded data ecc1 are also stored in the storage chip.

[0054] In the reading stage, the first sub-data d1 and the second encoded data ecc2 from the storage chip are read out and transmitted to the first error detection and correction module 120. The first error detection and correction module 120 performs the first error detection and correction process to obtain the first sub-data d1 after the first error detection and correction process, and the first sub-data d1 after the first error detection and correction process is transmitted to the controller. In addition, the base chip 100 also transmits the second sub-data d2 and the first encoded data ecc1 to the controller. For example, 256bit + 16bit + 16bit of data is read out from the storage chip. Among them, 128bit of the first sub-data d1 and 16bit of the second encoded data ecc2 are processed by the first error detection and correction module 120 for the first error detection and correction process, and then 128bit of the first sub-data d1 after the first error detection and correction process is output. The 128bit of the first sub-data d1 after the first error detection and correction process can be transmitted into the controller, and 128bit of the second sub-data d2 and the first encoded data ecc1 are also transmitted into the controller through the base chip 100, enabling the controller to perform the second error detection and correction process. It can be understood that the objects for which the controller performs error detection and correction include: the second sub-data d2, the first encoded data ecc1, and the first sub-data d1 after the first error detection process.

[0055] In this way, in the reading stage, the base chip 100 can perform the first error detection and correction process on the first sub-data d1 and the first encoded data ecc1, so that the first sub-data d1 transmitted back to the controller is the data after the error detection and correction process. That is to say, the accuracy rate of part of the first data data1 transmitted back to the controller is improved. Then, the controller performs the second error detection and correction process on the second sub-data d2, the first sub-data d1 after the first error detection and correction process, and the first encoded data ecc1, and obtains the first data data1 after the second error detection and correction process. The first data data1 after the second error detection and correction process will also have a high accuracy rate accordingly. Moreover, the base chip 100 only performs error detection and correction on the first sub-data d1, which is beneficial to ensuring the data transmission efficiency.

[0056] In summary, the base chip 100 is beneficial to improving the overall data error detection and correction accuracy rate of the storage system. In addition, the storage chip in the storage system does not need to have the encoding processing function and the error detection and correction function, and the base chip 100 can share the encoding processing function and the error detection and correction function required by the controller, thus being beneficial to improving the performance of the controller and the storage chip, and reasonably using the chip area of the base chip 100, which is beneficial to alleviating the chip area pressure of the controller and the storage chip, and further beneficial to improving the storage performance of the storage system.

[0057] In addition, in some embodiments, the base chip 100 may further be configured to generate a first error detection flag signal during the first error detection and correction process, and record the error conditions of the first sub-data d1 and the second encoded data ecc2 during the transmission process based on the first error detection flag signal. Specifically, if an error occurs in the first sub-data d1 or the second encoded data ecc2 during the transmission process, a first error detection flag signal is generated; if no error occurs in the first sub-data d1 and the second encoded data ecc2 during the transmission process, the first error detection flag signal is not generated. In addition, in some embodiments, the first error detection flag signal may be defined as: if an error occurs in the first sub-data d1 or the second encoded data ecc2 during the transmission process, the first error detection flag signal is 1; if no error occurs in the first sub-data d1 and the second encoded data ecc2 during the transmission process, the first error detection flag signal is 0. In other embodiments, the first error detection flag signal may also be defined as: if an error occurs in the first sub-data d1 or the second encoded data ecc2 during the transmission process, the first error detection flag signal is 0; if no error occurs in the first sub-data d1 and the second encoded data ecc2 during the transmission process, the first error detection flag signal is 1.

[0058] Through the first error detection flag signal, it is possible to obtain whether an error occurs in the first sub-data d1 or the second encoded data ecc2 in the data transmission path from the controller to the base chip 100 during the write phase, and it is also possible to obtain whether an error occurs in the first sub-data d1 or the second encoded data ecc2 in the data transmission path from the storage chip to the base chip during the read phase.

[0059] As Figure 5 shown, Figure 5 FIG. 3 is a schematic diagram of a third structure of the base chip provided by an embodiment of the present application. In some embodiments, the base chip 100 may further include: a first storage buffer module 101 configured to store the error conditions of the first sub-data d1 and the second encoded data ecc2 during the transmission process; a first command module 102 that receives a first polling instruction PS1 and generates a first command signal CMD1 and a first clock signal CLK1; the first storage buffer module 101 is further configured to output a first characterization signal flag1 based on the first command signal CMD1 and the first clock signal CLK1, and the first characterization signal flag1 characterizes the error conditions of the first sub-data d1 and the second encoded data ecc2 during the transmission process.

[0060] In addition, in the case where the first polling instruction PS1 is not received, the first storage buffer module 101 only stores the error conditions of the first sub-data d1 and the second encoded data ecc2 during the transmission process; after the first command module 102 receives the first polling instruction PS1, it controls the first storage buffer module 101 to output a first representation signal flag1 indicating the error conditions of the first sub-data d1 or the second encoded data ecc2 during the transmission process. Based on this first representation signal flag1, the error conditions of the first sub-data d1 and the second encoded data ecc2 can be obtained.

[0061] In some embodiments, the first representation signal flag1 may be a binary string of numbers. For example, if an error is detected in the first sub-data d1 or the second encoded data ecc2 during the transmission process, 1 is recorded; if no error is detected in the first sub-data d1 and the second encoded data ecc2 during the transmission process, 0 is recorded. Thus, after a period of time, the first representation signal flag1 is a binary string composed of 0 and 1. In other embodiments, the first representation signal flag1 may also be a decimal value. For example, the first storage buffer module 101 may be a counter, and if an error is detected in the first sub-data d1 or the second encoded data ecc2 during the transmission process, it is incremented by 1. Thus, after a period of time, the first representation signal flag1 is a decimal value related to the number of errors.

[0062] In some embodiments, the first storage buffer module 101 may be a first-in, first-out (FIFO, First Input First Output) register. Using a first-in, first-out register as the first storage buffer module 101 can cache continuous data streams to prevent data loss during storage operations; in addition, the error conditions of the first sub-data d1 and the second encoded data ecc2 during the transmission process are centralized for stacking and storage, which can avoid frequent bus operations and is beneficial to improving the data transmission speed.

[0063] In addition, in some embodiments, the first clock signal CLK1 may be independently generated by the first command module 102; in other embodiments, the first clock signal CLK1 may also be externally provided, such as being generated by the controller that generates the first polling instruction PS1.

[0064] The basic chip 100 provided in the above embodiments not only has the function of data transmission, but also has the functions of error correction code encoding processing and error detection and correction processing. Thus, the chip area of the basic chip 100 can be effectively utilized, reducing the chip area pressure on the controller and the storage chip, and saving the chip area of the controller and the storage chip.

[0065] Moreover, since the base chip 100 can perform second error correction code encoding processing on the first sub-data d1 to obtain the second encoded data ecc2, and can transmit the second encoded data ecc2, the first encoded data ecc1, and the first data data1 to the storage chip, facilitating the first error detection and correction processing of the first sub-data d1 based on the second encoded data ecc2 during the reading stage, it can detect whether errors occur in the first sub-data d1 and the second encoded data ecc2 during the writing stage or the reading stage and correct the errors. Moreover, the second sub-data, the first encoded data ecc1, and the first sub-data d1 after the first error detection and correction processing can be transmitted to the controller, so that the controller can perform error detection and correction processing again, thereby improving the error detection and correction ability of the storage system and enhancing the error detection and correction accuracy rate of the data.

[0066] Another embodiment of the present application further provides a storage system, which includes a controller, a storage chip, and a base chip as provided in the foregoing embodiment. The storage system provided in another embodiment of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those in the foregoing embodiment, reference may be made to the detailed description of the foregoing embodiment, which will not be repeated hereinafter.

[0067] Figure 6 It is the first structural schematic diagram of the storage system provided in the embodiment of the present application.

[0068] Refer to Figure 6, the storage system includes: a basic chip 200, a controller 300, and a storage chip 400; the controller 300 is configured to perform a first error correction code encoding process on the first data data1 during the write phase to generate first encoded data ecc1, and transmit a first sub-data d1, a second sub-data d2, and the first encoded data ecc1 to the basic chip 200, wherein the first sub-data d1 and the second sub-data d2 together constitute the first data data1; the basic chip 200 is configured to receive the first data data1 and the first encoded data ecc1 during the write phase, perform a second error correction code encoding process on the first sub-data d1 to generate second encoded data ecc2, transmit a second data data2 to the storage chip 400 during the write phase, the second data data2 includes the first sub-data d1, the second sub-data d2, the first encoded data ecc1, and the second encoded data ecc2, receive the second data data2 from the storage chip 400 during the read phase, perform a first error detection and correction process on the first sub-data d1 and the second encoded data ecc2, and transmit a third data data3 to the controller 300 during the read phase, the third data data3 includes the second sub-data d2, the first encoded data ecc1, and the first sub-data d1 after the first error detection and correction process; the storage chip 400 is configured to receive the second data data2 and store the second data data2 during the write phase, and transmit the second data data2 to the basic chip 200 during the read phase; the controller 300 is further configured to receive the third data data3 from the basic chip 200 during the read phase, perform a second error detection and correction process on the third data data3, and obtain the first data data1 after the second error detection and correction process.

[0069] In the above storage system, the error correction code encoding process and the error detection and correction process performed on the data can both be implemented by the basic chip 200. Thus, the storage chip 400 does not need to perform the encoding process and the error detection and correction process, and the basic chip 200 can share the encoding process and the error detection and correction process required by the controller 300, so that the functions required by the controller 300 and the storage chip 400 are relatively reduced. Therefore, the pressure of the tight chip area of the controller 300 and the storage chip 400 can be alleviated, so as to better improve the performance of the controller 300 and the storage chip 400. For example, the reliability of the storage chip 400 can be improved, thereby improving the storage performance of the storage system. Moreover, the basic chip 200 can perform a first error detection and correction process on the first sub-data d1 in the first data data1, and the controller 300 can perform a second error detection and correction process on the second sub-data d2. The controller 300 can also perform a second error detection and correction process on the first sub-data d1 that has undergone a first error detection and correction process, which is beneficial to improving the error detection and correction accuracy rate of the data.

[0070] Both the base chip 200 and the controller 300 are capable of performing error detection and correction processing on the first data, which is beneficial to improving the data error detection and correction ability of the storage system.

[0071] In some embodiments, the storage system may be a DRAM storage system, such as a DDR (double data rate) 4 DRAM storage system or a DDR5 DRAM storage system. In other embodiments, the storage system may also be an SRAM (Static Random-Access Memory) storage system, a NAND storage system, a NOR storage system, a FeRAM storage system, or a PcRAM storage system.

[0072] The controller 300 may include: a first encoding module 301 configured to perform a first error correction code encoding process on the first data data1 during the write phase to generate first encoded data ecc1; a second error detection and correction module 302 configured to receive the third data data3 and perform a second error detection and correction process during the read phase.

[0073] The base chip 200 can provide a high-speed interface for data transmission in the storage system. In addition, the base chip 200 is also used to manage and control the storage chip 400. In some embodiments, the base chip 200 can be used to monitor and manage the temperature of the storage chip 400, and can also be used to perform Memory Build-In-Self Test (MBIST) and self-repair on the storage chip 400. In addition, the base chip 200 is also used to perform error detection and correction on the transmitted data.

[0074] Figure 7 This is the second structural schematic diagram of the storage system provided by the embodiments of the present application. Refer to Figure 7 In some embodiments, the base chip 200 may include: a second encoding module 210 configured to receive the first sub-data d1 and perform a second error correction code encoding process during the write phase to generate second encoded data ecc2; a first error detection and correction module 220 configured to receive the first sub-data d1 and the second encoded data ecc2 and perform a first error detection and correction process during the read phase.

[0075] Regarding the working principle of the storage system, reference may be made to the corresponding descriptions of the foregoing embodiments, which will not be elaborated here. It can be understood that the controller 300 can perform a second error detection and correction process on the second sub-data d2 and the first sub-data d1 after the first error detection and correction process.

[0076] The first error correction code encoding process and the second error detection and correction process are performed using the first compilation algorithm, and the second error correction code encoding process and the first error detection and correction process are performed using the second compilation algorithm. In some embodiments, the first compilation algorithm and the second compilation algorithm may be different. Using different compilation algorithms for error detection and correction of data is beneficial to further improve the accuracy of error detection and correction of data, and increase reliability and security.

[0077] Specifically, the encoding algorithms used by the second encoding module 210 and the first encoding module 301 may be different, and the decoding algorithms used by the first error detection and correction module 220 and the second error detection and correction module 302 may be different.

[0078] It should be noted that in some other embodiments, the first compilation algorithm and the second compilation algorithm may also be the same.

[0079] Reference Figure 7 , the storage chip 400 may include: a first storage module 410, the first storage module 410 is used to store the first data data1, that is, the first storage module 410 is used to store the first sub-data d1 and the second sub-data d2; a second storage module 420, the second storage module 420 is used to store the first encoded data ecc1; a third storage module 430, the third storage module 430 is used to store the second encoded data ecc3. For example, the first storage module 410 may store 256-bit first data (i.e., the first sub-data d1 and the second sub-data d2), the second storage module 420 may store 16-bit first encoded data ecc1, and the third storage module 430 stores 16-bit second encoded data ecc2.

[0080] It can be understood that the number of data transmission channels between the controller 300 and the base chip 200 is M, and the number of data transmission channels between the base chip 200 and the storage chip 400 is N. Both M and N are positive integers greater than 1, and N is greater than M. This is because, in addition to transmitting the first data data1 and the first encoded data ecc1 between the base chip 200 and the storage chip 400, it is also necessary to transmit the second encoded data ecc2.

[0081] Reference Figure 8 , Figure 8 For Figure 7Schematic diagram of the basic structure. In some embodiments, the basic chip 200 is further configured to generate a first error detection flag signal during the first error detection and correction process, and record the error conditions of the first sub-data d1 and the second encoded data ecc2 during the transmission process based on the first error detection flag signal; the storage system further includes: a first register 501, and the first register 501 is configured to store the error conditions of the first sub-data d1 and the second encoded data ecc2 during the transmission process.

[0082] Specifically, referring to Figure 8 , the basic chip 200 may include: a first storage buffer module 201, and the first storage buffer module 201 is configured to store the error conditions of the first sub-data d1 and the second encoded data ecc2 during the transmission process; a first command module 202, and the first command module 202 receives the first polling instruction PS1 and generates a first command signal CMD1 and a first clock signal CLK1; the first storage buffer module 201 is further configured to output a first characterization signal flag1 to the first register 501 based on the first command signal CMD1 and the first clock signal CLK1, and the first characterization signal flag1 characterizes the error conditions of the first sub-data d1 and the second encoded data ecc2 during the transmission process.

[0083] In some embodiments, the controller 300 may also be configured to issue the first polling instruction PS1 to the first command module 202, that is, the controller 300 periodically issues an inquiry to control the first storage buffer module 201 to output the first characterization signal flag1 to the first register 501. It can be understood that in other embodiments, the first polling instruction may also be provided by an external circuit.

[0084] Referring to Figure 8 , in some embodiments, the controller 300 may also be configured to generate a second error detection flag signal during the second error detection and correction process, and record the error conditions of the first data data1 and the first encoded data ecc1 during the transmission process based on the second error detection flag signal; the storage system may further include: a second register 502, and the second register 502 is configured to store the error conditions of the first data data1 and the first encoded data ecc1 during the transmission process. It should be noted that the first data data1 for which the controller 300 performs the second error detection and correction process refers to the second sub-data d2 and the first sub-data d1 that has undergone the first error detection and correction process.

[0085] Referring to Figure 8, in some embodiments, the controller 300 may further include: a second storage buffer module 271 configured to store the error conditions of the first data data1 and the first encoded data ecc1 during transmission; a second command module 281 that receives a second polling instruction PS2 and generates a second command signal CMD2 and a second clock signal CLK2; the second storage buffer module 271 is further configured to output a second characterization signal flag2 to the second register 502 based on the second command signal CMD2 and the second clock signal CLK2, where the second characterization signal flag2 characterizes the error conditions of the first data data1 and the first encoded data ecc1 during transmission.

[0086] It can be understood that the first register 501 and the second register 502 may be the same register.

[0087] In the storage system provided by the above embodiments, the base chip 200 can implement error detection and correction functions. Correspondingly, the storage chip 400 does not need to have error detection and correction functions, and the base chip 200 can share the error detection and correction functions originally borne by the controller 300. Therefore, it is beneficial to save the space area of the controller 300 and the storage chip 400, improve the storage performance of the storage chip 400, and thus improve the storage performance of the storage system. At the same time, both the base chip 200 and the controller 300 can perform error detection and correction processing on the first data. Some of the first data data1 undergoes two error detection and correction processes. Therefore, the data error detection and correction accuracy rate of the storage system is high, and it is beneficial to improve the RAS performance of the storage system, that is, to improve the reliability, availability, and serviceability of the storage system.

[0088] In addition, the settings of the first error detection and correction module 220 and the second error detection and correction module 302 enable error detection and correction to be performed on different data transmission paths, improve the error detection and correction ability of the storage system, and are beneficial to locating the specific data transmission path where the error occurs.

[0089] Correspondingly, the embodiments of the present application also provide a semiconductor structure, which may include the storage system provided by the above embodiments. The semiconductor structure provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those in the foregoing embodiments, reference may be made to the detailed description of the foregoing embodiments, and details will not be repeated below.

[0090] Figure 9 It is a schematic cross-sectional structure diagram of the semiconductor structure provided by the embodiments of the present application.

[0091] Refer to Figure 9, the semiconductor structure includes: a carrier substrate 600; the storage system provided in the foregoing embodiment, and both the controller 300 and the base chip 200 are located on the surface of the carrier substrate 600, and the storage chip 400 is located on the surface of the base chip 200 away from the carrier substrate 600.

[0092] Among them, the semiconductor structure may include a plurality of storage chips 400 stacked in sequence. The semiconductor structure may be a memory such as a DRAM device or an SRAM device.

[0093] In some embodiments, the carrier substrate 600 may be a PCB (Printed Circuit Board). For a detailed description of the storage system, reference may be made to the foregoing embodiment, and details are not described herein again.

[0094] The semiconductor structure may be a 2.5D (dimensions) device, that is, the semiconductor structure is a stacked structure, which is beneficial to saving the size in the horizontal direction, and the ECC error detection and correction function is realized by using the base chip 200 in the semiconductor structure, which is beneficial to improving the performance of the semiconductor structure.

[0095] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present application. In practical applications, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A basic chip is applied to a storage system. It is characterized in that it includes: The basic chip is configured to receive first data and first encoded data during a write phase. The first encoded data is obtained by performing first error correction code encoding processing on the first data, and perform second error correction code encoding processing on first sub-data to generate second encoded data. During the write phase, transmit second data to the storage chip. The second data includes the first sub-data, second sub-data, the first encoded data, and the second encoded data. Among them, the first sub-data and the second sub-data together constitute the first data. The basic chip is further configured to receive the second data from the storage chip during a read phase, perform first error detection and correction processing on the first sub-data and the second encoded data, and transmit third data during the read phase. The third data includes the second sub-data, the first encoded data, and the first sub-data after the first error detection and correction processing.

2. The basic chip according to claim 1, It is characterized in that the basic chip includes: A second encoding module, which is configured to receive the first sub-data during the write phase and perform the second error correction code encoding processing to generate the second encoded data. A first error detection and correction module, which is configured to receive the first sub-data and the second encoded data during the read phase and perform the first error detection and correction processing.

3. The basic chip according to claim 1, It is characterized in that the number of bits of the first sub-data is the same as that of the second sub-data.

4. The basic chip according to claim 1, It is characterized in that the basic chip is further configured to generate a first error detection flag signal during the first error detection and correction processing, and record the error conditions of the first sub-data and the second encoded data during the transmission process based on the first error detection flag signal.

5. The basic chip according to claim 4, It is characterized in that the basic chip further includes: A first storage cache module, which is configured to store the error conditions of the first sub-data and the second encoded data during the transmission process. A first command module, which receives a first polling instruction and generates a first command signal and a first clock signal. The first storage cache module is further configured to output a first characterization signal based on the first command signal and the first clock signal. The first characterization signal characterizes the error conditions of the first sub-data and the second encoded data during the transmission process.

6. The basic chip according to claim 5, It is characterized in that the first storage cache module includes a first-in, first-out register.

7. The basic chip according to claim 1, It is characterized in that the first error correction code encoding processing and the second error correction code encoding processing are performed using different encoding algorithms.

8. A storage system, It is characterized in that it includes a controller, a basic chip, and a storage chip, and further includes: The controller is configured to perform a first error correction code encoding process on the first data during the write phase to generate first encoded data, and transmit first sub-data, second sub-data, and the first encoded data to the base chip, where the first sub-data and the second sub-data together constitute the first data; The base chip is configured to receive the first data and the first encoded data during the write phase, perform a second error correction code encoding process on the first sub-data to generate second encoded data, transmit second data to the storage chip during the write phase, the second data including the first sub-data, the second sub-data, the first encoded data, and the second encoded data, receive the second data from the storage chip during the read phase, perform a first error detection and correction process on the first sub-data and the second encoded data, and transmit third data to the controller during the read phase, the third data including the second sub-data, the first encoded data, and the first sub-data after the first error detection and correction process; The storage chip is configured to receive the second data and store the second data during the write phase, and transmit the second data to the base chip during the read phase; The controller is further configured to receive the third data from the base chip during the read phase, perform a second error detection and correction process on the third data to obtain the first data after the second error detection and correction process.

9. The storage system according to claim 8, wherein, the controller includes: a first encoding module configured to perform the first error correction code encoding process on the first data during the write phase to generate the first encoded data; a second error detection and correction module configured to receive the third data during the read phase and perform the second error detection and correction process on the third data.

10. The storage system according to claim 8, wherein, the base chip includes: a second encoding module configured to receive the first sub-data and perform the second error correction code encoding process to generate the second encoded data during the write phase; a first error detection and correction module configured to receive the first sub-data and the second encoded data and perform the first error detection and correction process during the read phase.

11. The storage system according to claim 8, wherein, the number of data transmission channels between the controller and the base chip is M, and the number of data transmission channels between the base chip and the storage chip is N; wherein, both M and N are positive integers greater than 1, and N is greater than M.

12. The storage system according to claim 8, wherein, the storage chip includes: a first storage module for storing the first data; a second storage module for storing the first encoded data; A third storage module, which is used to store the second encoded data.

13. The storage system according to claim 8, wherein, the first error correction code encoding process and the second error detection and correction process are performed using a first compilation algorithm, the second error correction code encoding process and the first error detection and correction process are performed using a second compilation algorithm, and the first compilation algorithm is different from the second compilation algorithm.

14. The storage system according to claim 8, wherein, the base chip is further configured to generate a first error detection flag signal during the first error detection and correction process, and record the error conditions of the first sub-data and the second encoded data during transmission based on the first error detection flag signal; the storage system further includes: a first register, which is configured to store the error conditions of the first sub-data and the second encoded data during transmission.

15. The storage system according to claim 14, wherein, the base chip includes: a first storage cache module, which is configured to store the error conditions of the first sub-data and the second encoded data during transmission; a first command module, which receives a first polling instruction and generates a first command signal and a first clock signal; the first storage cache module is further configured to output a first characterization signal to the first register based on the first command signal and the first clock signal, and the first characterization signal characterizes the error conditions of the first sub-data and the second encoded data during transmission.

16. The storage system according to claim 8, wherein, the controller is further configured to generate a second error detection flag signal during the second error detection and correction process, and record the error conditions of the first data and the first encoded data during transmission based on the second error detection flag signal; the storage system further includes: a second register, which is configured to store the error conditions of the first data and the first encoded data during transmission.

17. The storage system according to claim 16, wherein, the controller includes: a second storage cache module, which is configured to store the error conditions of the first data and the first encoded data during transmission; a second command module, which receives a second polling instruction and generates a second command signal and a second clock signal; the second storage cache module is further configured to output a second characterization signal to the second register based on the second command signal and the second clock signal, and the second characterization signal characterizes the error conditions of the first data and the first encoded data during transmission.

18. A semiconductor structure, wherein, it includes: a carrier substrate; The storage system according to any one of claims 8-17, wherein the controller and the base chip are both located on the surface of the carrier substrate, and the storage chip is located on the surface of the base chip away from the carrier substrate.

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