Semiconductor structure and method of manufacturing the same

Abstract

A semiconductor structure includes a substrate, a conductive layer, and a semiconductor component. The substrate includes a first surface, a second surface opposite to the first surface, at least one insulating cavity extending from the first surface to the second surface, and a through-hole penetrating the substrate. The conductive layer fills the through-hole. The semiconductor component is disposed on the second surface, and the semiconductor component is electrically connected to the conductive layer, wherein the at least one insulating cavity corresponds to the semiconductor component.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for manufacturing the same, and more particularly to a semiconductor structure and a method for manufacturing the same that can reduce the high-frequency coupling effect of semiconductor components. Background Technology

[0002] High electron mobility transistors (HEMTs), also known as modulation-doped field-effect transistors (MODFETs), are a type of field-effect transistor. Unlike metal-oxide-semiconductor (MOS) field-effect transistors, which directly use doped semiconductors to form channels, HEMTs use two materials with different band gaps to form a heterojunction to provide channels for carriers. Ternary compound semiconductors such as gallium arsenide (GaAs) and aluminum gallium arsenide (AlGaAs) are commonly used materials for HEMTs. In recent years, gallium nitride (GaN) HEMTs have attracted considerable attention due to their excellent high-frequency characteristics. HEMTs can operate at high frequencies, and therefore have been widely used in mobile phones, satellite television, and radar. However, HEMTs often face problems such as performance degradation caused by high-frequency coupling effects. Summary of the Invention

[0003] This invention provides a semiconductor structure with semiconductor components and a method for manufacturing the same, in order to reduce the high-frequency coupling effect of the semiconductor components in the semiconductor structure.

[0004] This invention provides a semiconductor structure including a substrate, a conductive layer, and a semiconductor component. The substrate includes a first surface, a second surface opposite to the first surface, at least one insulating cavity extending from the first surface to the second surface, and a via through the substrate. The conductive layer fills the via. The semiconductor component is disposed on the second surface and electrically connected to the conductive layer, wherein the at least one insulating cavity corresponds to the distribution of the semiconductor component.

[0005] In one embodiment of the present invention, the semiconductor component includes a transistor, the source of which is grounded through a conductive layer, and at least one insulating cavity is located below the channel layer of the transistor to reduce high-frequency coupling effects of the channel layer. In one embodiment of the present invention, the source is in contact with the top surface of the conductive layer via a contact plug, and the area of ​​the top surface of the conductive layer is greater than or equal to the area of ​​the contact plug. In one embodiment of the present invention, the source is electrically connected to the conductive layer via a contact plug, and the bottom surface of the contact plug is in contact with the top surface of the conductive layer. In one embodiment of the present invention, at least one insulating cavity extends from a first surface to a second surface to penetrate the substrate. In one embodiment of the present invention, the width of a via is less than or equal to the width of at least one insulating cavity. In one embodiment of the present invention, the width of the via is greater than the width of at least one insulating cavity, and the depth of at least one insulating cavity is less than the thickness of the substrate. In one embodiment of the present invention, the semiconductor structure further includes a substrate, wherein the substrate is at least located between the substrate and the conductive layer. In one embodiment of the present invention, the semiconductor structure further includes a supporting substrate, wherein the conductive layer is bonded to the supporting substrate.

[0006] This invention provides a method for manufacturing a semiconductor structure, comprising the following steps: providing a substrate, the substrate including a first surface and a second surface opposite to the first surface; forming a semiconductor component on the second surface of the substrate; forming at least one insulating cavity and a via through the substrate in the substrate, wherein the insulating cavity extends from the first surface to the second surface and at least one insulating cavity penetrates the substrate; forming a conductive layer within the via, wherein the semiconductor component is electrically connected to the conductive layer, and at least one insulating cavity corresponds to the distribution of the semiconductor component. In one embodiment of the invention, the at least one insulating cavity and the via are formed after the semiconductor component is formed. In one embodiment of the invention, the method for manufacturing the semiconductor structure further includes bonding the substrate on which the semiconductor component is formed to a carrier substrate, such that the semiconductor component is positioned between the substrate and the carrier substrate. In one embodiment of the invention, the at least one insulating cavity and the via are formed simultaneously in the substrate. In one embodiment of the invention, the at least one insulating cavity extends from the first surface to the second surface to penetrate the substrate, and the width of the via is less than or equal to the width of the at least one insulating cavity. In one embodiment of the invention, the width of the via is greater than the width of the at least one insulating cavity, and the depth of the at least one insulating cavity is less than the thickness of the substrate. In one embodiment of the present invention, the method of manufacturing a semiconductor structure further includes forming a liner, wherein the liner is at least located between a substrate and a conductive layer. In one embodiment of the present invention, the method of manufacturing a semiconductor structure further includes providing a support substrate and bonding the conductive layer to the support substrate.

[0007] Based on the above, embodiments of the present invention can effectively reduce the high-frequency coupling effect of semiconductor devices by forming insulating cavities in the substrate, thereby improving the performance of semiconductor devices. Furthermore, embodiments of the present invention can fabricate insulating cavities and vias in the same process step, improving the performance of semiconductor devices without significantly increasing process costs.

[0008] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention. Attached Figure Description

[0009] Figures 1 to 6 This is a cross-sectional schematic diagram of a semiconductor structure manufactured according to an embodiment of the present invention.

[0010] Figure 7 and Figure 8 These are cross-sectional and perspective views of a semiconductor structure according to embodiments of the present invention.

[0011] Figure 9 and Figure 10 Cross-sectional schematic diagrams of the substrate, conductive layer, and contact plug in the semiconductor structure are shown respectively.

[0012] Figures 11 to 18 This is a cross-sectional schematic diagram of a semiconductor structure according to different embodiments of the present invention. Detailed Implementation

[0013] The structural and working principles of the present invention will be described in detail below with reference to the accompanying drawings:

[0014] Figures 1 to 6 This is a cross-sectional schematic diagram of a semiconductor structure manufactured according to an embodiment of the present invention, and Figure 7 and Figure 8 These are cross-sectional and perspective views of a semiconductor structure according to embodiments of the present invention.

[0015] Please refer to Figure 1A substrate 100 is provided, having a first surface 100A and a second surface 100B (e.g., a top surface) opposite the first surface 100A (e.g., a bottom surface). In some embodiments, the substrate 100 is made of silicon or other suitable semiconductor materials. A semiconductor component 102 is formed on the second surface 100B of the substrate 100. A bonding dielectric layer 104 is then formed on the second surface 100B of the substrate 100 to cover the semiconductor component 102. A carrier substrate 106 is provided, and the substrate 100 with the semiconductor component 102 and the bonding dielectric layer 104 formed thereon is bonded to the carrier substrate 106 such that the semiconductor component 102 and the bonding dielectric layer 104 are located between the substrate 100 and the carrier substrate 106. In some embodiments, the bonding dielectric layer 104 is made of silicon oxide or other suitable dielectric materials. In this embodiment, the bonding dielectric layer 104 formed on the substrate 100 is directly bonded to the carrier substrate 106, so that the semiconductor component 102 and the bonding dielectric layer 104 are located between the substrate 100 and the carrier substrate 106. In some embodiments, the carrier substrate 106 is made of silicon, glass or other suitable semiconductor materials.

[0016] In this embodiment, the semiconductor component 102 includes a transistor. The transistor includes a gate 102G, a gate insulating layer 102GI, a source 102S, a drain 102D, and a channel layer 102C. The gate 102G, source 102S, and drain 102D are located above the channel layer 102C, and the gate 102G and the channel layer 102C are separated by the gate insulating layer 102GI. The source 102S and drain 102D are located on opposite sides of the gate 102G, and ohmic contacts are formed between the source 102S and the channel layer 102C, and between the drain 102D and the channel layer 102C, respectively. In other embodiments, the gate insulating layer 102GI may not be included in the transistor; in other words, the gate insulating layer 102GI in the transistor is a selective component. In some embodiments, the transistor is formed on a substrate 100 having a buffer compound semiconductor layer 110, and the buffer compound semiconductor layer 110 is formed on a second surface 100B of the substrate 100. In some embodiments, the transistor may further include at least one protective layer 112, wherein the protective layer 112 covers the gate 102G, the source 102S, and the drain 102. In some embodiments, the semiconductor component 102 includes a high electron mobility transistor (HEMT), and the channel layer 102C in the HEMT is made of GaN, AlGaN, InGaN, or other suitable semiconductor materials, while the buffer compound semiconductor layer 110 is made of GaN, AlGaN, InGaN, or other suitable semiconductor materials, and the materials of the channel layer 102C and the buffer compound semiconductor layer 110 may be the same or different.

[0017] In some embodiments, the transistor may further include a gate contact conductor 102GC, a source contact conductor 102SC, and a drain contact conductor 102DC, wherein the gate contact conductor 102GC is disposed on and electrically connected to the gate 102G, the source contact conductor 102SC is disposed on and electrically connected to the source 102S, and the drain contact conductor 102DC is disposed on and electrically connected to the drain 102D. Furthermore, the transistor may further include a contact plug CP, wherein the source contact conductor 102SC extends laterally from above the source 102S to above the contact plug CP, and the contact plug CP penetrates the protective layer 112, the gate insulating layer 102GI, and the buffer compound semiconductor layer 110, thereby contacting the second surface 100B of the substrate 100. In other words, the source 102S is electrically connected to the contact plug CP through the source contact conductor 102SC.

[0018] Please refer to Figure 2 ,Will Figure 1 The structure is flipped so that the first surface 100A of the substrate 100 faces upwards. Then, a thinning process is performed to reduce the thickness of the substrate 100. In this embodiment, the thinning process of the substrate 100 is performed on the first surface 100A of the substrate 100 to reduce the distance between the first surface 100A and the second surface 100B of the substrate 100. In some embodiments, the thinning process of the substrate 100 includes chemical mechanical polishing (CMP), mechanical grinding, or a combination of the foregoing processes. In this embodiment, the thickness of the substrate 100 after thinning is between 20 micrometers and 200 micrometers.

[0019] Please refer to Figure 3 After the substrate 100 is thinned, a patterning process is performed to pattern the substrate 100. In this embodiment, the patterning process of the substrate 100 is performed on the first surface 100A' of the thinned substrate 100 to simultaneously form at least one insulating cavity C and a through-hole TH in the substrate 100. The insulating cavity C extends from the first surface 100A' to the second surface 100B to penetrate the substrate 100, and the through-hole TH extends from the first surface 100A' to the second surface 100B to penetrate the substrate 100. In other words, the depth of the insulating cavity C and the through-hole TH is substantially the same as the thickness of the thinned substrate 100. In this embodiment, the width of the through-hole TH may be greater than or substantially equal to the width of the insulating cavity C.

[0020] like Figure 3As shown, the via TH exposes the bottom surface of the contact plug CP and a portion of the bottom surface of the buffer compound semiconductor layer 110, and the insulating cavity C also exposes a portion of the bottom surface of the buffer compound semiconductor layer 110, and the insulating cavity C is located below the semiconductor assembly 102. In this embodiment, the insulating cavity C is located below the transistor gate 102G and the channel layer 102C to reduce the high-frequency coupling effect of the channel layer 102C.

[0021] Please refer to Figure 4 A liner 114 is formed on the substrate 100, wherein the liner 114 is distributed on the first surface 100A' of the substrate 100 and on the sidewalls defining the insulating cavity C and the via TH, but the liner 114 does not cover the bottom surface of the contact plug CP. For example, a dielectric material can be formed on the substrate 100 by atomic layer deposition (ALD), chemical vapor deposition, physical vapor deposition, etc., and then the dielectric material in contact with the bottom surface of the contact plug CP is removed by etching to form the liner 114. In some embodiments, the liner 114 is in contact with the buffer compound semiconductor layer 110 exposed by the insulating cavity C and the via TH. Furthermore, the material of the liner 114 includes silicon oxide or other suitable dielectric materials.

[0022] Please refer to Figure 5 A seed layer 116 is formed on the substrate 100, covering the liner 114. Since the liner 114 does not cover the bottom surface of the contact plug CP, the seed layer 116 contacts the bottom surface of the contact plug CP not covered by the liner 114. In some embodiments, the seed layer 116 contacts the buffer compound semiconductor layer 110 not covered by the liner 114. The seed layer 116 can be deposited comprehensively on the liner 114, the bottom surface of the contact plug CP not covered by the liner 114, and the insulating cavity C by a sputtering process. Furthermore, the seed layer 116 can not only serve as a seed layer for subsequent electroplating processes but also provide a barrier layer effect.

[0023] Next, a mask layer 118 is formed on the first surface 100A' of the substrate 100 to cover the insulating cavity C and the seed layer 116 located near the insulating cavity C. In this embodiment, as... Figure 5 As illustrated, the mask layer 118 includes a patterned dry film with a specific pattern. When the patterned dry film is attached to the seed layer 116, it can cover the insulating cavity C but not fill it. In some other feasible embodiments, not shown in the figures, the mask layer 118 includes a patterned photoresist layer formed by a spin coating process. When the patterned photoresist layer is formed on the seed layer 116, it can cover and fill the insulating cavity C.

[0024] Please refer to Figure 5 and Figure 6 An electroplating process can be performed to form a conductive layer 120 on the seed layer 116 not covered by the masking layer 118, wherein the conductive layer 120 fills the insulating cavity C. In this embodiment, the through-hole TH is partially filled by the conductive layer 120. In other embodiments, not shown, the through-hole TH may be completely filled by the conductive layer 120. After forming the conductive layer 120, the masking layer 118 is removed to expose a portion of the seed layer 116 not covered by the conductive layer 120. Then, the seed layer 116 not covered by the conductive layer 120 is removed until a portion of the substrate 114 is exposed. Figure 6 As illustrated, the liner 114 is located at least between the substrate 100 and the conductive layer 120. In other words, the substrate 100 can be separated from the conductive layer 120 by the liner 114.

[0025] The source 102S is grounded through the source contact conductor 102SC, the conductive plug CP, and the conductive layer 120. Compared with wire bonding, the trace distance required for grounding the source 102S can be reduced, thereby reducing parasitic inductance and other related problems. The insulating cavity C located below the channel layer 102C of the transistor can reduce the high-frequency coupling effect of the channel layer 102C.

[0026] Please refer to Figure 7 and Figure 8 After forming the conductive layer 120, a support substrate 122 is provided, and the conductive layer 120 formed on the substrate 100 is bonded to the support substrate 122. In this embodiment, the support substrate 122 is made of silicon, an organic substrate, or other suitable semiconductor or packaging material. Next, the carrier substrate 106 is separated from the bonding dielectric layer 104 to peel the carrier substrate 106 off the bonding dielectric layer 104. Figure 8 As illustrated, the insulating cavity C located between the support substrate 122 and the semiconductor component 102 can be selectively vented with a heat dissipation fluid 124 (e.g., cooling water or other heat dissipation fluids) to improve the overall heat dissipation performance of the semiconductor structure.

[0027] Figure 9 and Figure 10 Cross-sectional schematic diagrams of the substrate, conductive layer, and contact plug in the semiconductor structure are shown respectively.

[0028] Please refer to Figure 9The liner 114 includes a first portion 114a covering the sidewall of the substrate 100 and a second portion 114b covering the first surface 100A' of the substrate 100. The first portion 114a is located in the via TH, and the thickness L of the first portion 114a may be substantially equal to the thickness T of the second portion 114b. In this embodiment, the bottom surface of the contact plug CP contacts the top surface of the conductive layer 120. The size of the via TH is larger than the size of the bottom surface of the contact plug CP, and the minimum size difference may be equal to the thickness T of the second portion 114b. The area of ​​the top surface of the conductive layer 120 is substantially equal to the area of ​​the bottom surface of the contact plug CP. In this case, the liner 114 contacts the bottom surface of the contact plug CP, while the substrate 100 does not contact the contact plug CP. In some other embodiments, the area of ​​the top surface of the conductive layer 120 is larger than the area of ​​the bottom surface of the contact plug CP. In this case, the liner 114 does not contact the bottom surface of the contact plug CP.

[0029] Please refer to Figure 10 The liner 114 includes a first portion 114a covering the sidewall of the substrate 100 and a second portion 114b covering the first surface 100A of the substrate 100. The first portion 114b is located in the via TH. The thickness L of the first portion 114a is less than the thickness T of the second portion 114b, and the thickness L of the first portion 114a is approximately 5% of the thickness T of the second portion 114b. In this embodiment, the bottom surface of the contact plug CP is in contact with the top surface of the conductive layer 120. The size of the via TH is larger than the size of the bottom surface of the contact plug CP, and the minimum size difference can be equal to the thickness T of the second portion 114b. The area of ​​the top surface of the conductive layer 120 is substantially equal to the area of ​​the bottom surface of the contact plug CP. At this time, the liner 114 is in contact with the bottom surface of the contact plug CP, while the substrate 100 is not in contact with the contact plug CP. In some other embodiments, the area of ​​the top surface of the conductive layer 120 is larger than the area of ​​the bottom surface of the contact plug CP, in which case the liner 114 does not contact the bottom surface of the contact plug CP.

[0030] Figures 11 to 18 This is a cross-sectional schematic diagram of a semiconductor structure according to different embodiments of the present invention.

[0031] Please refer to Figure 7 and Figure 11 , Figure 11 The semiconductor structure shown in the figure and Figure 7 The semiconductor structures shown in the figure are similar, the difference being... Figure 11 The insulating cavity C shown is relatively wide so that the width of the via TH in the semiconductor structure is smaller than the width of the insulating cavity C. In this embodiment, the insulating cavity C is located below the transistor gate 102G and the channel layer 102C to reduce the high-frequency coupling effect of the channel layer 102C.

[0032] Please refer to Figure 7 and Figure 12 , Figure 12 The semiconductor structure shown in the figure and Figure 7 The semiconductor structures shown in the figure are similar, the difference being... Figure 12 The depth of the insulating cavity C shown in the figure is less than the thickness of the substrate 100. In other words, the insulating cavity C extends from the first surface 100A' of the substrate 100 to the second surface 100B, but the insulating cavity C does not penetrate the substrate.

[0033] Please refer to Figure 13 The semiconductor component 102 includes a shared drain 102D and multiple sources 102S. In some embodiments, the semiconductor component 102 employs a finger-shaped drain 120D and source 102S. The substrate 100 has multiple vias TH, and multiple conductive layers 120 located in the vias TH are electrically connected to their respective sources 102S. In this embodiment, the insulating cavity C is located below the transistor's gate 102G, drain 102S, source 102D, and channel layer 102C to reduce the high-frequency coupling effect of the channel layer 102C.

[0034] Please refer to Figure 11 and Figure 14 , Figure 14 The semiconductor structure shown in the figure and Figure 11 The semiconductor structures shown in the figure are similar, the difference being... Figure 14 The semiconductor structure illustrated further includes a dielectric layer 126, which covers a conductive layer, a substrate not covered by the conductive layer, and a portion of the semiconductor component exposed through an insulating cavity. The dielectric layer 126 may be an organic adhesive, such as polyimide, benzocyclobutene (BCB), or other suitable dielectric layer materials.

[0035] Please refer to Figures 15 to 18 , Figures 15 to 18 The semiconductor structure shown in the figure and Figures 11 to 14 The semiconductor structures shown in the figure are similar, the difference being... Figures 15 to 18 The semiconductor structure in the figure does not include a support substrate 122 that is bonded to the conductive layer 120.

[0036] In summary, the above embodiments of the present invention can reduce the trace distance of the source ground without significantly increasing the process cost, thereby reducing parasitic inductance and other related problems, and can effectively reduce the high-frequency coupling effect of the channel layer.

[0037] Of course, the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a first surface, a second surface opposite to the first surface, at least one insulating cavity extending from the first surface to the second surface, and a through hole penetrating the substrate; A conductive layer is filled into the through-hole; as well as A semiconductor component is disposed on the second surface and electrically connected to the conductive layer, wherein the semiconductor component includes a transistor, and the at least one insulating cavity is located below the channel layer of the transistor to reduce the high-frequency coupling effect of the channel layer.

2. The semiconductor structure as described in claim 1, characterized in that, The source of the transistor is grounded through the conductive layer, and the at least one insulating cavity is located below the gate of the transistor.

3. The semiconductor structure as described in claim 2, characterized in that, The source electrode is in contact with the top surface of the conductive layer through the bottom surface of the contact plug, and the area of ​​the top surface of the conductive layer is greater than or equal to the area of ​​the bottom surface of the contact plug.

4. The semiconductor structure as described in claim 2, characterized in that, The source electrode is electrically connected to the conductive layer via a contact plug, and the bottom surface of the contact plug is in contact with the top surface of the conductive layer.

5. The semiconductor structure as described in claim 1, characterized in that, The at least one insulating cavity extends from the first surface to the second surface to penetrate the substrate.

6. The semiconductor structure as described in claim 5, characterized in that, The width of the through hole is less than or equal to the width of the at least one insulating cavity.

7. The semiconductor structure as described in claim 1, characterized in that, The width of the through hole is greater than the width of the at least one insulating cavity, and the depth of the at least one insulating cavity is less than the thickness of the substrate.

8. The semiconductor structure as described in claim 1, characterized in that, Including: A liner, wherein the liner is at least located between the substrate and the conductive layer.

9. The semiconductor structure as described in claim 1, characterized in that, Including: A support substrate, wherein the conductive layer is bonded to the support substrate.

10. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first surface and a second surface opposite to the first surface; A semiconductor component, including a transistor, is formed on a second surface of the substrate; At least one insulating cavity and a through-hole are formed in the substrate, wherein the insulating cavity extends from the first surface to the second surface and the at least one insulating cavity penetrates the substrate; as well as A conductive layer is formed within the via, wherein the semiconductor component is electrically connected to the conductive layer, and the at least one insulating cavity is located below the channel layer of the transistor to reduce the high-frequency coupling effect of the channel layer.

11. The method for manufacturing a semiconductor structure as described in claim 10, characterized in that, The at least one insulating cavity and the through-hole are formed after the semiconductor assembly is formed.

12. The method for manufacturing a semiconductor structure as described in claim 11, characterized in that, Including: The substrate on which the semiconductor component is formed is bonded to a carrier substrate such that the semiconductor component is positioned between the substrate and the carrier substrate.

13. The method for manufacturing a semiconductor structure as described in claim 10, characterized in that, The at least one insulating cavity and the through hole are formed simultaneously in the substrate.

14. The method for manufacturing a semiconductor structure as described in claim 10, characterized in that, The at least one insulating cavity extends from the first surface to the second surface through the substrate, and the width of the through hole is less than or equal to the width of the at least one insulating cavity.

15. The method for manufacturing a semiconductor structure as described in claim 10, characterized in that, The width of the through hole is greater than the width of the at least one insulating cavity.

16. The method for manufacturing a semiconductor structure as described in claim 10, characterized in that, Including: A liner is formed, wherein the liner is at least located between the substrate and the conductive layer.

17. The method for manufacturing a semiconductor structure as described in claim 10, characterized in that, Including: A support substrate is provided, and the conductive layer is bonded to the support substrate.

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