Display device and method of driving the same

Abstract

The present application relates to a display device and a method for driving the same. The display device includes a display unit, a memory, a compensator, and a data driver. The display unit includes pixels, each of which includes a stack connected in series, and each of the stacks includes at least one light-emitting device. The memory stores stack quantity information. Each piece of stack quantity information indicates the number of stacks constituting an effective light source in the stack for each pixel. The compensator generates compensation data by compensating image data based on the stack quantity information. The data driver generates a data voltage based on the compensation data and provides the data voltage to the display unit. Each pixel emits light having a brightness corresponding to the data voltage.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method of driving the same. Background Art

[0002] With the increasing interest in information display and the increasing demand for using portable information media, the demand and commercialization of display devices are intensifying. Summary of the Invention

[0003] Technical issues

[0004] An aspect of the present disclosure is to provide a display device capable of improving display quality and a method of driving the same.

[0005] Technical Solution

[0006] A display device according to an embodiment of the present disclosure includes: a display unit including pixels, wherein each pixel includes stacks connected in series, and each stack includes a light-emitting element; a memory storing a plurality of stack quantity information, wherein each of the plurality of stack quantity information indicates the number of stacks constituting an effective light source in the stack for each pixel; a compensator generating compensation data by compensating image data based on the plurality of stack quantity information; and a data driver generating a data voltage based on the compensation data and supplying the data voltage to the display unit. The pixel is configured to emit light having a brightness corresponding to the data voltage.

[0007] In an embodiment, the pixel may include a first pixel and a second pixel, the first stacking quantity information of the first pixel may have a value different from the value of the second stacking quantity information of the second pixel, and the first data voltage applied to the first pixel for the same brightness as the second pixel may be different from the second data voltage applied to the second pixel.

[0008] In an embodiment, as the value of the second stack number information decreases, the second data voltage for the same luminance as the first pixel and the driving current flowing through the light emitting element of the second pixel may increase.

[0009] In an embodiment, when the value of the first stack quantity information is greater than the value of the second stack quantity information, the compensator may generate a first compensated grayscale value by reducing the first grayscale value of the first pixel based on the second grayscale value of the second pixel, the image data may include the first grayscale value and the second grayscale value, and the compensation data may include the first compensated grayscale value.

[0010] In an embodiment, when the value of the first stack quantity information is greater than the value of the second stack quantity information, the compensator may generate a second compensated grayscale value by amplifying the second grayscale value of the second pixel based on the first grayscale value of the first pixel, the image data may include the first grayscale value and the second grayscale value, and the compensation data may include the second compensated grayscale value.

[0011] In an embodiment, each of the pixels may include two stacks.

[0012] In an embodiment, each pixel may further include: a driving transistor connected between a first power line and a second power line; a switching transistor connected between a data line and a gate electrode of the driving transistor; a sensing transistor connected between one electrode of the driving transistor and the sensing line; and a storage capacitor connected between the gate electrode of the driving transistor and one electrode of the driving transistor. The stack may be connected between one electrode of the driving transistor and the second power line.

[0013] In an embodiment, the compensator may set the plurality of pieces of stack quantity information based on a sensing voltage obtained by sensing a voltage applied to one electrode of the driving transistor in response to a reference voltage applied to a gate electrode of the driving transistor.

[0014] In an embodiment, when the sensing voltage is within a reference range, the compensator may set corresponding stack quantity information among the plurality of pieces of stack quantity information to have a maximum value.

[0015] In an embodiment, when the sensing voltage is outside the reference range, the compensator may set corresponding stack quantity information among the plurality of pieces of stack quantity information to have a value smaller than a maximum value.

[0016] In an embodiment, the sensing voltage may be equal to a value obtained by multiplying a threshold voltage of a light emitting element by a value of corresponding stacking quantity information.

[0017] In an embodiment, each of the pixels may include four stacks.

[0018] A method for driving a display device according to an embodiment of the present disclosure can drive a display device including pixels, wherein each pixel includes a driving transistor and a stack of first electrodes connected in series to the driving transistor, and each stack includes a light-emitting element. The method includes: applying a first voltage to the gate electrode of the driving transistor; measuring a second voltage applied to the first electrode of the driving transistor in response to the first voltage; generating stack quantity information based on the second voltage, wherein the stack quantity information indicates the number of stacks constituting an effective light source in the stack for each pixel; and setting a data voltage applied to the gate electrode of the driving transistor based on the stack quantity information.

[0019] In an embodiment, generating the stack quantity information based on the second voltage may include setting the stack quantity information to have a first value when the second voltage is within a first reference range.

[0020] In an embodiment, the first reference range may be set based on the total number of stacks and a threshold voltage of a light emitting element.

[0021] In an embodiment, generating the stack quantity information based on the second voltage may further include setting the stack quantity information to have a second value smaller than the first value when the second voltage is outside a first reference range.

[0022] In an embodiment, the pixel may include a first pixel and a second pixel, the first stacking quantity information of the first pixel may have a value different from the value of the second stacking quantity information of the second pixel, and the first data voltage applied to the first pixel for the same brightness as the second pixel may be different from the second data voltage applied to the second pixel.

[0023] In an embodiment, as the value of the second stack number information decreases, the second data voltage for the same luminance as the first pixel and the driving current flowing through the light emitting element of the second pixel may increase.

[0024] In an embodiment, setting the data voltage may include: when the value of the first stack quantity information is greater than the value of the second stack quantity information, generating a first compensated grayscale value by reducing the first grayscale value of the first pixel based on the second grayscale value of the second pixel; and generating a first data voltage for the first pixel based on the first compensated grayscale value.

[0025] In an embodiment, setting the data voltage may include: when the value of the first stack quantity information is greater than the value of the second stack quantity information, generating a second compensated grayscale value by amplifying the second grayscale value of the second pixel based on the first grayscale value of the first pixel; and generating a second data voltage for the second pixel based on the second compensated grayscale value.

[0026] Beneficial effects

[0027] The display device and the method for driving the display device according to the described embodiments of the present disclosure can generate stacking quantity information for each pixel and generate compensation data by compensating image data based on the stacking quantity information. Therefore, the degradation of display quality caused by the deviation of the number of pixel levels (i.e., the levels constituting the effective light source) can be reduced or improved.

[0028] In some embodiments, a display device and a method of driving a display device can improve the lifespan of a pixel by compensating (or reducing) a first grayscale value of a first pixel corresponding to a relatively large first stacking quantity information compared to a second grayscale value of a second pixel corresponding to a relatively small second stacking quantity information.

[0029] In addition, the display device can improve display quality by compensating (or increasing) the second grayscale value of the second pixel corresponding to the relatively small second stacking quantity information compared to the first grayscale value of the first pixel corresponding to the relatively large first stacking quantity information.

[0030] The aspects of the present disclosure are not limited to the above-exemplified contents, and more various aspects are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a block diagram illustrating a display device according to some embodiments of the present disclosure.

[0032] Figure 2 It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device.

[0033] Figure 3 It shows Figure 2 A plan view of an example of pixels.

[0034] Figure 4 It is shown in Figure 2 Graph showing an example waveform of a signal measured in a pixel.

[0035] Figure 5 It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device.

[0036] Figure 6 It is shown in Figure 5 Graph showing an example waveform of a signal measured in a pixel.

[0037] Figure 7 It is shown that the Figure 1 A diagram of an example of a lookup table of stack quantity information used in a display device.

[0038] Figure 8 It is used to describe the Figure 1 A diagram showing the operation of the compensator in the display device.

[0039] Figure 9 It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device.

[0040] Figure 10 It shows Figure 9 A plan view of an example of pixels.

[0041] Figure 11 It is shown in Figure 9 Graph showing an example waveform of a signal measured in a pixel.

[0042] Figure 12 It is shown that the Figure 1 FIG. 1 is a diagram of another example of a lookup table for stack quantity information used in a display device.

[0043] Figure 13 is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure.

[0044] Figure 14 It is shown that the Figure 13 A flowchart of an example of generating stack quantity information in a method.

[0045] Figure 15 is schematically shown in Figure 1 A three-dimensional diagram of a light-emitting element used as a light source in a display device.

[0046] Figure 16 yes Figure 15 A cross-sectional view of a light-emitting element. DETAILED DESCRIPTION

[0047] Since the present disclosure may have various modified embodiments and forms, specific embodiments are shown in the drawings and described in the detailed description. However, this is not intended to limit the present disclosure to specific embodiments, and it will be understood that it includes various modifications, equivalents and / or substitutes that fall within the spirit and scope of the present disclosure.

[0048] Throughout the accompanying drawings, the same reference numerals are used to represent the same elements. In the accompanying drawings, for clarity of the present disclosure, the size of the structure is larger than the actual size. In addition, these terms such as "first", "second" and other numerical terms are only used to distinguish one element from another element. These terms are only used for the purpose of distinguishing one element from another element. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the singular forms "one", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise.

[0049] As used in this disclosure, the terms "comprises," "comprising," "including," and "having" are inclusive, and thus specify the presence of the recited features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. It will be understood that when a part, such as a layer, film, region, or plate, is referred to as being "on" another part, it may be "directly "on" the other part, or may be "indirectly "on" the other part with one or more intervening parts therebetween. In this disclosure, it will be understood that when a part, such as a layer, film, region, or plate, is referred to as being formed "on" another part, the direction formed is not limited to an upward direction, and includes a lateral or downward direction. Conversely, it will be understood that when a part, such as a layer, film, region, or plate, is referred to as being "under" another part, it may be "directly "under" the other part, or may be "indirectly "under" the other part with one or more intervening parts therebetween.

[0050] When a particular element (e.g., a first element) is “(operably or communicatively) coupled” with / “(operably or communicatively) coupled to” or “connected to” another element (e.g., a second element), it will be understood that the particular element may be directly connected to the other element or connected to the other element through another element (e.g., a third element). When a particular element (e.g., a first element) is “directly coupled” with / “directly coupled to” or “directly connected to” another element (e.g., a second element), it will be understood that there is no further element (e.g., a third element) between the particular element and the other element.

[0051] Hereinafter, embodiments of the present disclosure and other issues necessary for those skilled in the art to easily understand the contents of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, unless the context clearly includes only the singular, expressions in the singular also include expressions in the plural.

[0052] Figure 1 is a block diagram illustrating a display device according to some embodiments of the present disclosure.

[0053] refer to Figure 1 The display device 100 includes a display unit 110 (or pixel unit, display panel, etc.), a scan driver 120, a data driver 130, a sensing driver 140, a timing controller 150, a compensator 160 and a memory 170.

[0054] The display unit 110 may include scan lines SL1 to SLn (where n is a positive integer) (or first scan lines), data lines DL1 to DLm (where m is a positive integer), and pixels PXL. The display unit 110 may also include sensing scan lines SSL1 to SSLn (or second scan lines) and sensing lines RL1 to RLm (or readout lines).

[0055] The pixels PXL may be disposed in a region (eg, a pixel region) divided by the scan lines SL1 to SLn and the data lines DL1 to DLm.

[0056] The pixel PXL can be connected to a corresponding one of the scan lines SL1 to SLn and a corresponding one of the data lines DL1 to DLm. In some embodiments, the pixel PXL can be connected to a corresponding one of the sensing scan lines SSL1 to SSLn and a corresponding one of the sensing lines RL1 to RLm. Hereinafter, "connected" includes not only electrical connection but also physical connection, and may include not only direct connection but also indirect connection through other elements.

[0057] The pixel PXL may include a light emitting element and at least one transistor for supplying or intended to supply a driving current to the light emitting element.

[0058] The pixel PXL may emit light having a brightness corresponding to a data signal (or data voltage) provided through a data line (e.g., a corresponding one of the data lines DL1 to DLm) in response to a first scan signal provided through a scan line (e.g., a corresponding one of the scan lines SL1 to SLn). In some embodiments, the pixel PXL may output characteristic information of the light-emitting element (e.g., outputting a sensed voltage or a sensed current as information related to the threshold voltage of the driving transistor) through a sensing line (e.g., a corresponding one of the sensing scan lines SSL1 to SSLn) in response to a second scan signal provided through a sensing scan line (e.g., a corresponding one of the sensing scan lines SSL1 to SSLn).

[0059] The detailed configuration of the pixel PXL will be referred to below Figure 2 Provide a description.

[0060] On the other hand, a first power supply voltage VDD (or high power supply voltage) and a second power supply voltage VSS (or low power supply voltage) may be provided to the display unit 110. The first power supply voltage VDD and the second power supply voltage VSS may be voltages required for the operation of the pixel PXL, and the first power supply voltage VDD may have a higher voltage level than the second power supply voltage VSS. The first power supply voltage VDD and the second power supply voltage VSS may be provided from separate power supplies (or power management integrated circuits (PMICs)).

[0061] The scan driver 120 may generate a scan signal (or a first scan signal) based on the scan control signal SCS and may sequentially provide the scan signal to the scan lines SL1 to SLn. In this case, the scan control signal SCS may include a scan start pulse, a scan clock signal, etc., and may be provided from the timing controller 150. For example, the scan driver 120 may include a shift register for sequentially generating and outputting a pulse scan signal corresponding to a pulse scan start signal (e.g., a gate-on voltage level pulse for turning on a transistor) using a scan clock signal.

[0062] Similar to the scan signal, the scan driver 120 may also generate a sensing scan signal (or a second scan signal) and sequentially provide the sensing scan signal to the sensing scan lines SSL1 to SSLn.

[0063] The data driver 130 may generate a data signal (or data voltage) based on the data control signal DCS provided from the timing controller 150 and the compensation data DATA3 provided from the compensator 160, and may provide the data signal to the data lines DL1 to DLm. In this case, the data control signal DCS is a signal for controlling the operation of the data driver 130 and may include a load signal (or data enable signal) instructing to output a valid data voltage.

[0064] In an embodiment, the data driver 130 may generate a data signal (or data voltage) corresponding to the data value (or grayscale value) included in the compensation data DATA3 using a gamma voltage. In this case, the gamma voltage may be generated by the data driver 130 or may be provided from a separate gamma voltage generating circuit (e.g., a gamma integrated circuit). For example, the data driver 130 may select one of the gamma voltages based on the data value and output the selected gamma voltage as the data signal.

[0065] The sensing driver 140 may supply an initialization voltage to the sensing lines RL1 to RLm in a sensing mode (or a sensing period), and may sense light emission characteristics of the pixels PXL through the sensing lines RL1 to RLm.

[0066] For reference, the display device 100 can operate in a sensing mode (or sensing period) or a display mode (or display period). In the display mode, the display device 100 can provide a data voltage to the pixel PXL so that the pixel PXL emits light, and in the sensing mode, the display device 100 can sense the light emission characteristics of the pixel PXL. The sensing time corresponding to the sensing mode can be allocated before or after the display period. In some cases, the display period and the sensing period can be included in one frame (or frame period).

[0067] The light emission characteristics of the pixel PXL may include a threshold voltage, mobility, and characteristic information (e.g., current-voltage characteristics) of at least one transistor (e.g., a driving transistor) in the pixel PXL. For example, the sensing driver 140 may detect a sensing value V_S (e.g., a sensing voltage, a sensing current, sensing data, etc.) corresponding to the light emission characteristics of the pixel PXL through the sensing lines RL1 to RLm.

[0068] The sensed value V_S may be provided to the compensator 160 (or the timing controller 150), and the compensator 160 (or the timing controller 150) may compensate the image data DATA2 (or the input image data DATA1) based on the sensed value V_S. However, the present disclosure is not limited thereto. For example, the sensed value V_S may be provided from the sense driver 140 to the data driver 130, and the data driver 130 may generate a data voltage based on the sensed value V_S. For example, the data driver 130 may change or compensate the data voltage based on the amount of change in the sensed value V_S. That is, the data voltage may be compensated based on the sensed light emission characteristics (or changes in the light emission characteristics) of the pixel PXL.

[0069] The timing controller 150 may receive input image data DATA1 and a control signal CS from an external device (e.g., an application processor), may generate a scan control signal SCS and a data control signal DCS based on the control signal CS, and may convert the input image data DATA1 to generate image data DATA2. In this case, the control signal CS may include a vertical synchronization signal, a horizontal synchronization signal, a clock signal, etc. For example, the timing controller 150 may convert the input image data DATA1 into image data DATA2 in a format usable by the data driver 130.

[0070] The compensator 160 may generate stack number information INFO_S based on the sensing value V_S provided from the sensing driver 140 .

[0071] In this case, the stack number information INFO_S may indicate the number of stages (or stacks, which include a plurality of light emitting elements connected in parallel) connected in series to constitute an effective light source within each of the pixels PXL. Figure 2 As described above, a light source may include multiple stages. In some cases, due to connection defects (e.g., short circuits), some stages may not contribute to forming an effective light source. The stack quantity information INFO_S may indicate the number of stages contributing to forming an effective light source (i.e., normally aligned stages, excluding some defective stages).

[0072] However, the stacking number information INFO_S is not limited thereto. For example, the stacking number information INFO_S may indicate the number of some stages (eg, defective stages) that do not participate in constituting an effective light source among the stages of the pixel PXL.

[0073] As will be referenced below Figure 5 As described above, when the light source includes some defective stages, the sensing value V_S (e.g., the sensing value corresponding to the threshold voltage of the driving transistor) of the corresponding pixel PXL may be outside the expected sensing value range, that is, the reference range (e.g., the deviation or variable range of the threshold voltage of the driving transistor). When the sensing value V_S is outside the reference range, it can be determined that defects have occurred in some stages, and the number of stages participating in constituting the effective light source can be calculated based on the sensing value V_S.

[0074] The stack quantity information INFO_S and the configuration for calculating the stack quantity information INFO_S will be referred to below. Figure 6 and Figure 7 Provide a description.

[0075] On the other hand, the stack quantity information INFO_S may be stored in the memory 170 and may be provided from the memory 170 to the compensator 160 .

[0076] In some embodiments, the compensator 160 may compensate the image data DATA2 based on the stacking number information INFO_S to generate the compensation data DATA3 .

[0077] In some embodiments, when the first stacking quantity information of the first pixel PXL1 has a value different from the value of the second stacking quantity information of the second pixel PXL2, the compensator 160 can compensate for at least one of the first grayscale value of the first pixel PXL1 and the second grayscale value of the second pixel PXL2 based on the first stacking quantity information and the second stacking quantity information.

[0078] In an embodiment, when the first stack quantity information of the first pixel PXL1 is greater than the second stack quantity information of the second pixel PXL2, the compensator 160 may reduce the first grayscale value of the first pixel PXL1 by a specific ratio based on the second grayscale value of the second pixel PXL2. In this case, the specific ratio may be the ratio of the value of the second stack quantity information to the value of the first stack quantity information. For example, when the first stack quantity information of the first pixel PXL1 is 2 and the second stack quantity information of the second pixel PXL2 is 1, the compensator 160 may reduce the first grayscale value of the first pixel PXL1 by ½.

[0079] For reference, when the same drive current flows through first pixel PXL1 and second pixel PXL2, the first stacking quantity information of first pixel PXL1 has a value greater than the second stacking quantity information of second pixel PXL2, and therefore, first pixel PXL1 can emit light having a higher brightness than the brightness of second pixel PXL2. Therefore, based on second pixel PXL2 emitting light having a relatively low brightness, the first grayscale value of first pixel PXL1 can be reduced so that first pixel PXL1 emits light having a brightness substantially the same as that of second pixel PXL2. In this case, the overall brightness of display device 100 can be reduced, but the degradation of display quality caused by the deviation in stacking quantity information (e.g., light spots due to brightness differences) can be improved. In some embodiments, because the drive current flowing through first pixel PXL1 is relatively reduced according to the reduced first grayscale value, the stress (or light emission stress) of first pixel PXL1 (and pixel PXL) can be reduced, and the lifespan of first pixel PXL1 (and pixel PXL) can be improved.

[0080] In an embodiment, when the first stack quantity information of the first pixel PXL1 has a value greater than the second stack quantity information of the second pixel PXL2, the compensator 160 may increase the second grayscale value of the second pixel PXL2 by a specific ratio based on the first grayscale value of the first pixel PXL1. For example, when the first stack quantity information of the first pixel PXL1 has a value of 2 and the second stack quantity information of the second pixel PXL2 has a value of 1, the compensator 160 may increase the second grayscale value of the second pixel PXL2 by twice.

[0081] That is, based on the first pixel PXL1 emitting light having relatively high brightness, the second grayscale value of the second pixel PXL2 can be increased so that the second pixel PXL2 emits light having substantially the same brightness as the first pixel PXL1. In this case, the overall brightness of the display device 100 is not reduced and is substantially maintained at a desired brightness, and the deterioration of display quality due to the deviation of the stacking quantity information (for example, light spots due to brightness differences) can be improved.

[0082] In an embodiment, when the first stack quantity information of the first pixel PXL1 has a value greater than the second stack quantity information of the second pixel PXL2, the compensator 160 may reduce the first grayscale value of the first pixel PXL1 and increase the second grayscale value of the second pixel PXL2. For example, when the first stack quantity information of the first pixel PXL1 has a value of 2 and the second stack quantity information of the second pixel PXL2 has a value of 1, the compensator 160 may reduce the first grayscale value of the first pixel PXL1 to 0.75 times the value and increase the second grayscale value of the second pixel PXL2 to 1.5 times the value.

[0083] The memory 170 may store stacking number information INFO_S and light emission characteristics (eg, a threshold voltage, mobility, etc. of a driving transistor) for each pixel PXL.

[0084] The memory 170 may be implemented as a non-volatile memory device, such as an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano-floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), and a ferroelectric random access memory (FRAM).

[0085] As referenced above Figure 1 As described above, the display device 100 can generate stacking quantity information INFO_S for each pixel PXL through the compensator 160, and compensate the image data DATA2 based on the stacking quantity information INFO_S to generate compensation data DATA3. Therefore, it is possible to reduce or improve the degradation of display quality caused by the deviation of the number of pixel levels (e.g., effective levels) (i.e., levels constituting an effective light source).

[0086] In some embodiments, the display device 100 can improve the lifespan of the pixel PXL by compensating (or reducing) the first grayscale value of the first pixel PXL1 corresponding to the relatively large first stacking quantity information compared to the second grayscale value of the second pixel PXL2 corresponding to the relatively small second stacking quantity information.

[0087] In addition, when necessary, the display device 100 can improve the display quality by compensating (or increasing) the second grayscale value of the second pixel PXL2 corresponding to the relatively small second stacking quantity information compared to the first grayscale value of the first pixel PXL1 corresponding to the relatively large first stacking quantity information.

[0088] Figure 1The scan driver 120, the data driver 130, the sense driver 140, the timing controller 150, and the compensator 160 are shown as being configured independently of one another, but this is an example and the present disclosure is not limited thereto. For example, at least one of the scan driver 120, the data driver 130, the sense driver 140, the timing controller 150, and the compensator 160 may be formed on the display unit 110, or implemented as an integrated circuit (IC), and may be mounted on a flexible circuit board and connected to the display unit 110. For example, the scan driver 120 may be formed on the display unit 110. In some embodiments, at least two of the scan driver 120, the data driver 130, the sense driver 140, the timing controller 150, and the compensator 160 may be implemented as one IC. For example, the data driver 130 and the sense driver 140 may be implemented as one integrated circuit. As an example, the timing controller 150 and the compensator 160 may be implemented as one integrated circuit.

[0089] Figure 2 It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device.

[0090] refer to Figure 2 The pixel PXL may include a light emitting unit EMU that generates light with brightness corresponding to the data signal. In some embodiments, the pixel PXL may further include a pixel circuit PXC for driving the light emitting unit EMU.

[0091] The light-emitting unit EMU may include a plurality of light-emitting elements LD connected in parallel between a first power line PL1 to which a first power supply voltage VDD is applied and a second power line PL2 to which a second power supply voltage VSS is applied. For example, the light-emitting unit EMU may include a first electrode EL1 (or a first alignment electrode) connected to the first power line PL1 via the pixel circuit PXC, a third electrode EL3 (or a second alignment electrode) connected to the second power line PL2, and a plurality of light-emitting elements LD connected in parallel in the same direction between the first electrode EL1 and the third electrode EL3. In an embodiment of the present disclosure, the first electrode EL1 may be an anode electrode, and the third electrode EL3 may be a cathode electrode.

[0092] Each of the light emitting elements LD included in the light emitting unit EMU may include one end connected to the first power line PL1 through the first electrode EL1 and the other end connected to the second power line PL2 through the third electrode EL3 .

[0093] Each light-emitting element LD connected in parallel in the same direction between the first electrode EL1 and the third electrode EL3 (to which voltages of different potentials (i.e., the first power supply voltage VDD and the second power supply voltage VSS) are supplied, respectively) can constitute each effective light source. These effective light sources can together constitute the light-emitting unit EMU of the pixel PXL.

[0094] The light emitting element LD of the light emitting unit EMU may emit light having a brightness corresponding to the driving current supplied by the pixel circuit PXC. For example, during each frame period, the pixel circuit PXC may supply the light emitting unit EMU with the frame data (eg, compensation data DATA3, see Figure 1 ) corresponding to the grayscale value of the light emitting unit. The driving current supplied to the light emitting unit EMU can be divided and flow through the light emitting elements LD. Therefore, when each of the light emitting elements LD emits light with a brightness corresponding to the current flowing therethrough, the light emitting unit EMU can emit light with a brightness corresponding to the driving current.

[0095] In addition to the light-emitting element LD constituting the effective light source, the light-emitting unit EMU may further include at least one ineffective light source, such as a reverse light-emitting element LDr. The reverse light-emitting element LDr may be connected in parallel with the light-emitting element LD constituting the effective light source between the first electrode EL1 and the third electrode EL3, and may be connected between the first electrode EL1 and the third electrode EL3 in a direction opposite to that of the light-emitting element LD (or a direction of different polarity). Even when a driving voltage (e.g., a set or predetermined driving voltage) (e.g., a forward driving voltage) is applied between the first electrode EL1 and the third electrode EL3, the reverse light-emitting element LDr remains in an ineffective state. Therefore, substantially no current flows through the reverse light-emitting element LDr.

[0096] The pixel circuit PXC may be connected to the scan line SLi, the sensing scan line SSLi, the data line DLj, and the sensing line RLj connected to the pixel PXL. In this case, each of i and j may be a positive integer. As an example, when it is assumed that the pixel PXL is provided in the display unit 110 (see FIG. Figure 1 ), the pixel circuit PXC of the pixel PXL can be connected to the i-th scan line SLi (hereinafter, referred to as the scan line SLi), the i-th sensing scan line SSLi (hereinafter, referred to as the sensing scan line SSLi), the j-th data line DLj (hereinafter, referred to as the data line DLj) and the j-th sensing line RLj (hereinafter, referred to as the sensing line RLj).

[0097] According to an embodiment, the pixel circuit PXC may include a first transistor T1, a second transistor T2, and a third transistor T3 and a storage capacitor Cst. However, the structure of the pixel circuit PXC is not limited to Figure 2 The embodiment shown in .

[0098] The first terminal (or first electrode) of the first transistor (e.g., a driving transistor) T1 can be connected to the first power line PL1, and the second terminal (or second electrode) of the first transistor (e.g., a driving transistor) T1 can be connected to the second node N2 (or the first electrode EL1 of the light-emitting unit EMU). In this case, the first terminal and the second terminal of the first transistor T1 can be different terminals. For example, when the first terminal is a drain electrode, the second terminal can be a source electrode. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the amount of drive current supplied to the light-emitting element LD in response to the voltage of the first node N1.

[0099] A first terminal of a second transistor (e.g., a switching transistor) T2 may be connected to a data line DLj, and a second terminal of the second transistor (e.g., a switching transistor) T2 may be connected to a first node N1. A gate electrode of the second transistor T2 may be connected to a scan line SLi. When the second transistor T2 is turned on by a scan signal SC having a gate-on voltage (e.g., a high voltage at which the second transistor T2 may be turned on) supplied from the scan line SLi, the second transistor T2 may electrically connect the data line DLj to the first node N1. At this time, a data signal Vdata of a corresponding frame may be supplied to the data line DLj, and thus, the data signal Vdata may be transmitted to the first node N1. The data signal Vdata transmitted to the first node N1 may be charged into a storage capacitor Cst. For example, the storage capacitor Cst connected between the first node N1 and the second node N2 may be charged to a voltage corresponding to the data signal Vdata transmitted to the first node N1, or may hold a charge corresponding to the data signal Vdata transmitted to the first node N1.

[0100] One electrode of the storage capacitor Cst may be connected to the first node N1, and the other electrode of the storage capacitor Cst may be connected to the second node N2. The storage capacitor Cst may be charged with a voltage corresponding to the data signal Vdata supplied to the first node N1 and may maintain the charged voltage until the data signal Vdata of the next frame is supplied.

[0101] A first terminal of the third transistor (e.g., a sensing transistor) T3 can be connected to the second node N2, and a second terminal of the third transistor (e.g., a sensing transistor) T3 can be connected to the sensing line RLj. A gate electrode of the third transistor T3 can be connected to the sensing scan line SSLi. In some embodiments, when the sensing line RLj is not used (e.g., omitted), the second terminal of the third transistor T3 can be connected to the data line DLj. In some embodiments, when the sensing scan line SSLi is not used (e.g., omitted), the gate electrode of the third transistor T3 can be connected to the scan line SLi. The third transistor T3 can be turned on by a sensing scan signal SS having a gate-on voltage (e.g., a high-level voltage) supplied to the sensing scan line SSLi during a sensing period (e.g., a set or predetermined sensing period) and can electrically connect the sensing line RLj to the second node N2.

[0102] Depending on the embodiment, the sensing period may be a period during which characteristic information (e.g., the threshold voltage of the first transistor T1) of each pixel PXL is extracted. During the sensing period described above, a reference voltage (e.g., a set or predetermined reference voltage at which the first transistor T1 can be turned on) can be supplied to the first node N1 via the data line DLj and the second transistor T2, or the first transistor T1 can be turned on by connecting each pixel PXL to a current source, etc. In some embodiments, the third transistor T3 can be turned on by supplying a sensing scan signal SS of a gate-on voltage to the third transistor T3 to connect the first transistor T1 to the sensing line RLj. Therefore, characteristic information of each pixel PXL (including the threshold voltage of the first transistor T1) can be extracted via the sensing line RLj described above. The extracted characteristic information can be used to convert image data, thereby compensating for characteristic deviations between the pixels PXL.

[0103] Figure 2 , the first transistor T1, the second transistor T2, and the third transistor T3 are all n-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 described above may be changed to a p-type transistor. Figure 2 , an embodiment in which the light emitting unit EMU is connected between the pixel circuit PXC and the second power line PL2 is disclosed, but the light emitting unit EMU may be connected between the first power line PL1 and the pixel circuit PXC.

[0104] The light emitting unit EMU may include a first stage SET1 (e.g., a first stack, a first sub-light emitting unit, etc.) and a second stage SET2 (e.g., a second stack, a second sub-light emitting unit, etc.) sequentially connected between a first power line PL1 and a second power line PL2. The light emitting unit EMU may include a first electrode EL1, a second electrode EL2, a third electrode EL3, and a fourth electrode EL4, and each of the first stage SET1 and the second stage SET2 may include a plurality of light emitting elements LD connected in parallel in the same direction between two electrodes among the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4.

[0105] The first stage SET1 may include a first electrode EL1 and a second electrode EL2 (or a first sub-intermediate electrode CTE-1), and may include at least one first light-emitting element LD1 connected between the first electrode EL1 and the second electrode EL2 (or the first sub-intermediate electrode CTE-1). In some embodiments, the first stage SET1 may include a reverse light-emitting element LDr connected between the first electrode EL1 and the second electrode EL2 (or the first sub-intermediate electrode CTE-1) in a direction opposite to the first light-emitting element LD1.

[0106] The second stage SET2 may include a fourth electrode EL4 (or a second sub-intermediate electrode CTE-2) and a third electrode EL3, and may include at least one second light-emitting element LD2 connected between the fourth electrode EL4 (or the second sub-intermediate electrode CTE-2) and the third electrode EL3. In some embodiments, the second stage SET2 may include a reverse light-emitting element LDr connected between the fourth electrode EL4 (or the second sub-intermediate electrode CTE-2) and the third electrode EL3 in a direction opposite to the second light-emitting element LD2.

[0107] The first sub-intermediate electrode CTE-1 of the first-stage SET1 and the second sub-intermediate electrode CTE-2 of the second-stage SET2 can be integrally provided and connected to each other. That is, the first sub-intermediate electrode CTE-1 and the second sub-intermediate electrode CTE-2 can constitute an intermediate electrode CTE for electrically connecting the consecutive first-stage SET1 and the second-stage SET2 (for example, connected in series with each other). When the first sub-intermediate electrode CTE-1 and the second sub-intermediate electrode CTE-2 are integrally provided, the first sub-intermediate electrode CTE-1 and the second sub-intermediate electrode CTE-2 can be different regions of the intermediate electrode CTE.

[0108] In the above-described embodiment, the first electrode EL1 may be the anode electrode of the light emitting unit EMU of each pixel PXL, and the third electrode EL3 may be the cathode electrode of the light emitting unit EMU of each pixel PXL.

[0109] As described above, the light emitting unit EMU of the pixel PXL including the light emitting elements LD connected in a series / parallel hybrid structure can easily adjust the driving current / voltage conditions according to the applied product specifications.

[0110] For example, the light emitting unit EMU of the pixel PXL including the light emitting elements LD connected in a series / parallel hybrid structure can reduce driving current compared to the light emitting unit EMU having a structure in which the light emitting elements LD are connected only in parallel.

[0111] As referenced above Figure 2 As described, the pixel PXL may include stages (eg, the first stage SET1 and the second stage SET2) connected in series as the light emitting unit EMU. In this way, the driving current of the pixel PXL may be reduced.

[0112] although Figure 2 The pixel PXL (or light emitting unit EMU) is shown to include two stages (ie, the first stage SET1 and the second stage SET2), but the present disclosure is not limited thereto. For example, the pixel PXL may include three or more stages, which will be referred to below. Figure 9 describe.

[0113] Figure 3 It shows Figure 2 A plan view of an example of a pixel. Figure 3 For convenience, the transistor connected to the light emitting element LD and the signal line connected to the transistor are omitted, and the focus is on the above reference Figure 2 The described light emitting unit EMU schematically illustrates a pixel PXL.

[0114] refer to Figure 2 and Figure 3 , the pixel PXL may be formed in the pixel area PXA on the substrate. The pixel area PXA may include an emission area EMA. According to an embodiment, the pixel PXL may include a bank BNK, and the emission area EMA may be surrounded by and defined by the bank BNK. Figure 3 As shown in FIG, the bank BNK may include a first opening OP1 and a second opening OP2 exposing the lower structure, and the emission area EMA may be defined by the first opening OP1 of the bank BNK. The second opening OP2 may be positioned spaced apart from the first opening OP1 in the pixel area PXA and may be positioned adjacent to one side (e.g., the lower side or the upper side) of the pixel area PXA.

[0115] The pixel PXL may include a first electrode EL1, a second electrode EL2, a third electrode EL3, and a fourth electrode EL4 that are physically separated or spaced apart from each other along the first direction DR1. The first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may be respectively connected to the electrodes 1 and 2 above. Figure 2 The first electrode EL1 , the second electrode EL2 , the third electrode EL3 , and the fourth electrode EL4 described correspond.

[0116] The first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may be arranged sequentially along a first direction DR1. Each of the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may extend in a second direction DR2 that intersects the first direction DR1. Ends of the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may be located within the second opening OP2 of the bank BNK. For reference, during the process of manufacturing the display device, the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may extend to adjacent pixel regions before the light-emitting element LD is supplied onto the substrate. After the light-emitting element LD is supplied and disposed in the pixel region PXA, the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may be separated from other electrodes (e.g., electrodes of adjacent pixels in the second direction DR2) at the second opening OP2. In other words, the second opening OP2 of the bank BNK may be provided to facilitate the process of separating the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4.

[0117] The first electrode EL1 may include a protrusion that protrudes toward the second electrode EL2 in the first direction DR1 in the emission area EMA. The protrusion of the first electrode EL1 may be provided to maintain a distance between the first electrode EL1 and the second electrode EL2 at an interval (e.g., a set or predetermined interval) in the emission area EMA. Similarly, the fourth electrode EL4 may include a protrusion that protrudes toward the third electrode EL3 in the emission area EMA in a direction opposite to the first direction DR1. The protrusion of the fourth electrode EL4 may be provided to maintain a distance between the third electrode EL3 and the fourth electrode EL4 at an interval (e.g., a set or predetermined interval) in the emission area EMA.

[0118] However, the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 are not limited thereto. For example, the shapes and / or mutual arrangement relationship of the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may be varied. For example, each of the first electrode EL1 and the fourth electrode EL4 may not include a protrusion and may have a curved shape.

[0119] The first electrode EL1 may be connected to the upper reference electrode through the first contact hole CNT1 Figure 2 The first transistor T1 described above, and the third electrode EL3 can be connected to the reference 1 through the second contact hole CNT2. Figure 2 The second power line PL2 is described.

[0120] Depending on the embodiment, each of the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may have a single-layer structure or a multi-layer structure. For example, the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may have a multi-layer structure including a reflective electrode and a conductive capping layer. In some embodiments, the reflective electrode may have a single-layer structure or a multi-layer structure. As an example, the reflective electrode may include at least one reflective conductive layer and, optionally, may further include at least one transparent conductive layer disposed above and / or below the reflective conductive layer.

[0121] According to an embodiment, the pixel PXL may include a first bank pattern BNKP1 overlapping an area of ​​the first electrode EL1, a second bank pattern BNKP2 overlapping an area of ​​the second electrode EL2, a third bank pattern BNKP3 overlapping an area of ​​the third electrode EL3, and a fourth bank pattern BNKP4 overlapping an area of ​​the fourth electrode EL4.

[0122] The first bank pattern BNKP1, the second bank pattern BNKP2, the third bank pattern BNKP3, and the fourth bank pattern BNKP4 may be spaced apart from each other in the first direction DR1 in the emission area EMA, and the region of each of the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may protrude upward. For example, the first electrode EL1 (or a protrusion of the first electrode EL1) may be disposed on the first bank pattern BNKP1 and may protrude in the third direction DR3 (i.e., the thickness direction of the substrate) through the first bank pattern BNKP1, the second electrode EL2 may be disposed on the second bank pattern BNKP2 and may protrude in the third direction DR3 through the second bank pattern BNKP2, the third electrode EL3 may be disposed on the third bank pattern BNKP3 and may protrude in the third direction DR3 through the third bank pattern BNKP3, and the fourth electrode EL4 (or a protrusion of the fourth electrode EL4) may be disposed on the fourth bank pattern BNKP4 and may protrude in the third direction DR3 through the fourth bank pattern BNKP4.

[0123] The pixel PXL may include a first light emitting element LD1 and a second light emitting element LD2. In some embodiments, the pixel PXL may further include the Figure 2 The reverse light emitting element LDr is described.

[0124] The first light emitting element LD1 may be provided between the first electrode EL1 and the second electrode EL2. A first end portion (or one end portion) of the first light emitting element LD1 may face the first electrode EL1, and a second end portion (or the other end portion) of the first light emitting element LD1 may face the second electrode EL2. When a plurality of first light emitting elements LD1 are provided, the first light emitting elements LD1 may be connected in parallel between the first electrode EL1 and the second electrode EL2, and may constitute the above reference Figure 2 The first level SET1 is described.

[0125] Similarly, the second light emitting element LD2 can be provided between the third electrode EL3 and the fourth electrode EL4. The first end of the second light emitting element LD2 can face the fourth electrode EL4, and the second end of the second light emitting element LD2 can face the third electrode EL3. The second end of the second light emitting element LD2 and the second end of the first light emitting element LD1 can include the same type of semiconductor layer (for example, a p-type semiconductor layer) and can face each other with the second electrode EL2 and the third electrode EL3 provided therebetween. When a plurality of second light emitting elements LD2 are provided, the second light emitting elements LD2 can be connected in parallel between the third electrode EL3 and the fourth electrode EL4, and can constitute the above reference Figure 2 The second level SET2 is described.

[0126] although Figure 3 The light emitting elements LD are shown aligned in the first direction DR1 between the first and second electrodes EL1 and EL2 and between the third and fourth electrodes EL3 and EL4, but the alignment direction of the light emitting elements LD is not limited thereto. For example, at least one of the light emitting elements LD may be arranged in a diagonal direction.

[0127] In an exemplary embodiment, the first end of the first light-emitting element LD1 is not directly disposed on the first electrode EL1, but may be electrically connected to the first electrode EL1 via at least one contact electrode (e.g., the first contact electrode CNE1). Similarly, the second end of the second light-emitting element LD2 is not directly disposed on the third electrode EL3, but may be electrically connected to the third electrode EL3 via at least one contact electrode (e.g., the second contact electrode CNE2). However, the present disclosure is not limited thereto. For example, the first end of the first light-emitting element LD1 may be in direct contact with the first electrode EL1 and may be electrically connected to the first electrode EL1.

[0128] According to an embodiment, each of the first light emitting element LD1 and the second light emitting element LD2 may be a light emitting diode having an ultra-small size (eg, a size as small as nanometer to micrometer) using a material having an inorganic crystal structure. Detailed structures of the light emitting elements LD will be referred to. Figure 15 and Figure 16Provide a detailed description.

[0129] According to an embodiment, the light-emitting element LD can be prepared in the form of being distributed in a solution (e.g., a set or predetermined solution) and can be supplied to the emission area EMA of the pixel area PXA by inkjet printing or slit coating. For example, the light-emitting element LD can be mixed with a volatile solvent and supplied to the emission area EMA. At this time, when a voltage (e.g., a set or predetermined voltage) is applied between the first electrode EL1 and the second electrode EL2 and between the third electrode EL3 and the fourth electrode EL4, an electric field is formed between the first electrode EL1 and the second electrode EL2 and between the third electrode EL3 and the fourth electrode EL4, and the light-emitting element LD is self-aligned between the first electrode EL1, the second electrode EL2, the third electrode EL3 and the fourth electrode EL4. After the light-emitting element LD is aligned, the solvent is volatilized or removed in any other way. Therefore, the light-emitting element LD can be stably arranged between the first electrode EL1 and the second electrode EL2 and between the third electrode EL3 and the fourth electrode EL4.

[0130] According to some embodiments, the pixel PXL may include a first contact electrode CNE1 , a second contact electrode CNE2 , and an intermediate electrode CTE.

[0131] The first contact electrode CNE1 may be formed on the first end portion of the first light emitting element LD1 and at least a region of the first electrode EL1 corresponding thereto, and may physically and / or electrically connect the first end portion of the first light emitting element LD1 to the first electrode EL1 .

[0132] The second contact electrode CNE2 may be formed on the second end of the second light emitting element LD2 and at least one region of the third electrode EL3 corresponding thereto, and may physically and / or electrically connect the second end of the second light emitting element LD2 to the third electrode EL3 .

[0133] The intermediate electrode CTE may include a first sub-intermediate electrode CTE-1 (or first intermediate electrode) and a second sub-intermediate electrode CTE-2 (or second intermediate electrode) extending in the second direction DR2. The first sub-intermediate electrode CTE-1 may be formed on the second end of the first light-emitting element LD1 and at least one region of the corresponding second electrode EL2. The intermediate electrode CTE may extend from the first sub-intermediate electrode CTE-1 to bypass the second contact electrode CNE2 or the second light-emitting element LD2, and the second sub-intermediate electrode CTE-2 may be formed on the first end of the second light-emitting element LD2 and at least one region of the corresponding fourth electrode EL4. The intermediate electrode CTE may electrically connect the second end of the first light-emitting element LD1 to the first end of the second light-emitting element LD2.

[0134] like Figure 3 As shown in , the intermediate electrode CTE may be spaced apart from the second contact electrode CNE2 and may have a closed loop shape surrounding the second contact electrode CNE2. Therefore, the second light emitting element LD2 may be connected in series to the first light emitting element LD1 through the intermediate electrode CTE.

[0135] As referenced above Figure 3 As described, the first light-emitting element LD1 and the second light-emitting element LD2 can be disposed between the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4, and the first light-emitting element LD1 and the second light-emitting element LD2 can be connected in series via the intermediate electrode CTE. In this manner, the light-emitting unit EMU of the pixel PXL can be configured by connecting the first light-emitting element LD1 and the second light-emitting element LD2 disposed in the pixel region PXA of the pixel PXL in a series structure.

[0136] Figure 4 It is shown in Figure 2 The waveform diagram of an example of the signal measured in the pixel. Figure 4 Signals for explaining the operation of the pixel PXL in the sensing mode are shown in . In the sensing mode, characteristics of the pixel PXL (eg, the threshold voltage of the first transistor T1 ) may be sensed.

[0137] refer to Figure 1 、 Figure 2 and Figure 4 , in the first period P1, the scan signal SC applied to the scan line SLi may have a pulse of a gate-on voltage level.

[0138] In this case, in the first period P1, the second transistor T2 may be turned on in response to the scan signal SC of the gate-on voltage level, and the data line DLj may be connected to the first node N1.

[0139] When a data signal Vdata (or a reference voltage) is applied to the data line DLj, the data signal Vdata may be applied to the first node N1. In this case, the data signal Vdata may have a voltage level for sensing the threshold voltage Vth of the first transistor T1. In an embodiment, the data signal Vdata may have a voltage level lower than the total operating voltage of the first stage SET1 (or the first light-emitting element LD1) and the second stage SET2 (or the second light-emitting element LD2). In this case, the operating voltage is the voltage required for the light-emitting element LD to emit light. The operating voltage may be, for example, the threshold voltage of the light-emitting element LD. In some embodiments, the data signal Vdata may have a voltage level higher than the operating voltage of each of the first stage SET1 (or the first light-emitting element LD1) and the second stage SET2 (or the second light-emitting element LD2). For example, when the operating voltage of each of the first and second light-emitting elements LD1 and LD2 is 2.5V, the data signal Vdata may have a voltage level of 4V, which is lower than 5V (=2.5V×2), based on the second power supply voltage VSS. However, the present disclosure is not limited to this. For example, the data signal Vdata may have a voltage level substantially equal to or similar to a total operating voltage of the first stage SET1 (or the first light emitting element LD1 ) and the second stage SET2 (or the second light emitting element LD2 ).

[0140] Similar to the scan signal SC, in the first period P1, the sensing scan signal SS applied to the sensing scan line SSLi may have a pulse of a gate-on voltage level. The waveform and phase of the sensing scan signal SS may be substantially the same as those of the scan signal SC.

[0141] In this case, in the first period P1 , the third transistor T3 may be turned on in response to the sensing scan signal SS of the gate-on voltage level, and the sensing line RLj may be connected to the second node N2 .

[0142] When the initialization voltage Vinit is applied from the sense driver 140 to the sense line RLj at the start of the first period P1, the initialization voltage Vinit may be applied to the second node N2. Therefore, the node voltage V_N2 (or V@N2) of the second node N2 may have a voltage level of the initialization voltage Vinit at the start of the first period P1. For example, the initialization voltage Vinit may have a voltage level of 2V.

[0143] Thereafter, the sensing driver 140 may cut off the supply of the initialization voltage Vinit until the first period P1 ends.

[0144] In this case, the first transistor T1 supplies a current corresponding to the gate-source voltage to the second node N2. Therefore, the node voltage V_N2 of the second node N2 can linearly increase to a specific voltage level (e.g., the first voltage level V1). For example, the node voltage V_N2 of the second node N2 can increase to the first voltage level V1 corresponding to the difference between the data signal Vdata and the threshold voltage Vth of the first transistor T1 (i.e., V1=Vdata-Vth).

[0145] Therefore, the sensing driver 140 may sense the threshold voltage Vth (or the node voltage V_N2 ) of the first transistor T1 .

[0146] In some embodiments, when the first voltage level V1 (or sensing voltage) measured in the first period P1 is within a reference range, the sensing driver 140 may set the stack quantity information of the pixel PXL to have a maximum value. In this case, the reference range may be less than the product of the total number of stages SET1 and SET2 and the operating voltage of the light-emitting element LD, and greater than the product of the number of stages SET1 and SET2 excluding one stage (i.e., the total number minus 1) and the operating voltage of the light-emitting element LD. For example, when there are two stages SET1 and SET2 and the operating voltage of the light-emitting element LD is 2.5V, the reference range may be less than 5V and greater than 2.5V. When the first voltage level V1 is approximately 3V, the first voltage level V1 is within the reference range, and therefore, the sensing driver 140 may set the stack quantity information of the pixel PXL to 2, which is the maximum value (i.e., the total number of stages SET1 and SET2).

[0147] Will refer to Figure 5 and Figure 6 A case is described where the stack quantity information is set to a value different from the maximum value (ie, a value smaller than the maximum value).

[0148] Figure 5 It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device. Figure 5 Shown with Figure 2 Corresponding circuit diagram. Figure 6 It is shown in Figure 5 Graph showing an example waveform of a signal measured in a pixel. Figure 6 Shown with Figure 4 The corresponding waveform diagram.

[0149] First, refer to Figure 2 and Figure 5 , except that the first light emitting element LD1 is defective, Figure 5 The pixel PXL_1 can be connected with Figure 2The pixels PXL are substantially the same or similar. Therefore, a redundant description thereof will not be repeated. The defect of the first light emitting element LD1 is an example, and for example, a defect may occur in the second light emitting element LD2 instead of the first light emitting element LD1.

[0150] For example, the first electrode EL1 and the second electrode EL2 may be Figure 5 In this case, the driving current flowing between the first electrode EL1 and the second electrode EL2 may flow through the first light emitting element LD1 having a defect (i.e., a short circuit), and the driving current may not flow through other first light emitting elements LD1 requiring an operating voltage.

[0151] For reference, when the first light-emitting element LD1 is open-circuited, the driving current may flow not only to the corresponding first light-emitting element LD1, but also through the other first light-emitting elements LD1. Therefore, the display quality may hardly be degraded. As the number of the first light-emitting elements LD1 increases, the open circuit of one first light-emitting element LD1 may have a small effect on the first stage SET1. In contrast, when the first light-emitting element LD1 is short-circuited, the first stage SET1 does not operate (or does not emit light), and the brightness of the pixel PXL_1 may be greatly reduced (for example, at a level of 1 / 2). When the same data signal Vdata is applied to Figure 2 Pixel PXL and Figure 5 When the pixel PXL_1 is Figure 5 The pixel PXL_1 can emit a signal with a ratio Figure 2 The brightness of the pixel PXL is low. When the display unit 110 (see Figure 1 ) includes multiple Figure 5 When the defective pixel PXL_1 (ie, the defective pixel PXL_1) is displayed, a luminance deviation may occur and the display quality may be deteriorated.

[0152] Therefore, the defective pixel PXL_1 is detected, and the defective pixel PXL_1 and other pixels PXL (see Figure 2 ) emits light with the same brightness, thereby preventing degradation of display quality.

[0153] In some embodiments, the measurement display unit 110 (see Figure 1) or a method of sensing the current flowing through the display unit 110 (or pixel PXL_1) makes it difficult to accurately determine whether a defect has occurred in each pixel PXL_1, or to accurately detect a defective pixel PXL_1. Therefore, the display device 100 according to an embodiment of the present disclosure can detect whether a defect (e.g., a short circuit that has a large impact on brightness changes) has occurred in the pixel PXL_1 based on the sensed threshold voltage Vth of the first transistor T1 (or the driving transistor).

[0154] refer to Figure 4 、 Figure 5 and Figure 6 , Figure 6 The scan signal SC, the sensing scan signal SS and the data signal Vdata shown in FIG can be respectively Figure 4 The scan signal SC, the sensing scan signal SS, and the data signal Vdata described are substantially the same or similar, and therefore, redundant descriptions thereof will not be repeated.

[0155] The initialization voltage Vinit is applied from the sensing driver 140 to the sensing line RLj at the start of the first period P1 , and the supply of the initialization voltage Vinit may be cut off until the end of the first period P1 .

[0156] In this case, the first transistor T1 supplies a current corresponding to the gate-source voltage to the second node N2. Therefore, the node voltage V_N2 of the second node N2 can increase linearly. However, when a defect occurs in the first light emitting element LD1, the node voltage V_N2 of the second node N2 can only increase to a second voltage level V2 lower than the first voltage level V1. This is because when Figure 5 When the first electrode EL1 and the second electrode EL2 are short-circuited as shown in FIG, when the node voltage V_N2 of the second node N2 becomes higher than the operating voltage of the second light-emitting element LD2 (or the second stage SET2) based on the second power supply voltage VSS, current flows through the second light-emitting element LD2 or leaks through the second light-emitting element LD2. Therefore, based on the second power supply voltage VSS, the second voltage level V2 can be equal to or similar to the operating voltage of the second light-emitting element LD2. For example, the second voltage level V2 can be approximately 2.5V.

[0157] When the second voltage level V2 measured in the first period P1 is within the reference range (ie, the above reference range Figure 4When the second voltage level V2 is outside the reference range described above, the sensing driver 140 may set the stack quantity information of the pixel PXL_1 to a value less than the maximum value (e.g., "maximum value minus 1"). For example, when the second voltage level V2 is approximately 2.5V and the reference range is greater than 2.5V and less than 5V, the second voltage level V2 is outside the reference range, and therefore, the sensing driver 140 may set the stack quantity information of the pixel PXL_1 to 1.

[0158] For reference, when defects occur in both the first light emitting element LD1 and the second light emitting element LD2, Figure 5 , the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 shown in FIG can be short-circuited, and the node voltage V_N2 of the second node N2 can be equal to the voltage level of the second power supply voltage VSS. Therefore, a complete defect (not a partial defect), that is, a non-functioning pixel PXL_1, can be detected. Because the stack quantity information of the non-functioning pixel PXL_1 (and the data compensation based thereon) is meaningless, the stack quantity information of the non-functioning pixel PXL_1 can be arbitrarily set (for example, set to 0). On the other hand, a repair operation can be performed on the non-functioning pixel PXL_1.

[0159] The case where the sensing driver 140 sets the stacking quantity information of the pixel PXL_1 (or the pixel PXL) based on whether the second voltage level V2 (or the first voltage level V1) is within the reference range has been described above, but the present disclosure is not limited thereto. For example, the sensing driver 140 may set the stacking quantity information based on whether the threshold voltage Vth or Vth_1 of the first transistor T1 of the pixel PXL_1 is within the normal range.

[0160] As referenced above Figures 4 to 6 As described, the display device 100 can determine whether a defect (for example, a short circuit having a large impact on brightness variation) has occurred in the pixel PXL or PXL_1 based on the sensed threshold voltage Vth or Vth_1 of the first transistor T1 (or the driving transistor) (or the sensed voltage level V1 or V2), and can set the stacking quantity information of the pixel PXL or PXL_1.

[0161] Figure 7 It is shown that the Figure 1 A diagram of an example of a lookup table of stack quantity information used in a display device.

[0162] refer to Figure 1 、 Figure 2 and Figure 7 , the lookup table LUT may include stacking quantity information INFO_S of each of the pixels PXL.

[0163] The lookup table LUT may include first stack quantity information INFO_S1 of the first pixel PXL1 located in the first row and the first column and second stack quantity information INFO_S2 of the second pixel PXL2 located in the first row and the second column.

[0164] When the value of the first stack number information INFO_S1 is 2, two of the two stages of the first pixel PXL1 may constitute an effective light source. The number of stages not participating in constituting the effective light source may be 0, which is given in brackets.

[0165] When the value of the second stack number information INFO_S2 is 1, only one of the two stages in the second pixel PXL2 may constitute an effective light source. The number of stages not participating in constituting the effective light source may be 1.

[0166] In another embodiment, the stacking number information INFO_S may indicate the number of some stages (eg, defective stages) that do not participate in constituting an effective light source among the stages of the pixel PXL.

[0167] Figure 8 It is used to describe the Figure 1 A diagram showing the operation of the compensator in the display device.

[0168] refer to Figure 1 、 Figure 7 and Figure 8 , the reference curve CURVE_REF (or reference conversion line), the first curve CURVE1 (or first conversion line), and the second curve CURVE2 (or second conversion line) may each represent a relationship between an input gray level GRAY_IN and an output gray level GRAY_OUT (or compensated gray level). In this case, the input gray level GRAY_IN may be included in the image data DATA2, and the output gray level GRAY_OUT may be included in the compensated data DATA3.

[0169] The value of the input grayscale GRAY_IN and the value of the output grayscale GRAY_OUT on the reference curve CURVE_REF may be equal to each other. For example, the first grayscale value GRAY1 of the input grayscale GRAY_IN on the reference curve CURVE_REF may correspond to the first grayscale value GRAY1 of the output grayscale GRAY_OUT.

[0170] The value of the output grayscale GRAY_OUT on the first curve CURVE1 can be smaller than the value of the input grayscale GRAY_IN. For example, the first grayscale value GRAY1 of the input grayscale GRAY_IN on the first curve CURVE1 can correspond to the first compensated grayscale value GRAY_C1 of the output grayscale GRAY_OUT, and the first compensated grayscale value GRAY_C1 can be smaller than the first grayscale value GRAY1. For example, the first compensated grayscale value GRAY_C1 can be 1 / 2 or 3 / 4 times the first grayscale value GRAY1.

[0171] The value of the output grayscale GRAY_OUT on the second curve CURVE2 can be greater than the value of the input grayscale GRAY_IN. For example, the first grayscale value GRAY1 of the input grayscale GRAY_IN on the second curve CURVE2 can correspond to the second compensated grayscale value GRAY_C2 of the output grayscale GRAY_OUT, and the second compensated grayscale value GRAY_C2 can be greater than the first grayscale value GRAY1. For example, the second compensated grayscale value GRAY_C2 can be twice or 1.5 times the first grayscale value GRAY1.

[0172] In some embodiments, the compensator 160 may select one of the reference curve CURVE_REF, the first curve CURVE1, and the second curve CURVE2 based on the stacking number information INFO_S, and may use the selected curve to compensate for the input grayscale GRAY_IN and generate the output grayscale GRAY_OUT (or compensated grayscale).

[0173] In an embodiment, when the first stack quantity information INFO_S1 of the first pixel PXL1 is greater than the second stack quantity information INFO_S2 of the second pixel PXL2, the compensator 160 may generate a first compensated grayscale value GRAY_C1 by reducing the grayscale value of the first pixel PXL1 based on the grayscale value of the second pixel PXL2. For example, the compensator 160 may generate the first compensated grayscale value GRAY_C1 by compensating the first grayscale value GRAY1 of the first pixel PXL1 using the first curve CURVE1. Alternatively, the compensator 160 may compensate the grayscale value of the second pixel PXL2 using the reference curve CURVE_REF, or may not compensate the grayscale value of the second pixel PXL2.

[0174] In this case, for the same brightness, the data signal Vdata (see FIG. 1 ) applied to the first pixel PXL1 corresponds to the first compensated grayscale value GRAY_C1. Figure 2) may become smaller than the data signal Vdata applied to the second pixel PXL2, and the driving current (or the amount of current) flowing through the first pixel PXL1 may become smaller than the driving current flowing through the second pixel PXL2.

[0175] In an embodiment, when the first stack quantity information INFO_S1 of the first pixel PXL1 is greater than the second stack quantity information INFO_S2 of the second pixel PXL2, the compensator 160 may generate a second compensated grayscale value GRAY_C2 by amplifying the grayscale value of the second pixel PXL2 based on the grayscale value of the first pixel PXL1. For example, the compensator 160 may generate the second compensated grayscale value GRAY_C2 by compensating the first grayscale value GRAY1 of the second pixel PXL2 using the second curve CURVE2. Alternatively, the compensator 160 may compensate the grayscale value of the first pixel PXL1 using the reference curve CURVE_REF, or may not compensate the grayscale value of the first pixel PXL1.

[0176] In this case, for the same brightness, the data signal Vdata applied to the second pixel PXL2 corresponding to the second compensated grayscale value GRAY_C2 can become larger than the data signal Vdata applied to the first pixel PXL1, and the driving current (or amount of current) flowing through the second pixel PXL2 can become larger than the driving current flowing through the first pixel PXL1.

[0177] In an embodiment, when the first stack quantity information INFO_S1 of the first pixel PXL1 is greater than the second stack quantity information INFO_S2 of the second pixel PXL2, the compensator 160 may generate a first compensated grayscale value GRAY_C1 by reducing the grayscale value of the first pixel PXL1, and generate a second compensated grayscale value GRAY_C2 by amplifying the grayscale value of the second pixel PXL2. For example, the compensator 160 may generate the first compensated grayscale value GRAY_C1 by compensating the first grayscale value GRAY1 of the first pixel PXL1 using a first curve CURVE1, and generate the second compensated grayscale value GRAY_C2 by compensating the first grayscale value GRAY1 of the second pixel PXL2 using a second curve CURVE2.

[0178] As referenced above Figure 8As described above, the compensator 160 can reduce the grayscale value of the first pixel PXL1 corresponding to the relatively large first stack quantity information INFO_S1, or can increase the grayscale value of the second pixel PXL2 corresponding to the relatively small second stack quantity information INFO_S2. Therefore, the data signal Vdata applied to the first pixel PXL1 and the corresponding driving current can be reduced, or the data signal Vdata applied to the second pixel PXL2 and the corresponding driving current can be increased, and the brightness difference between the first pixel PXL1 and the second pixel PXL2 can be improved.

[0179] Figure 9 It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device.

[0180] refer to Figure 1 、 Figure 2 and Figure 9 , the pixel PXL_2 includes a light emitting unit EMU_1 and a pixel circuit PXC. Because the pixel circuit PXC is the same as the above reference Figure 2 The described pixel circuits PXC are substantially the same, so a redundant description thereof will not be repeated.

[0181] The light emitting unit EMU_1 may include a plurality of light emitting elements LD connected in series / parallel between a first power line PL1 to which a first power supply voltage VDD is applied and a second power line PL2 to which a second power supply voltage VSS is applied.

[0182] The light emitting unit EMU_1 may include a third stage SET3 (or a third sub-light emitting unit), a first stage SET1_1 (or a first sub-light emitting unit), a second stage SET2_1 (or a second sub-light emitting unit), and a fourth stage SET4 (or a fourth sub-light emitting unit) sequentially connected between a first power line PL1 and a second power line PL2. The light emitting unit EMU_1 may include a first electrode EL1_1, a second electrode EL2_1, a third electrode EL3_1, a fourth electrode EL4_1, a fifth electrode EL5, a sixth electrode EL6, a seventh electrode EL7, and an eighth electrode EL8, and each of the first stage SET1_1, the second stage SET2_1, the third stage SET3, and the fourth stage SET4 may include a plurality of light emitting elements LD connected in parallel in the same direction between two of the first electrode EL1_1, the second electrode EL2_1, the third electrode EL3_1, the fourth electrode EL4_1, the fifth electrode EL5, the sixth electrode EL6, the seventh electrode EL7, and the eighth electrode EL8.

[0183] The first level SET1_1 and the second level SET2_1 can be respectively Figure 2The described first stage SET1 and second stage SET2 are substantially the same or similar.

[0184] The first stage SET1_1 may include a first electrode EL1_1 (or the (1-2)th intermediate electrode CTE1-2) and a second electrode EL2_1 (or the (2-1)th intermediate electrode CTE2-1), and may include at least one first light emitting element LD1 connected between the first electrode EL1_1 (or the (1-2)th intermediate electrode CTE1-2) and the second electrode EL2_1 (or the (2-1)th intermediate electrode CTE2-1).

[0185] The second stage SET2_1 may include a fourth electrode EL4_1 (or the (2-2) intermediate electrode CTE2-2) and a third electrode EL3_1 (or the (3-1) intermediate electrode CTE3-1), and may include at least one second light emitting element LD2 connected between the fourth electrode EL4_1 (or the (2-2) intermediate electrode CTE2-2) and the third electrode EL3_1 (or the (3-1) intermediate electrode CTE3-1).

[0186] The third stage SET3 may include fifth and sixth electrodes EL5 and EL6 (or (1-1)th intermediate electrode CTE1-1), and may include at least one third light emitting element LD3 connected between the fifth and sixth electrodes EL5 and EL6 (or (1-1)th intermediate electrode CTE1-1).

[0187] The fourth stage SET4 may include an eighth electrode EL8 (or (3-2)th intermediate electrode CTE3-2) and a seventh electrode EL7, and may include at least one fourth light emitting element LD4 connected between the eighth electrode EL8 (or (3-2)th intermediate electrode CTE3-2) and the seventh electrode EL7.

[0188] The (1-1)th intermediate electrode CTE1-1 of the third-stage SET3 and the (1-2)th intermediate electrode CTE1-2 of the first-stage SET1_1 may be integrally provided and connected to each other. That is, the (1-1)th intermediate electrode CTE1-1 and the (1-2)th intermediate electrode CTE1-2 may constitute the first intermediate electrode CTE1 for electrically connecting the consecutive third-stage SET3 and first-stage SET1_1. When the (1-1)th intermediate electrode CTE1-1 and the (1-2)th intermediate electrode CTE1-2 are integrally provided, the (1-1)th intermediate electrode CTE1-1 and the (1-2)th intermediate electrode CTE1-2 may be different regions of the first intermediate electrode CTE1.

[0189] Similarly, the (2-1)th intermediate electrode CTE2-1 of the first-stage SET1_1 and the (2-2)th intermediate electrode CTE2-2 of the second-stage SET2_1 may be integrally provided and connected to each other. That is, the (2-1)th intermediate electrode CTE2-1 and the (2-2)th intermediate electrode CTE2-2 may constitute a second intermediate electrode CTE2 for electrically connecting the consecutive first-stage SET1_1 and second-stage SET2_1.

[0190] Similarly, the (3-1)th intermediate electrode CTE3-1 of the second-stage SET2_1 and the (3-2)th intermediate electrode CTE3-2 of the fourth-stage SET4 may be integrally provided and connected to each other. That is, the (3-1)th intermediate electrode CTE3-1 and the (3-2)th intermediate electrode CTE3-2 may constitute a third intermediate electrode CTE3 for electrically connecting the consecutive second-stage SET2_1 and fourth-stage SET4.

[0191] In the embodiment described above, the fifth electrode EL5 may be the anode electrode of the light emitting unit EMU_1 of the pixel PXL_2 , and the seventh electrode EL7 may be the cathode electrode of the light emitting unit EMU_1 of the pixel PXL_2 .

[0192] As described above, the light emitting unit EMU_1 of the pixel PXL_2 including the light emitting elements LD connected in a series / parallel hybrid structure can easily adjust the driving current / voltage conditions according to the applied product specifications.

[0193] Figure 10 It shows Figure 9 A plan view of an example of a pixel. Figure 10 For convenience, the transistor connected to the light emitting element LD and the signal line connected to the transistor are omitted, and the focus is on the above reference Figure 9 The described light emitting unit EMU_1 schematically illustrates the pixel PXL_2.

[0194] refer to Figure 1 、 Figure 3 、 Figure 9 and Figure 10 , the pixel PXL_2 may be formed in the pixel area PXA on the substrate. The pixel area PXA may include an emission area EMA. According to an embodiment, the pixel PXL_2 may include a bank BNK, and the emission area EMA may be surrounded by and defined by the bank BNK. As has been mentioned above Figure 3 The bank BNK is described, so a redundant description thereof will not be repeated.

[0195] The pixel PXL_2 may include first, second, third, fourth, sixth, seventh, and eighth electrodes EL1_1, EL2_1, EL3_1, EL4_1, EL5, EL6, EL7, and EL8, which are physically separated or spaced apart from each other.

[0196] The first, second, third, and fourth electrodes EL1_1, EL2_1, EL3_1, and EL4_1 may be sequentially disposed in the first direction DR1 (or arranged along the first direction DR1) and each may extend in a second direction DR2 crossing the first direction DR1.

[0197] The fifth electrode EL5, the sixth electrode EL6, the seventh electrode EL7, and the eighth electrode EL8 may be spaced apart from the first electrode EL1_1, the second electrode EL2_1, the third electrode EL3_1, and the fourth electrode EL4_1 in the second direction DR2, respectively, and may be sequentially disposed in the first direction DR1 (or arranged along the first direction DR1). Each of the fifth electrode EL5, the sixth electrode EL6, the seventh electrode EL7, and the eighth electrode EL8 may extend in the second direction DR2.

[0198] One end of each of the first electrode EL1_1, the second electrode EL2_1, the third electrode EL3_1, and the fourth electrode EL4_1, and one end of each of the fifth electrode EL5, the sixth electrode EL6, the seventh electrode EL7, and the eighth electrode EL8 may terminate at an opening area OA within the emission area EMA. The opening area OA may correspond to the area center of the emission area EMA.

[0199] In a process for manufacturing a display device, before the light-emitting element LD is supplied on a substrate, the first electrode EL1_1, the second electrode EL2_1, the third electrode EL3_1, and the fourth electrode EL4_1 may be integrally provided with the fifth electrode EL5, the sixth electrode EL6, the seventh electrode EL7, and the eighth electrode EL8, respectively. After the light-emitting element LD is supplied and provided in the pixel area PXA, the first electrode EL1_1, the second electrode EL2_1, the third electrode EL3_1, and the fourth electrode EL4_1 may be separated from the fifth electrode EL5, the sixth electrode EL6, the seventh electrode EL7, and the eighth electrode EL8, respectively, in the opening area OA (and the second opening OP2 of the bank BNK).

[0200] Because the first electrode EL1_1, the second electrode EL2_1, the third electrode EL3_1 and the fourth electrode EL4_1 are symmetrical with the fifth electrode EL5, the sixth electrode EL6, the seventh electrode EL7 and the eighth electrode EL8 based on the opening area OA, the following description will focus on the fifth electrode EL5, the sixth electrode EL6, the seventh electrode EL7 and the eighth electrode EL8.

[0201] In the emission area EMA, the fifth electrode EL5 may have a shape that is curved in the first direction DR1 toward the sixth electrode EL6. The curved shape of the fifth electrode EL5 may be set to keep the distance between the fifth electrode EL5 and the sixth electrode EL6 at an interval (e.g., a set or predetermined interval) in the emission area EMA. Similarly, in the emission area EMA, the eighth electrode EL8 may have a shape that is curved in a direction opposite to the first direction DR1 toward the seventh electrode EL7. The curved shape of the eighth electrode EL8 may be set to keep the distance between the seventh electrode EL7 and the eighth electrode EL8 at an interval (e.g., a set or predetermined interval) in the emission area EMA. However, the fifth electrode EL5 and the eighth electrode EL8 are not limited thereto. For example, each of the fifth electrode EL5 and the eighth electrode EL8 may include the above reference Figure 3 Describe the protrusions instead of the curved shapes.

[0202] The fifth electrode EL5 can be connected to the Figure 9 The first transistor T1 in the embodiment of the present invention can be connected to the seventh electrode EL7 through the second contact hole CNT2. Figure 9 The second power line PL2 in.

[0203] The structure (eg, a single-layer structure or a multi-layer structure) of each of the first electrode EL1_1, the second electrode EL2_1, the third electrode EL3_1, the fourth electrode EL4_1, the fifth electrode EL5, the sixth electrode EL6, the seventh electrode EL7, and the eighth electrode EL8 may be the same as that described above with reference to FIG. Figure 3 The structures of the described first electrode EL1 , second electrode EL2 , third electrode EL3 , and fourth electrode EL4 are substantially the same or similar.

[0204] According to an embodiment, the pixel PXL_2 may include a first embankment pattern BNKP1_1 overlapping with an area of ​​the first electrode EL1_1 in the emission area EMA, a second embankment pattern BNKP2_1 overlapping with an area of ​​the second electrode EL2_1 in the emission area EMA, a third embankment pattern BNKP3_1 overlapping with an area of ​​the third electrode EL3_1 in the emission area EMA, a fourth embankment pattern BNKP4_1 overlapping with an area of ​​the fourth electrode EL4_1 in the emission area EMA, a fifth embankment pattern BNKP5 overlapping with an area of ​​the fifth electrode EL5 in the emission area EMA, a sixth embankment pattern BNKP6 overlapping with an area of ​​the sixth electrode EL6 in the emission area EMA, a seventh embankment pattern BNKP7 overlapping with an area of ​​the seventh electrode EL7 in the emission area EMA, and an eighth embankment pattern BNKP8 overlapping with an area of ​​the eighth electrode EL8 in the emission area EMA.

[0205] The first embankment pattern BNKP1_1, the second embankment pattern BNKP2_1, the third embankment pattern BNKP3_1, the fourth embankment pattern BNKP4_1, the fifth embankment pattern BNKP5, the sixth embankment pattern BNKP6, the seventh embankment pattern BNKP7 and the eighth embankment pattern BNKP8 can be spaced apart from each other in the emission area EMA, and can make the area of ​​each of the first electrode EL1_1, the second electrode EL2_1, the third electrode EL3_1, the fourth electrode EL4_1, the fifth electrode EL5, the sixth electrode EL6, the seventh electrode EL7 and the eighth electrode EL8 protrude in an upward direction (for example, in the thickness direction of the substrate).

[0206] The pixel PXL_2 may include a first light emitting element LD1, a second light emitting element LD2, a third light emitting element LD3 and a fourth light emitting element LD4. Figure 3 The described first light emitting element LD1 and second light emitting element LD2 are substantially the same or similar, so redundant descriptions thereof will not be repeated.

[0207] The third light emitting element LD3 may be provided between the fifth electrode EL5 and the sixth electrode EL6. The first end EP1 (or one end) of the third light emitting element LD3 may face the fifth electrode EL5, and the second end EP2 (or the other end) of the third light emitting element LD3 may face the sixth electrode EL6. When a plurality of third light emitting elements LD3 are provided, the plurality of third light emitting elements LD3 may be connected in parallel between the fifth electrode EL5 and the sixth electrode EL6, and may constitute the above reference Figure 9 The third level SET3 is described.

[0208] The fourth light emitting element LD4 may be disposed between the seventh electrode EL7 and the eighth electrode EL8. The first end EP1 of the fourth light emitting element LD4 may face the eighth electrode EL8, and the second end EP2 of the fourth light emitting element LD4 may face the seventh electrode EL7. The first end EP1 of the third light emitting element LD3 and the first end EP1 of the fourth light emitting element LD4 may include the same type of semiconductor layer (e.g., a p-type semiconductor layer). When a plurality of fourth light emitting elements LD4 are provided, the plurality of fourth light emitting elements LD4 may be connected in parallel between the seventh electrode EL7 and the eighth electrode EL8, and may constitute the structure described above with reference to FIG. Figure 9 The fourth level SET4 is described.

[0209] According to an embodiment, each of the first light emitting element LD1, the second light emitting element LD2, the third light emitting element LD3 and the fourth light emitting element LD4 may be a light emitting diode having an ultra-small size (e.g., as small as nanometer to micrometer size) using a material having an inorganic crystal structure.

[0210] According to some embodiments, the pixel PXL_2 may include a first contact electrode CNE1 , a second contact electrode CNE2 , a first intermediate electrode CTE1 , a second intermediate electrode CTE2 , and a third intermediate electrode CTE3 .

[0211] The first contact electrode CNE1 may be formed on the first end portion EP1 of the third light emitting element LD3 and at least one region of the fifth electrode EL5 corresponding thereto and may physically and / or electrically connect the first end portion EP1 of the third light emitting element LD3 to the fifth electrode EL5 .

[0212] The second contact electrode CNE2 may be formed on the second end portion EP2 of the fourth light emitting element LD4 and at least one region of the seventh electrode EL7 corresponding thereto and may physically and / or electrically connect the second end portion EP2 of the fourth light emitting element LD4 to the seventh electrode EL7.

[0213] The first intermediate electrode CTE1 may include a (1-1)th intermediate electrode CTE1-1 and a (1-2)th intermediate electrode CTE1-2 extending in the second direction DR2. The (1-1)th intermediate electrode CTE1-1 may be formed on the second end EP2 of the third light-emitting element LD3 and at least one region of the corresponding sixth electrode EL6. The first intermediate electrode CTE1 may extend from the sixth electrode EL6 (or the (1-1)th intermediate electrode CTE1-1) to the first electrode EL1_1 (or the (1-2)th intermediate electrode CTE1-2), and the (1-2)th intermediate electrode CTE1-2 may be formed on the first end of the first light-emitting element LD1 and at least one region of the corresponding first electrode EL1_1. The first intermediate electrode CTE1 may electrically connect the second end EP2 of the third light-emitting element LD3 to the first end of the first light-emitting element LD1.

[0214] The second intermediate electrode CTE2 may include a (2-1)th intermediate electrode CTE2-1 and a (2-2)th intermediate electrode CTE2-2 extending in the second direction DR2. The (2-1)th intermediate electrode CTE2-1 may be formed on the second end of the first light-emitting element LD1 and at least one region of the second electrode EL2_1 corresponding thereto. The second intermediate electrode CTE2 may extend from the second electrode EL2_1 (or the (2-1)th intermediate electrode CTE2-1) to bypass (e.g., detour) the (3-1)th intermediate electrode CTE3-1, and the (2-2)th intermediate electrode CTE2-2 may be formed on the first end of the second light-emitting element LD2 and at least one region of the fourth electrode EL4_1 corresponding thereto. The second intermediate electrode CTE2 may electrically connect the second end of the first light-emitting element LD1 to the first end of the second light-emitting element LD2.

[0215] The third intermediate electrode CTE3 may include a (3-1)th intermediate electrode CTE3-1 and a (3-2)th intermediate electrode CTE3-2 extending in the second direction DR2. The (3-1)th intermediate electrode CTE3-1 may be formed on the second end of the second light-emitting element LD2 and at least one region of the third electrode EL3_1 corresponding thereto. The third intermediate electrode CTE3 may extend from the third electrode EL3_1 (or the (3-1)th intermediate electrode CTE3-1) to the eighth electrode EL8 (or the (3-2)th intermediate electrode CTE3-2), and the (3-2)th intermediate electrode CTE3-2 may be formed on the first end EP1 of the fourth light-emitting element LD4 and at least one region of the eighth electrode EL8 corresponding thereto. The third intermediate electrode CTE3 may electrically connect the second end of the second light-emitting element LD2 to the first end EP1 of the fourth light-emitting element LD4.

[0216] Therefore, the third light emitting element LD3 , the first light emitting element LD1 , the second light emitting element LD2 , and the fourth light emitting element LD4 may be sequentially connected in series.

[0217] During each frame period, in the pixel PXL_2, the first driving current may flow from the fifth electrode EL5 to the seventh electrode EL7 through the third light emitting element LD3, the first intermediate electrode CTE1, the first light emitting element LD1, the second intermediate electrode CTE2, the second light emitting element LD2, the third intermediate electrode CTE3, and the fourth light emitting element LD4.

[0218] Figure 11 It is shown in Figure 9 Graph showing an example waveform of a signal measured in a pixel. Figure 11 Shown with Figure 4 and Figure 6 Corresponding waveform diagram.

[0219] refer to Figure 1 、 Figure 4 、 Figure 6 、 Figure 9 and Figure 11 , Figure 11 The scan signal SC, the sensing scan signal SS and the data signal Vdata shown in FIG can be respectively Figure 4 The scan signal SC, the sensing scan signal SS, and the data signal Vdata described are substantially the same or similar, and therefore, redundant descriptions thereof will not be repeated.

[0220] The data voltage or data signal Vdata may be set to be lower than the total operating voltage of the four stages SET1_1, SET2_1, SET3, and SET4, and may be set to be higher than the total operating voltage of three stages (i.e., excluding one stage from the four stages SET1_1, SET2_1, SET3, and SET4). For example, the data voltage or data signal Vdata may have a voltage level of approximately 9 V (i.e., a value less than 2.5 V (the operating voltage of each stage)×4).

[0221] The initialization voltage Vinit is applied from the sensing driver 140 to the sensing line RLj at the start of the first period P1 , and the supply of the initialization voltage Vinit may be cut off until the end of the first period P1 .

[0222] In this case, the first transistor T1 supplies a current corresponding to the gate-source voltage to the second node N2. Therefore, the node voltage V_N2 of the second node N2 may increase linearly.

[0223] When all the stages SET1_1, SET2_1, SET3, and SET4 of the pixel PXL_2 constitute an effective light source (ie, when a short circuit does not occur in the stages SET1_1, SET2_1, SET3, and SET4), the node voltage V_N2 of the second node N2 may increase to the first voltage level V1. Figure 4 As described, the node voltage V_N2 of the second node N2 may increase to the first voltage level V1 corresponding to the difference between the data signal Vdata and the threshold voltage Vth of the first transistor T1 (ie, V1 =Vdata-Vth).

[0224] When a short circuit occurs in one of the stages SET1_1, SET2_1, SET3, and SET4 of pixel PXL_2, the node voltage V_N2 of the second node N2 may only increase to the second voltage level V2. Because three of the stages SET1_1, SET2_1, SET3, and SET4 constitute an effective light source, the second voltage level V2 is equal to the total operating voltage of the three stages. For example, the second voltage level V2 may have a voltage level of 7.5 V (i.e., 2.5 V (the threshold voltage of each stage) × 3) based on the second power supply voltage VSS.

[0225] When a short circuit occurs in two of the stages SET1_1, SET2_1, SET3, and SET4 of pixel PXL_2, the node voltage V_N2 of the second node N2 may only increase to the third voltage level V3. Because the remaining two of the stages SET1_1, SET2_1, SET3, and SET4 constitute an effective light source, the third voltage level V3 is equal to the total operating voltage of the two stages. For example, the third voltage level V3 may have a voltage level of 5.0 V (i.e., 2.5 V (the threshold voltage of each stage) × 2) based on the second power supply voltage VSS.

[0226] When a short circuit occurs in three of the stages SET1_1, SET2_1, SET3, and SET4 of the pixel PXL_2, the node voltage V_N2 of the second node N2 may only increase to the fourth voltage level V4. Because the remaining one of the stages SET1_1, SET2_1, SET3, and SET4 constitutes an effective light source, the fourth voltage level V4 is equal to the operating voltage of one stage. For example, the fourth voltage level V4 may have a voltage level of 2.5V based on the second power supply voltage VSS.

[0227] When a short circuit occurs in all stages SET1_1, SET2_1, SET3, and SET4 of the pixel PXL_2, the second node N2 is connected to the second power line PL2. Therefore, a node voltage V_N2 of the second node N2 may be equal to the second power supply voltage VSS.

[0228] In some embodiments, the compensator 160 may set the stack quantity information of the pixel PXL_2 by comparing the voltage sensed in the first period P1 (or the sensed voltage) with a plurality of reference ranges.

[0229] In an embodiment, when the sensed voltage is within the first reference range, the compensator 160 may set the value of the stacking quantity information to a maximum first value. For example, assuming that the threshold voltage of each level is 2.5V, when the sensed voltage has a first voltage level V1 and the first reference range is greater than 7.5V and less than or equal to 10V, the value of the stacking quantity information may be set to 4, which is the maximum value.

[0230] In an embodiment, when the sensed voltage is within the second reference range, the compensator 160 may set the value of the stack quantity information to a second value smaller than the first value. For example, assuming that the threshold voltage of each stage is 2.5V, when the sensed voltage has a second voltage level V2 and the second reference range is greater than 5.0V and less than or equal to 7.5V, the value of the stack quantity information may be set to 3 smaller than the maximum value.

[0231] In an embodiment, when the sensed voltage is within a third reference range, the compensator 160 may set the value of the stack quantity information to a third value smaller than the second value. For example, assuming that the threshold voltage of each stage is 2.5V, when the sensed voltage has a third voltage level V3 and the third reference range is greater than 2.5V and less than or equal to 5.0V, the value of the stack quantity information may be set to 2.

[0232] In an embodiment, when the sensed voltage is within a fourth reference range, the compensator 160 may set the value of the stack quantity information to a fourth value smaller than the third value. For example, assuming that the threshold voltage of each stage is 2.5V, when the sensed voltage has a fourth voltage level V4 and the fourth reference range is greater than 0V and less than or equal to 2.5V, the value of the stack quantity information may be set to 1.

[0233] In an embodiment, when the sensed voltage is equal to the second power supply voltage VSS, the compensator 160 may set the value of the stack quantity information to 0.

[0234] As referenced above Figure 11 As described, the display device 100 can determine whether a defect (e.g., a short circuit having a large impact on brightness variation) has occurred in the pixel PXL_2 based on a sensing voltage obtained by sensing the threshold voltage of the first transistor T1 (or the driving transistor), and can set the stacking quantity information of the pixel PXL_2.

[0235] Figure 12 It is shown that the Figure 1FIG. 1 is a diagram of another example of a lookup table for stack quantity information used in a display device.

[0236] refer to Figure 1 、 Figure 9 and Figure 12 , the lookup table LUT_1 may include stacking quantity information INFO_S of each of the pixels PXL.

[0237] The lookup table LUT_1 may include first stack quantity information INFO_S1 of the first pixel PXL1 located in the first row and first column, second stack quantity information INFO_S2 of the second pixel PXL2 located in the first row and second column, third stack quantity information INFO_S3 of the pixel PXL located in the first row and third column, and fourth stack quantity information INFO_S4 of the pixel PXL located in the second row and third column.

[0238] When the value of the first stack number information INFO_S1 is 4, all four stages in the first pixel PXL1 may constitute an effective light source. The number of stages not participating in constituting an effective light source may be 0, which is given in brackets.

[0239] When the value of the second stack number information INFO_S2 is 3, only three of the four stages in the second pixel PXL2 may constitute an effective light source. The number of stages not participating in constituting the effective light source may be 1.

[0240] When the value of the third stack number information INFO_S3 is 2, only two of the four stages in the pixel PXL may constitute an effective light source. The number of stages not participating in constituting the effective light source may be two.

[0241] When the value of the fourth stack number information INFO_S4 is 1, only one of the four stages in the pixel PXL may constitute an effective light source. The number of stages not participating in constituting the effective light source may be three.

[0242] In an embodiment, the stacking number information INFO_S may indicate the number of some stages (eg, defective stages) that do not participate in constituting an effective light source among the stages of the pixel PXL.

[0243] On the other hand, the compensator 160 may determine the value of the stack quantity information INFO_S (or the lookup table LUT_1) based on the above reference Figure 8 The described reference curve CURVE_REF, the first curve CURVE1 and the second curve CURVE2 correspond to grayscale conversion formulas, and the grayscale conversion formulas may be used to compensate the input grayscale GRAY_IN to generate the output grayscale GRAY_OUT (or compensated grayscale).

[0244] Figure 13is a flowchart illustrating a method of driving a display device according to some embodiments of the present disclosure. Figure 14 It is shown that the Figure 13 A flowchart of an example of generating stack quantity information in a method.

[0245] refer to Figure 1 、 Figure 2 、 Figure 13 and Figure 14 , Figure 13 The method can be Figure 1 The display device 100 performs

[0246] As referenced above Figure 2 and Figure 9 As described, the display device 100 may include pixels PXL and PXL_2 , which may include a driving transistor (or first transistor T1 ) and a stage (or stack) connected to a first electrode of the driving transistor, and each of the stages may include at least one light emitting element LD.

[0247] Figure 13 The method may include applying a first voltage (or a reference voltage) to a gate electrode of a driving transistor of a pixel PXL (step S100).

[0248] As referenced above Figure 4 As described, when the scan signal SC has the gate-on voltage level in the first period P1 , the data voltage or data signal Vdata may be applied to the gate electrode of the driving transistor (ie, the first transistor T1 ).

[0249] The first voltage may be set to be lower than the total operating voltage of the stage so that the light emitting element LD in the stage does not emit light.

[0250] Figure 13 The method may measure or sense a second voltage applied to the first electrode of the driving transistor (ie, a node voltage V_N2 of the second node N2) in response to the first voltage (step S200).

[0251] As referenced above Figure 4 As described, the initialization voltage Vinit may be applied from the sensing driver 140 to the sensing line RLj at the start of the first period P1 , and then the supply of the initialization voltage Vinit from the sensing driver 140 may be cut off until the end of the first period P1 .

[0252] In this case, a current corresponding to the gate-source voltage of the driving transistor can be supplied to the second node (see Figure 2N2), and the node voltage V_N2 of the second node N2 may linearly increase. The node voltage V_N2 of the second node N2 may be sensed by the sense driver 140 at the end of the first period P1 or after the first period P1.

[0253] Figure 13 The method can generate stack quantity information based on the second voltage (step S300).

[0254] As referenced above Figure 4 、 Figure 6 and Figure 11 As described, the node voltage V_N2 of the second node N2 may have one of the first voltage level V1, the second voltage level V2, the third voltage level V3, and the fourth voltage level V4 according to the number of stages constituting an effective light source (or the number of defective stages) in the stage. The compensator 160 may compare the second voltage (i.e., the voltage sensed in the first period P1 or the sensed voltage) with a plurality of reference ranges and set the stacking number information of the pixel PXL.

[0255] In an embodiment, when the second voltage is within the first reference range, Figure 13 The method can set the value of the stack quantity information to the largest first value. Here, as mentioned above Figure 4 and Figure 11 As described, the first reference range may be set based on the total number of stages and the threshold voltage of the light emitting element LD.

[0256] In an embodiment, when the second voltage is outside the first reference range, Figure 13 The method can set the value of the stack quantity information to a second value that is smaller than the first value.

[0257] In some embodiments, Figure 13 The method can compare the second voltage with multiple reference ranges and set the stack quantity information.

[0258] refer to Figure 14 , Figure 13 The method can determine whether the second voltage is within the kth reference range (step S320). Here, the initial value of the constant k can be set to 1 (step S310).

[0259] When the second voltage is within the kth reference range, Figure 13 The method can determine that k-1 stacks are defective (step S330).

[0260] For example, as referenced above Figure 11As described, when the second voltage (eg, the first voltage level V1 ) is within the first reference range, it may be determined that 0 stacks are defective, and the stack quantity information may be set to have a first value (eg, 4).

[0261] When the second voltage is outside the kth reference range, Figure 13 The method may increase k (ie, k++) (step S340), and may determine again whether the second voltage is within the kth reference range (step S320).

[0262] For example, as referenced above Figure 11 As described, when the second voltage (eg, the second voltage level V2) is outside the first reference range, Figure 13 The method can again determine whether the second voltage is within the second reference range. In this way, Figure 13 The method may compare the second voltage with a plurality of reference ranges and set the stack quantity information based on the comparison result.

[0263] Return Reference Figure 13 , Figure 13 The method may set a data voltage applied to a gate electrode of a driving transistor based on the stacking number information (step S400).

[0264] As referenced above Figure 1 、 Figure 7 and Figure 8 As described above, when the first stack quantity information INFO_S1 of the first pixel PXL1 has a different value from the second stack quantity information INFO_S2 of the second pixel PXL2, the compensator 160 may compensate the first grayscale value of the first pixel PXL1 and the second grayscale value of the second pixel PXL2 differently for the same brightness. Therefore, the first data voltage applied to the first pixel PXL1 may be different from the second data voltage applied to the second pixel PXL2.

[0265] In an embodiment, as the value of the second stack quantity information INFO_S2 of the second pixel PXL2 decreases, the second data voltage for the same brightness may increase, and the driving current (or total driving current) flowing through the light-emitting element LD of the second pixel PXL2 may increase. That is, as the value of the second stack quantity information INFO_S2 of the second pixel PXL2 decreases, the second grayscale value of the second pixel PXL2 may be greatly compensated compared to the first grayscale value of the first pixel PXL1, the second data voltage increases according to the relatively large second grayscale value (i.e., the second compensated grayscale value), and the driving current corresponding to the second data voltage may increase.

[0266] In an embodiment, when the first stack quantity information INFO_S1 of the first pixel PXL1 has a value greater than the second stack quantity information INFO_S2 of the second pixel PXL2, the compensator 160 may generate a first compensated grayscale value by reducing the first grayscale value of the first pixel PXL1 based on the second grayscale value of the second pixel PXL2.

[0267] In an embodiment, when the first stack quantity information INFO_S1 of the first pixel PXL1 has a value greater than the second stack quantity information INFO_S2 of the second pixel PXL2, the compensator 160 may generate a second compensated grayscale value by amplifying the second grayscale value of the second pixel PXL2 based on the first grayscale value of the first pixel PXL1.

[0268] In an embodiment, when the first stack quantity information INFO_S1 of the first pixel PXL1 has a value greater than the value of the second stack quantity information INFO_S2 of the second pixel PXL2, the compensator 160 can generate a first compensated grayscale value by reducing the first grayscale value of the first pixel PXL1, and can generate a second compensated grayscale value by amplifying the second grayscale value of the second pixel PXL2.

[0269] Right now, Figure 13 The method may reduce the first grayscale value of the first pixel PXL1 corresponding to the relatively large first stack number information INFO_S1, or may increase the second grayscale value of the second pixel PXL2 corresponding to the relatively small second stack number information INFO_S2.

[0270] Therefore, the data voltage applied to the first pixel PXL1 and the driving current corresponding thereto can be reduced, or the data voltage applied to the second pixel PXL2 and the driving current corresponding thereto can be increased, and the brightness difference between the first pixel PXL1 and the second pixel PXL2 caused by the difference in the number of stacks (i.e., the difference deviation in the number of levels constituting the effective light source) can be improved.

[0271] Figure 15 It is shown in Figure 1 A schematic perspective view of a light-emitting element used as a light source in a display device. Figure 16 yes Figure 15 A cross-sectional view of a light-emitting element.

[0272] In the embodiments of the present disclosure, the type and / or shape of the light emitting element is not limited to Figure 15 and Figure 16 The embodiment shown in .

[0273] refer to Figure 15 and Figure 16The light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light emitting element LD may implement a light emitting stack in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked.

[0274] The light-emitting element LD can be provided in a shape extending in one direction. When the extension direction of the light-emitting element LD is the longitudinal direction, the light-emitting element LD can include one end (or lower end) and the other end (or upper end) in the extension direction. Any one of the first semiconductor layer 11 and the second semiconductor layer 13 can be provided at one end (or lower end) of the light-emitting element LD, and the remaining one of the first semiconductor layer 11 and the second semiconductor layer 13 can be provided at the other end (or upper end) of the light-emitting element LD. For example, the first semiconductor layer 11 can be provided at one end (or lower end) of the light-emitting element LD, and the second semiconductor layer 13 can be provided at the other end (or upper end) of the light-emitting element LD.

[0275] The light emitting element LD can be provided in various shapes. For example, the light emitting element LD can have a rod-like shape or a bar-like shape that is long in the longitudinal direction (i.e., the aspect ratio is greater than 1). In an embodiment of the present disclosure, the length L of the light emitting element LD in the longitudinal direction can be greater than its diameter D (or the width of the cross section). Such a light emitting element LD can include, for example, a light emitting diode (LED) manufactured with a very small size having a diameter D and / or length L of about micrometer or nanometer order.

[0276] The diameter D of the light-emitting element LD may be about 0.5 μm to about 5 μm, and the length L of the light-emitting element LD may be about 1 μm to about 10 μm. However, the diameter D and the length L of the light-emitting element LD are not limited thereto, and the size of the light-emitting element LD may be changed to meet the requirements (or design conditions) of the lighting device or self-luminous display device to which the light-emitting element LD is applied.

[0277] The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include a semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as Si, Ge, and Sn. However, the material forming the first semiconductor layer 11 is not limited thereto, and the first semiconductor layer 11 may be formed using various other materials. In an embodiment of the present disclosure, the first semiconductor layer 11 may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant). The first semiconductor layer 11 may include an upper surface in contact with the active layer 12 in the direction of the length L of the light-emitting element LD and a lower surface exposed to the outside. The lower surface of the first semiconductor layer 11 may be one end (or lower end) of the light-emitting element LD.

[0278] The active layer 12 may be disposed on the first semiconductor layer 11 and may be formed in a single quantum well structure or a multi-quantum well structure. For example, when the active layer 12 is formed in a multi-quantum well structure, the active layer 12 may include a barrier layer, a strain enhancement layer, and a well layer that are periodically and repeatedly stacked as a unit. The strain enhancement layer has a lattice constant smaller than that of the barrier layer, thereby further enhancing the strain applied to the well layer, such as compressive strain. However, the structure of the active layer 12 is not limited to the embodiment described above.

[0279] The active layer 12 can emit light having a wavelength of 400nm to 900nm, and a double heterostructure can be used. In an embodiment of the present disclosure, a cladding layer (not shown) doped with a conductive dopant can be formed above and / or below the active layer 12 in the direction of the length L of the light emitting element LD. For example, the cladding layer can be formed using an AlGaN layer or an InAlGaN layer. Depending on the embodiment, materials such as AlGaN or InAlGaN can be used to form the active layer 12. However, the material constituting the active layer 12 is not limited thereto, and various other materials can constitute the active layer 12. The active layer 12 may include a first surface in contact with the first semiconductor layer 11 and a second surface in contact with the second semiconductor layer 13.

[0280] When an electric field corresponding to a voltage (e.g., a set or predetermined voltage or greater) is applied between both ends of the light-emitting element LD, electron-hole pairs are recombined in the active layer 12, causing the light-emitting element LD to emit light. By controlling the light emission of the light-emitting element LD using this principle, the light-emitting element LD can be used as a light source (or light emitting source) for various light-emitting devices including pixels of a display device.

[0281] The second semiconductor layer 13 may be disposed on the second surface of the active layer 12 and may include a semiconductor layer of a different type from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as Mg. However, the material forming the second semiconductor layer 13 is not limited thereto, and the second semiconductor layer 13 may be formed using various other materials. In an embodiment of the present disclosure, the second semiconductor layer 13 may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant). The second semiconductor layer 13 may include a lower surface in contact with the second surface of the active layer 12 in the direction of the length L of the light-emitting element LD and an upper surface exposed to the outside. Here, the upper surface of the second semiconductor layer 13 may be the other end (or upper end) of the light-emitting element LD.

[0282] In an embodiment of the present disclosure, the first semiconductor layer 11 and the second semiconductor layer 13 may have different thicknesses in the direction of the length L of the light emitting element LD. For example, the first semiconductor layer 11 may have a thickness relatively greater than that of the second semiconductor layer 13 in the direction of the length L of the light emitting element LD. Therefore, the active layer 12 of the light emitting element LD may be positioned closer to the upper surface of the second semiconductor layer 13 than to the lower surface of the first semiconductor layer 11.

[0283] Although each of the first semiconductor layer 11 and the second semiconductor layer 13 is shown as including one layer, the present disclosure is not limited thereto. In an embodiment of the present disclosure, each of the first semiconductor layer 11 and the second semiconductor layer 13 may further include at least one layer, such as a cladding layer and / or a tensile strain barrier reduction (TSBR) layer, depending on the material of the active layer 12. The TSBR layer may be a strain relief layer that is provided between semiconductor layers having different lattice structures and serves as a buffer for reducing the difference in lattice constants. The TSBR layer may include a p-type semiconductor layer such as p-GaInP, p-AlInP, or p-AlGaInP, but the present disclosure is not limited thereto.

[0284] According to an embodiment, in addition to the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 described above, the light emitting element LD may further include an additional electrode (not shown) (hereinafter referred to as a "first additional electrode") provided on the second semiconductor layer 13. In an embodiment, another additional electrode (hereinafter referred to as a "second additional electrode") provided at one end of the first semiconductor layer 11 may be further included.

[0285] Each of the first additional electrode and the second additional electrode may be an ohmic contact electrode, but the present disclosure is not limited thereto. According to an embodiment, each of the first additional electrode and the second additional electrode may be a Schottky contact electrode. Each of the first additional electrode and the second additional electrode may include a conductive material (or substance). For example, each of the first additional electrode and the second additional electrode may include an opaque metal such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), and oxides or alloys thereof, used alone or in combination, but the present disclosure is not limited thereto. According to an embodiment, each of the first additional electrode and the second additional electrode may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (ITZO), or indium tin zinc oxide (ITZO).

[0286] The materials included in the first and second additional electrodes may be the same as or different from each other. The first and second additional electrodes may be substantially transparent or translucent. Therefore, light generated by the light-emitting element LD can be transmitted through the first and second additional electrodes and emitted to the outside of the light-emitting element LD. According to an embodiment, when light generated by the light-emitting element LD is emitted to the outside of the light-emitting element LD through areas other than the two end portions of the light-emitting element LD without being transmitted through the first and second additional electrodes, each of the first and second additional electrodes may include an opaque metal.

[0287] In an embodiment of the present disclosure, the light emitting element LD may further include an insulating film 14. However, according to some embodiments, the insulating film 14 may be omitted or may be provided to cover only a portion of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0288] The insulating film 14 can prevent the occurrence of electrical short circuits that may occur when the active layer 12 contacts conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 13. In some embodiments, the insulating film 14 can reduce or minimize surface defects of the light-emitting element LD, thereby improving the lifespan and luminous efficiency of the light-emitting element LD. In some embodiments, when multiple light-emitting elements LD are closely arranged, the insulating film 14 can prevent the occurrence of undesirable short circuits that may occur between the light-emitting elements LD. Whether or not the insulating film 14 is provided is not limited, as long as the active layer 12 can prevent the occurrence of short circuits with external conductive materials.

[0289] The insulating film 14 may be provided to completely surround the outer peripheral surface of the light emitting stack including the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 .

[0290] In the embodiment described above, the insulating film 14 is described as completely surrounding the outer peripheral surface of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, but the present disclosure is not limited thereto. According to an embodiment, when the light-emitting element LD includes a first additional electrode, the insulating film 14 may completely surround the outer peripheral surface of each of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the first additional electrode. In an embodiment, the insulating film 14 may not completely surround the outer peripheral surface of the first additional electrode, or may surround only a portion of the outer peripheral surface of the first additional electrode and may not surround the other portions of the outer peripheral surface of the first additional electrode. In an embodiment, when the first additional electrode is provided at the other end (or upper end) of the light-emitting element LD and the second additional electrode is provided at one end (or lower end) of the light-emitting element LD, the insulating film 14 may expose at least one region of each of the first and second additional electrodes.

[0291] The insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include a transparent insulating material made of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (AlO x ) and titanium dioxide (TiO 2 ) group consisting of one or more insulating materials, but the present disclosure is not limited thereto. Various materials having insulating properties can be used as the material of the insulating film 14.

[0292] The light-emitting element LD described above can be used as a light source for various display devices. The light-emitting element LD can be manufactured by a surface treatment process. For example, when a plurality of light-emitting elements LD are mixed with a liquid solution (or solvent) and supplied to each pixel area (e.g., the light-emitting area of ​​each pixel or the light-emitting area of ​​each sub-pixel), each of the light-emitting elements LD can be surface-treated so that the light-emitting element LD is evenly sprayed without unevenly agglomerating in the solution.

[0293] The light-emitting unit (or light-emitting device) including the light-emitting element LD described above can be used in various types of electronic devices (including display devices) that require a light source. For example, when a plurality of light-emitting elements LD are arranged in a pixel area of ​​each pixel of a display panel, the light-emitting element LD can be used as a light source for each pixel. However, the application field of the light-emitting element LD is not limited to the example described above. For example, the light-emitting element LD can be used in other types of electronic devices that require a light source, such as a lighting device.

[0294] While the present disclosure has been described with reference to various embodiments, it will be understood by those skilled in the relevant art that the present disclosure can be variously modified and varied without departing from the spirit and scope of the present disclosure as set forth in the following claims.

[0295] Therefore, the technical scope of the present disclosure should not be limited to the contents described in the detailed description of the present disclosure, but should be determined by the appended claims.

Claims

1. A display device comprising: a display unit comprising pixels, wherein each of the pixels comprises stacks connected in series, and each of the stacks comprises light emitting elements connected in parallel; a memory storing a plurality of pieces of stacking number information, wherein each of the plurality of pieces of stacking number information indicates the number of stacks constituting an effective light source in the stack for each of the pixels; a compensator that generates compensation data by compensating the image data based on the plurality of pieces of stacking amount information; and a data driver that generates a data voltage based on the compensation data and provides the data voltage to the display unit, The pixel is configured to emit light having a brightness corresponding to the data voltage.

2. The display device according to claim 1, wherein The pixels include a first pixel and a second pixel, wherein the first stacking quantity information of the first pixel has a value different from a value of the second stacking quantity information of the second pixel, and The first data voltage applied to the first pixel for the same brightness as the second pixel is different from the second data voltage applied to the second pixel.

3. The display device according to claim 2, wherein: As the value of the second stack number information decreases, the second data voltage for the same luminance as the first pixel and the driving current of the light emitting element among the light emitting elements of the second pixel increase.

4. The display device according to claim 2, wherein When the value of the first stacking quantity information is greater than the value of the second stacking quantity information, the compensator is configured to generate a first compensated grayscale value by reducing the first grayscale value of the first pixel based on the second grayscale value of the second pixel, wherein the image data includes the first grayscale value and the second grayscale value, and Wherein, the compensation data includes the first compensated grayscale value.

5. The display device according to claim 2, wherein When the value of the first stack quantity information is greater than the value of the second stack quantity information, the compensator is configured to generate a second compensated grayscale value by amplifying a second grayscale value of the second pixel based on a first grayscale value of the first pixel, wherein the image data includes the first grayscale value and the second grayscale value, and Wherein, the compensation data includes the second compensated grayscale value. The display device according to claim 1 , wherein: Each of the pixels includes two of the stacks.

7. The display device according to claim 6, wherein: Each of the pixels further comprises: a driving transistor connected between the first power line and the second power line; a switching transistor connected between the data line and the gate electrode of the driving transistor; a sensing transistor connected between one electrode of the driving transistor and a sensing line; and a storage capacitor connected between the gate electrode of the driving transistor and the one electrode of the driving transistor, and The stack is connected between the one electrode of the driving transistor and the second power line.

8. The display device according to claim 7, wherein: The compensator is for setting the plurality of pieces of stack quantity information based on a sensing voltage obtained by sensing a voltage applied to the one electrode of the driving transistor in response to a reference voltage applied to the gate electrode of the driving transistor.

9. The display device according to claim 8, wherein When the sensing voltage is within a reference range, the compensator is configured to set corresponding stack quantity information among the plurality of pieces of stack quantity information to have a maximum value.

10. The display device according to claim 8, wherein The compensator is configured to set corresponding pieces of stack quantity information among the plurality of pieces of stack quantity information to have a value smaller than a maximum value when the sensing voltage is outside a reference range.

11. The display device according to claim 10, wherein: The sensing voltage is equal to a value obtained by multiplying a threshold voltage of a light emitting element among the light emitting elements by the value of the corresponding stacking quantity information.

12. The display device according to claim 1, wherein Each of the pixels includes four of the stacks.

13. A method of driving a display device comprising pixels, wherein: Each of the pixels includes a driving transistor and a stack of first electrodes connected in series to the driving transistor, and each of the stacks includes light emitting elements connected in parallel, the method comprising: applying a first voltage to the gate electrode of the driving transistor; measuring a second voltage applied to the first electrode of the drive transistor in response to the first voltage; generating stack number information based on the second voltage, wherein the stack number information indicates the number of stacks constituting an effective light source in the stack for each of the pixels; and A data voltage applied to the gate electrode of the driving transistor is set based on the stacking number information.

14. The method according to claim 13, wherein Generating the stack quantity information includes: When the second voltage is within a first reference range, the stack quantity information is set to have a first value.

15. The method according to claim 14, wherein The first reference range is set based on the total number of the stacks and a threshold voltage of a light emitting element among the light emitting elements.

16. The method according to claim 14, wherein Generating the stack quantity information further includes: When the second voltage is outside the first reference range, the stack quantity information is set to have a second value smaller than the first value.

17. The method of claim 13, wherein: The pixels include a first pixel and a second pixel, The first stacking number information of the first pixel has a value different from a value of the second stacking number information of the second pixel, and A first data voltage applied to the first pixel for the same brightness as the second pixel is different from a second data voltage applied to the second pixel.

18. The method according to claim 17, wherein: As the value of the second stack number information decreases, the second data voltage for the same luminance as the first pixel and the driving current of the light emitting element among the light emitting elements of the second pixel increase.

19. The method according to claim 17, wherein Setting the data voltage includes: generating a first compensated grayscale value by scaling down a first grayscale value of the first pixel based on a second grayscale value of the second pixel when the value of the first stack quantity information is greater than the value of the second stack quantity information; and The first data voltage for the first pixel is generated based on the first compensated grayscale value.

20. The method according to claim 17, wherein Setting the data voltage includes: generating a second compensated grayscale value by amplifying a second grayscale value of the second pixel based on a first grayscale value of the first pixel when the value of the first stack quantity information is greater than the value of the second stack quantity information; and The second data voltage for the second pixel is generated based on the second compensated grayscale value.

Images