Display substrate and display panel

Abstract

A display substrate and a display panel, the display substrate comprising a first gate drive circuit and a second gate drive circuit respectively arranged on opposite first and second sides of a display area; the first gate scan drive circuit comprises a plurality of first shift register units, each first shift register unit comprising a first thin film transistor, the first thin film transistor comprising a first active layer, the first active layer comprising a metal oxide semiconductor material; the second gate scan drive circuit comprises a plurality of second shift register units, each second shift register unit comprising a second thin film transistor having the same function as the first thin film transistor, the second thin film transistor comprising a second active layer, the second active layer comprising a metal oxide semiconductor material; an average on-current of at least one first thin film transistor is I on1 , an average on-current of at least one second thin film transistor is I on2 , I on1 > I on2 . The display substrate is simpler to manufacture and has better display effect.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a display substrate and a display panel. BACKGROUND

[0002] With the gradual development of display technology and manufacturing technology, large-size display devices are gradually applied in various aspects of life to meet people's growing visual needs. For example, for display panels of 50 inches or more, even 100 inches or more, display uniformity is an important indicator for evaluating the display effect. In the production process, display uniformity affects key indicators such as product performance and yield. SUMMARY

[0003] At least one embodiment of the present disclosure provides a display substrate, which includes a substrate and a first gate drive circuit and a second gate drive circuit disposed on the substrate, wherein the display substrate includes a display area, and the first gate drive circuit and the second gate drive circuit are respectively disposed on a first side and a second side of the display area opposite to each other; the first gate scan drive circuit includes a plurality of first shift register units arranged along a first direction, each of the plurality of first shift register units includes a first thin film transistor having a first function in the first gate drive circuit, the first thin film transistor includes a first active layer, and the first active layer includes a metal oxide semiconductor material; the second gate scan drive circuit includes a plurality of second shift register units arranged along the first direction, each of the plurality of second shift register units includes a second thin film transistor having the same function as the first thin film transistor, the second thin film transistor includes a second active layer, and the second active layer includes a metal oxide semiconductor material; an average on-current of the first thin film transistor of at least one first shift register unit of the plurality of first shift register units is I on1 , an average on-current of the second thin film transistor of at least one second shift register unit of the plurality of second shift register units is I on2 , and I on1 > I on2 .

[0004] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first thin film transistor and the second thin film transistor are output transistors for outputting signals, input transistors for inputting signals, or reset transistors.

[0005] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the display region includes a plurality of sub-pixels and a scan line connected to the plurality of sub-pixels, the first thin film transistor and the second thin film transistor are output transistors configured to provide a gate scanning signal to the scan line of the plurality of sub-pixels; the scan line extends along a second direction, the second direction is substantially perpendicular to the first direction; the first side and the second side are opposite to each other in the second direction.

[0006] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the scan line extends along a second direction, the second direction is substantially perpendicular to the first direction; the first side and the second side are opposite to each other in the second direction.

[0007] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, I on1 -I on2 <I on2 ×20%.

[0008] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, I on1 -I on2 <I on2 ×10%.

[0009] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the second side has a first region, a second region and a third region arranged in sequence along the first direction, the average on-current of the plurality of second thin film transistors located in the first region is I on21 , the average on-current of the plurality of second thin film transistors located in the second region is I on22 , the average on-current of the plurality of second thin film transistors located in the third region is I on23 , I on21 >I on22 , and I on23 >I on22 .

[0010] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, when the gate voltage Vg of the plurality of first thin film transistors is 10V-20V, the on-current of the plurality of first thin film transistors and the on-current of the plurality of second thin film transistors are both greater than 1200μA.

[0011] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, when the gate voltage Vg of the plurality of first thin film transistors is 10V-20V, the maximum value of the on-current of the plurality of first thin film transistors is I on1MAX , the minimum value of the on-current of the plurality of first thin film transistors is I on1MIN , Ion1MAX -I on1MIN ≤1000μA; when the gate voltage Vg of the plurality of second thin-film transistors is 10V-20V, the maximum value of the turn-on current of the plurality of second thin-film transistors is I. on2MAX The minimum turn-on current of the plurality of second thin-film transistors is I. on2MIN I on2MAX -I on2MIN ≤1000μA.

[0012] For example, in the display substrate provided in at least one embodiment of this disclosure, the maximum value of the turn-on current in the plurality of first thin-film transistors of the plurality of first shift register units and the plurality of second thin-film transistors of the plurality of second shift register units is I. onMAX The maximum value is I onMIN Set 3δ1=(I onMAX -I onMIN ) / (I onMAX +I onMIN ), then: 3δ1=50~700.

[0013] For example, in a display substrate provided in at least one embodiment of this disclosure, both the first thin-film transistor and the second thin-film transistor are reset transistors, and the gate of the reset transistor is connected to a reset control signal terminal.

[0014] For example, in at least one embodiment of the display substrate provided in this disclosure, I on1 -I on2 <I on2 ×30%.

[0015] For example, in at least one embodiment of the display substrate provided in this disclosure, I on1 -I on2 <I on2 ×20%.

[0016] For example, in the display substrate provided in at least one embodiment of this disclosure, the maximum value of the turn-on current in the plurality of first thin-film transistors of the plurality of first shift register units and the plurality of second thin-film transistors of the plurality of second shift register units is I. onMAX The minimum value is I onMIN Set 3δ1=(I onMAX -I onMIN ) / (I onMAX +I onMIN ), then: 3δ1=50~700.

[0017] For example, in a display substrate provided in at least one embodiment of this disclosure, the average threshold voltage of the plurality of first thin-film transistors in the plurality of first shift register units is V. th1, the average threshold voltage of the plurality of second thin film transistors of the plurality of second shift register units is V th2 , and V th1 > V th2 .

[0018] For example, in the display substrate provided by at least one embodiment of the present disclosure, V th1 - V th2 < |V th2 | x 30%.

[0019] For example, in the display substrate provided by at least one embodiment of the present disclosure, when the source-drain input voltage Vd of the plurality of first thin film transistors is 10V-20V, and the on current Id is 10 -8 A, |V th1 | < 2V, and |V th2 | < 2V.

[0020] For example, in the display substrate provided by at least one embodiment of the present disclosure, the maximum value of the threshold voltage of the plurality of first thin film transistors is V th1MAX , the minimum value of the threshold voltage of the plurality of first thin film transistors is V th1MIN , and V th1MAX - V th1MIN ≤ 2V; the maximum value of the threshold voltage of the plurality of second thin film transistors is V th2MAX , the minimum value of the threshold voltage of the plurality of second thin film transistors is V th2MIN , and V th2MAX - V th2MIN ≤ 2V.

[0021] For example, in the display substrate provided by at least one embodiment of the present disclosure, the maximum value of the threshold voltage of the plurality of first thin film transistors of the plurality of first shift register units and the plurality of second thin film transistors of the plurality of second shift register units is V thMAX , and the minimum value is V thMIN , 3δ2 = (V thMAX - V thMIN ) / (V thMAX + V thMIN ) is set, and 3δ2 = 0.1-2.5.

[0022] For example, in the display substrate provided by at least one embodiment of the present disclosure, the average lifespan of the plurality of first thin film transistors of the plurality of first shift register units is longer than the average lifespan of the plurality of second thin film transistors of the plurality of second shift register units.

[0023] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the first side is the left side of the display area and the second side is the right side of the display area in the direction from the substrate to the first gate scanning driving circuit.

[0024] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the first active layer and the second active layer are arranged in the same layer.

[0025] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, each of the plurality of sub-pixels includes a pixel driving circuit, and the pixel driving circuit includes a third thin film transistor, wherein the third thin film transistor includes a third active layer arranged in the same layer as the first active layer and the second active layer, and the third active layer is a plurality of metal oxide semiconductor layers arranged in a stack, wherein the metal oxide semiconductor layer close to the gate of the third thin film transistor is amorphous IGZO, and in the amorphous IGZO, In: Ga: Zn is 1: 1: 1 or 4: 2: 3; and the metal oxide semiconductor layer away from the gate of the third thin film transistor is crystalline IGZO, and in the crystalline IGZO, In: Ga: Zn is 4: 2: 3 or 1: 3: 6.

[0026] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the size of the display substrate along the second direction is greater than the size along the first direction.

[0027] The display panel provided by at least one of the embodiments of the present disclosure includes a display substrate and a counter substrate arranged opposite to each other, and a liquid crystal layer arranged between the display substrate and the counter substrate, wherein the display substrate is the display substrate provided by the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some of the embodiments of the present disclosure, and not limit the present disclosure.

[0029] Figure 1 The display substrate provided by at least one of the embodiments of the present disclosure is shown in a plan view;

[0030] Figure 2A The display substrate provided by at least one of the embodiments of the present disclosure is shown in a partial cross-sectional view of the first thin film transistor and the pixel driving circuit of the sub-pixel closest to the first thin film transistor;

[0031] Figure 2B The display substrate provided by at least one of the embodiments of the present disclosure is shown in a partial cross-sectional view of the second thin film transistor and the pixel driving circuit of the sub-pixel closest to the second thin film transistor;

[0032] Figure 3 A cross-sectional schematic view of active layers of a first thin-film transistor, a second thin-film transistor, and a third thin-film transistor in a display substrate is provided for at least one embodiment of the present disclosure.

[0033] Figure 4 Another planar schematic view of a display substrate is provided for at least one embodiment of the present disclosure.

[0034] Figures 5A-5D A plurality of sets of data of on currents of a plurality of first thin-film transistors and a plurality of second thin-film transistors as output transistors in a display substrate is provided for at least one embodiment of the present disclosure.

[0035] Figures 6A-6D A plurality of sets of data of on currents of a plurality of first thin-film transistors and a plurality of second thin-film transistors as reset transistors in a display substrate is provided for at least one embodiment of the present disclosure.

[0036] Figures 7A-7D A plurality of sets of data of threshold voltages of a plurality of first thin-film transistors and a plurality of second thin-film transistors as output transistors in a display substrate is provided for at least one embodiment of the present disclosure.

[0037] Figures 8A-8D A plurality of sets of data of threshold voltages of a plurality of first thin-film transistors and a plurality of second thin-film transistors as reset transistors in a display substrate is provided for at least one embodiment of the present disclosure.

[0038] Figure 9 A GOA architecture circuit diagram in a display substrate is provided for at least one embodiment of the present disclosure.

[0039] Figure 10 A GOA architecture circuit diagram is provided for at least one embodiment of the present disclosure; and

[0040] Figure 11 A cross-sectional schematic view of a display panel is provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] In order to make the objects, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0042] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as commonly understood by one of ordinary skill in the art to which this present disclosure belongs. Unless specifically stated otherwise, the use of terms such as "first", "second" and like terms in the present disclosure is not to imply any priority or order of use, but to distinguish different constituent components. The use of terms such as "comprises", "comprising", "includes", "including" and like terms in the present disclosure are not to be construed as limiting the scope of what is included but rather to encompass the meaning of "including", "comprising", and the like terms. The use of terms such as "connected", "coupled", and like terms in the present disclosure are not to be construed as being limited to a direct or indirect connection or coupling, but rather to encompass the meaning of "connected", "coupled", and like terms as understood by one of ordinary skill in the art. The use of terms such as "top", "bottom", "left", "right", and like terms in the present disclosure are not to be construed as limiting the relative position of the described objects, but rather to encompass the meaning of "top", "bottom", "left", "right", and like terms as understood by one of ordinary skill in the art.

[0043] As described above, for large size display panels, display uniformity is an important indicator for evaluating the display effect, and forming a display device with better display uniformity is the direction that the person skilled in the art is striving for in the production process.

[0044] At least one embodiment of the present disclosure provides a display substrate and a display panel, the display substrate comprising a substrate and a first gate drive circuit and a second gate drive circuit disposed on the substrate, wherein the display substrate comprises a display area, and the first gate drive circuit and the second gate drive circuit are respectively disposed on the first side and the second side of the display area opposite to each other; the first gate scanning drive circuit comprises a plurality of first shift register units arranged along a first direction, each of the plurality of first shift register units comprises a first thin film transistor, the first thin film transistor comprises a first active layer, and the first active layer comprises a metal oxide semiconductor material; the second gate scanning drive circuit comprises a plurality of second shift register units arranged along the first direction, each of the plurality of second shift register units comprises a second thin film transistor having the same function as the first thin film transistor, the second thin film transistor comprises a second active layer, and the second active layer comprises a metal oxide semiconductor material; the average on-current of the plurality of first thin film transistors of the plurality of first shift register units is I on1 , the average on-current of the plurality of second thin film transistors of the plurality of second shift register units is I on2 , and I on1 > I on2 .

[0045] The display substrate provided in this disclosure can be used to form large-size (e.g., 50-100 inches, or over 100 inches) LCD (Liquid Crystal Display) products, which employ the aforementioned dual-sided GOA (Gate on Array) driving display. Both GOA circuits use metal oxide TFT (Oxide thin film transistor, hereinafter referred to as Oxide-TFT).

[0046] The GOA circuit using Oxide-TFT has a higher turn-on current Ion and a lower turn-off current Ioff. Its carrier mobility is 10-100 times that of thin film transistors using a-Si, resulting in stronger driving capability. It is suitable for products with large size, high resolution, and high frequency driving.

[0047] Currently, this type of GOA has a display malfunction problem. The main reason is that the threshold voltage Vth of the internal TFT of the GOA (such as the TFT that mainly performs the reset function) drifts, causing the cascade relationship to fail and the GOA cannot work properly.

[0048] When process uniformity needs improvement, excessive Vth drift of the TFT, which mainly functions as a reset element, can easily cause GOA circuit failure, leading to poor display. Improving the uniformity of the manufacturing process and reducing the Vth drift of the TFT within the GOA are currently the main directions for improvement.

[0049] Specifically, TFTs with the same function located in different areas exhibit varying degrees of Vth drift. For instance, the Vth drift of TFTs in dual-driven GOAs located on the left and right sides of the display panel differs. Furthermore, the Vth drift of TFTs with different functions within the same GOA on the same side of the display panel also varies.

[0050] For example, targeting Figure 10 The 17T1C GOA architecture shown has M1, M2, and M13 as the main reset units, and M3 as the output transistor, which helps with PU bootstrapping. These four transistors are the main transistors. M1 is connected to the signal input terminal and is called the input transistor, while M13, related to the input signal, can also be called the output transistor. The Vth drift of these four transistors causes the cascade relationship to fail, and the GOA cannot function properly. Of course, the drift of M10 and M11 is also relatively large.

[0051] For the Oxide-TFT in the GOA provided by the embodiments of the present disclosure, in some embodiments, the TFT is a bottom-gate structure with back channel etching, the active layer is a single-layer or stacked metal oxide semiconductor layer structure, the material of the single-layer or stacked metal oxide semiconductor layer is IGZO, the atomic ratio of any one layer is In:Ga:Zn = 1:1:1, or 4:2:3, or 1:3:6, or other ratios, and the IGZO can be doped with N, F, etc. to improve the performance of the device.

[0052] For other architectures of GOA, similar situations as described above will also occur, which will not be described here.

[0053] The display substrate provided by the embodiments of the present disclosure has relatively high uniformity, which can overcome the display defects described above.

[0054] The double-sided driving GOA described above provided by the embodiments of the present disclosure is respectively referred to as a first gate driving circuit and a second gate driving circuit, both of which are Oxide-TFT driving circuits.

[0055] The display substrate and the display panel of the present disclosure will be described below through several specific embodiments.

[0056] At least one embodiment of the present disclosure provides a display substrate, Figure 1 A schematic plan view of the display substrate from a top view angle is shown, as Figure 1 shown, the display substrate includes a substrate 10 and a first gate driving circuit G1 and a second gate driving circuit G2 disposed on the substrate 10, the display substrate includes a display area AA, and the display area AA includes a plurality of sub-pixels P arranged in an array. The first gate driving circuit G1 and the second gate driving circuit G2 are respectively disposed on the first side and the second side of the display area AA opposite to each other, Figure 1 shown, the gate driving circuit is disposed on the left and right sides of the gate driving circuit.

[0057] For example, as Figure 1 shown, the display substrate further includes a peripheral area NA surrounding the display area AA, at this time, the first gate driving circuit G1 and the second gate driving circuit G2 respectively disposed on the first side and the second side of the display area AA opposite to each other can be that the first gate driving circuit G1 and the second gate driving circuit G2 are respectively disposed in the peripheral area NA on the first side and the second side of the display area AA opposite to each other, that is, as Figure 1 shown; or, in some other examples, at least part of the first gate driving circuit G1 and the second gate driving circuit G2 can also be disposed in the display area AA and disposed on the first side and the second side opposite to each other in the display area AA. The embodiments of the present disclosure do not limit the specific positions of the first gate driving circuit G1 and the second gate driving circuit G2.

[0058] For example, such as Figure 1 As shown, the first gate scan driving circuit G1 includes a first direction ( Figure 1 The diagram shows a plurality of first shift register units G11 arranged in a column direction (as shown in the image), each of the plurality of first shift register units G11 including a first thin-film transistor T1. For example, Figure 2A A cross-sectional schematic diagram of the first thin-film transistor T1 and a partial cross-sectional schematic diagram of the pixel driving circuit of the sub-pixel P closest to the first thin-film transistor T1 (in LCD products, the pixel driving circuit can be understood as a circuit such as a switching transistor) are shown. Figure 2A As shown, the first thin-film transistor T1 includes a first active layer T11, which comprises a metal oxide semiconductor material, such as at least one of the metal elements In, Zn, Ga, Sn, and Pr. For example, in some embodiments, the metal oxide semiconductor material may be ZnO-based and doped with rare earth elements, group IIIB elements, Sn, In, N, F, etc., or In2O3-based and doped with rare earth elements, group IIIB elements, Sn, In, N, F, etc. Typical target materials or active layer compositions include IGZO, ITZO, IGZTO, Ln-IZO, etc., and the metal ratios in these materials vary, which will not be elaborated here. Among them, Ln-IZO is IZO doped with lanthanide metals, and Ln-based metals are part of rare earth metals, belonging to group IB elements.

[0059] For example, the pixel driving circuit of sub-pixel P located in display area AA includes a third thin-film transistor T3, which includes a third active layer T31. For example, in some examples, the third active layer T31 is disposed on the same layer as the first active layer T11.

[0060] It should be noted that, in the embodiments of this disclosure, "same-layer configuration" means that two functional layers or structural layers are formed on the same layer and with the same material in the hierarchical structure of the display substrate. That is, in the fabrication process, the two functional layers or structural layers can be formed from the same material layer, and the required patterns and structures can be formed through the same patterning process. This simplifies the fabrication process of the display substrate.

[0061] That is, in the embodiments of this disclosure, the Oxide-TFT thin film transistors in the display areas AA and GOA are formed in a single process, and the active layers of these two areas are made of the same material.

[0062] For example, in some embodiments, the first active layer T11, the second active layer T21, and the third active layer T31 are all multiple metal-oxide-semiconductor layers stacked together. Figure 3 A schematic cross-sectional view of multiple stacked metal-oxide-semiconductor layers is shown. In some embodiments, such as... Figure 3As shown, the metal oxide semiconductor layer A1 close to the gate of the third thin film transistor T3 can be amorphous IGZO, in which In:Ga:Zn is 1:1:1 or 4:2:3; and the metal oxide semiconductor layer A3 far from the gate of the third thin film transistor T3 can be crystalline IGZO, in which In:Ga:Zn is 4:2:3 or 1:3:6.

[0063] It should be noted that, Figure 3 Two metal oxide semiconductor layers arranged in a stack are shown as an example, and in other examples, the number of metal oxide semiconductor layers can also be three or four, etc.

[0064] For example, as Figure 1 shown, the second gate scanning driving circuit G2 includes a plurality of second shift register units G21 arranged along a first direction (such as the column direction of the pixels), and each of the plurality of second shift register units G21 includes a second thin film transistor T2 having the same function as the first thin film transistor T1. For example, the first shift register unit G11 and the second shift register unit G21 have substantially the same circuit structure, and in the first shift register unit G11 and the second shift register unit G21, the first thin film transistor T1 and the second thin film transistor T2 are substantially at the same position, have substantially the same circuit connection relationship, and are used to realize the same function.

[0065] For example, Figure 2B A cross-sectional schematic diagram of the second thin film transistor T2 and a partial cross-sectional schematic diagram of the pixel driving circuit of the sub-pixel P closest to the second thin film transistor T2 are shown. As Figure 2B shown, the second thin film transistor T2 includes a second active layer T21, and the second active layer T21 includes a metal oxide semiconductor material. For example, the first active layer T11 and the second active layer T21 are arranged in the same layer, and for example, the first active layer T11, the second active layer T21 and the third active layer T31 are all arranged in the same layer, thereby simplifying the preparation process of the display substrate.

[0066] In the field of LCD, the bottom gate back channel etching structure (referred to as bottom gate BCE structure) with simpler process procedure is commonly used. The above Figure 2A and Figure 2B are only used to exemplarily describe the relationship between the active layer of the Oxide-TFT and the TFT in the GOA region and the display region AA, and are not used to limit the LCD technical field to only use TFT with top gate structure. For example, the average on-current of the plurality of first thin film transistors T1 of the plurality of first shift register units G11 is I on1 , and the average on-current of the plurality of second thin film transistors of the plurality of second shift register units G21 is I on2, and I on1 >I on2 .

[0067] It should be noted that in the embodiments of this disclosure, the turn-on current of the thin-film transistor refers to I. DS .

[0068] For example, Ion = I DS = W / L*A / (dε(Vgs-Vth-Vds / 2)Vds, where d is the thickness of the gate insulating layer (i.e., the insulating layer GI between the gate and the active layer), ε is the dielectric constant of the gate insulating layer, and I DS Vgs is the current between the source and drain, W / L is the width-to-length ratio of the channel of the thin-film transistor, A is a fixed constant, A = με0, that is, A is equal to the carrier mobility of the channel multiplied by ε0, Vgs is the voltage between the gate and the source, Vth is the threshold voltage, and Vds is the voltage between the source and the drain.

[0069] For example, in some embodiments, the first thin-film transistor T1 and the second thin-film transistor T2 are output transistors that function as output signals, input transistors that function as signal inputs, or reset transistors, which will be described in detail later.

[0070] For example, in some embodiments, such as Figure 1 As shown, the display area AA also includes a scan line GL connected to multiple sub-pixels P. For example, the first thin-film transistor T1 and the second thin-film transistor T2 are output transistors configured to be directly or indirectly electrically connected to the scan line GL to provide a gate scan signal to the multiple sub-pixels P.

[0071] For example, in some embodiments, such as Figure 1 As shown, the scan line GL is along the second direction ( Figure 1 The first side extends in a horizontal direction, and the second side extends in a direction that is approximately perpendicular to the first direction. The first side and the second side are opposite to each other in the second direction.

[0072] For example, in some embodiments, I on1 -I on2 <I on2 ×20%, meaning that the average turn-on current of the plurality of first thin-film transistors located on the first side does not exceed 20% of the average turn-on current of the plurality of second thin-film transistors located on the second side. Such current uniformity can solve the problem of display abnormalities caused by the characteristic differences of TFTs.

[0073] For example, in some embodiments, I on1 -I on2 <I on2×10%. Such current uniformity can solve the problem of display abnormalities caused by differences in TFT characteristics.

[0074] For example, Figure 4 Another planar schematic diagram of the display substrate provided in the embodiments of this disclosure is shown, such as... Figure 4 As shown, in some embodiments, the second side has a first region R1, a second region R2, and a third region R3 arranged sequentially along a first direction, and the average turn-on current of the plurality of second thin-film transistors T2 located in the first region R1 is I. on21 The average turn-on current of the plurality of second thin-film transistors T2 located in the second region R2 is I. on22 The average turn-on current of the multiple second thin-film transistors T2 located in the third region R3 is I. on23 I on21 >I on22 , and I on23 >I on22 Therefore, the average turn-on current of the multiple second thin-film transistors T2 located in the middle region is less than the average turn-on current of the multiple second thin-film transistors T2 located on its upper and lower sides. This design can improve the display effect of the display substrate, that is, improve the viewing experience for the viewer.

[0075] For example, in some examples, the multiple first thin-film transistors T1 located on the first side may also have the above design, which will not be described in detail here.

[0076] For example, such as Figure 2A As shown, the first thin-film transistor T1 includes a first active layer T11, a first gate T12, a first source / drain electrode T13, and a second source / drain electrode T14. Figure 2B As shown, the second thin-film transistor T2 includes a second active layer T21, a second gate T22, a third source / drain electrode T23, and a fourth source / drain electrode T24. The third thin-film transistor T3 includes a third active layer T31, a third gate T32, a fifth source / drain electrode T33, and a sixth source / drain electrode T34. For example, the first thin-film transistor T1, the second thin-film transistor T2, and the third thin-film transistor T3 are disposed in the same layer, that is, the corresponding layers in the first thin-film transistor T1, the second thin-film transistor T2, and the third thin-film transistor T3 are all disposed in the same layer, thereby simplifying the fabrication process of the display substrate.

[0077] It should be noted that in each thin-film transistor, one of the first source / drain electrode and the other of the second source / drain electrode is the source and the other is the drain. The two are structurally symmetrical and therefore can be interchanged in implementation.

[0078] For example, in some embodiments, when the gate voltage Vg of the plurality of first thin film transistors T1 is 10V-20V, for example, 15V, the on current of the plurality of first thin film transistors T1 and the on current of the plurality of second thin film transistors T2 are both greater than 1200μA.

[0079] For example, in some embodiments, when the gate voltage Vg of the plurality of first thin film transistors T1 is 10V-20V, for example, 15V, the maximum value of the on current of the plurality of first thin film transistors T1 is I on1MAX , and the minimum value of the on current of the plurality of first thin film transistors T1 is I on1MIN , I on1MAX -I on1MIN ≤1000μA; when the gate voltage Vg of the plurality of second thin film transistors T2 is 10V-20V, for example, 15V, the maximum value of the on current of the plurality of second thin film transistors T2 is I on2MAX , and the minimum value of the on current of the plurality of second thin film transistors T2 is I on2MIN , I on2MAX -I on2MIN ≤1000μA.

[0080] The above designs can help improve the display uniformity of the display substrate and improve the viewing experience of the viewer.

[0081] For example, in some embodiments, the maximum value of the on current of the plurality of first thin film transistors T1 of the plurality of first shift register units G11 and the plurality of second thin film transistors T2 of the plurality of second shift register units G21 is I onMAX , and the maximum value is I onMIN , and 3δ1=(I onMAX -I onMIN ) / (I onMAX +I onMIN ), then: 3δ1=50-700.

[0082] In the embodiments of the present disclosure, 3δ1 can be used to evaluate the uniformity of the display substrate as a whole, and when 3δ1=50-700, the display substrate has a better display effect and meets the viewing experience needs of the viewer.

[0083] For example, Figures 5A-5D The data of the on current of the plurality of first thin film transistors T1 and the plurality of second thin film transistors T1 as output transistors under multiple tests is shown. Corresponding to the direction of Figure 1 , Figures 5A-5DData of the on currents of the first thin film transistors T1 and the second thin film transistors T1 at various positions are shown, which are measured when the gate voltages Vg of the first thin film transistors T1 are 15V and the gate voltages Vg of the second thin film transistors T2 are 15V, and the unit of the data is microampere (μA), wherein Avg represents the average of the on currents of the first thin film transistors T1 and the second thin film transistors T1. It can be seen that each display substrate has the above design, at this time, the display substrate has better display effect, which can meet the viewing needs of the viewer.

[0084] For example, in other embodiments, the first thin film transistors T1 and the second thin film transistors T2 are both reset transistors, the gate of the reset transistor is connected with a reset control signal end, which will be described in detail later.

[0085] For example, in this embodiment, I on1 -I on2 <I on2 ×30%. For example, I on1 -I on2 <I on2 ×20%. The above design can meet the display uniformity of the display substrate on the one hand, and can also make the preparation process simple and improve the production yield on the other hand.

[0086] For example, in this embodiment, the maximum value of the on currents of the first thin film transistors T1 of the first shift register units G11 and the second thin film transistors T2 of the second shift register units G21 is I onMAX , and the minimum value is I onMIN , and 3δ1=(I onMAX -I onMIN ) / (I onMAX +I onMIN ) is set, then: 3δ1=50-700.

[0087] For example, Figures 6A-6D Data of the on currents of the first thin film transistors T1 and the second thin film transistors T1 as reset transistors are shown under multiple tests. Corresponding to the direction of Figure 1 , Figures 6A-6DData of the on currents of the first thin film transistors T1 and the second thin film transistors T1 located at various positions are shown, which are measured when the gate voltages Vg of the plurality of first thin film transistors T1 are 15 V and the gate voltages Vg of the plurality of second thin film transistors T2 are 15 V, and the unit of the data is microampere (μA), wherein Avg represents the average of the on currents of the plurality of first thin film transistors T1 and the plurality of second thin film transistors T1. It can be seen that each display substrate has the above design, at this time, the display substrate has better display effect, which can meet the viewing needs of the viewer.

[0088] For example, in some embodiments, the average threshold voltage of the plurality of first thin film transistors T1 of the plurality of first shift register units G11 is V th1 , and the average threshold voltage of the plurality of second thin film transistors T2 of the plurality of second shift register units G21 is V th2 , then: V th1 > V th2 .

[0089] It should be noted that the threshold voltage in the embodiments of the present disclosure refers to the on voltage of the thin film transistor.

[0090] For example, in some embodiments, V th1 -V th2 < |V th2 | x 30%. That is, the average threshold voltage of the plurality of first thin film transistors located at the first side is in the range of 30% greater than the average threshold voltage of the plurality of second thin film transistors located at the second side. For example, in some examples, V th1 -V th2 < |V th2 | x 20%. The above design can meet the display uniformity of the display substrate on the one hand, and can also make the preparation process simple and improve the production yield on the other hand.

[0091] For example, in some embodiments, when the source-drain input voltage Vd of the plurality of first thin film transistors T1 is 15.1 V, and the on current Id is 10 -8 A, |V th1 | < 2 V, and |V th2 | < 2 V.

[0092] For example, in some embodiments, the maximum value of the threshold voltage of the plurality of first thin film transistors T1 is V th1MAX , the minimum value of the threshold voltage of the plurality of first thin film transistors T1 is V th1MIN , and V th1MAX -V th1MIN ≤ 2 V; and the maximum value of the threshold voltage of the plurality of second thin film transistors T2 is V th2MAX, the minimum value of the threshold voltage of the plurality of second thin film transistors is V th2MIN , and V th2MAX -V th2MIN ≤ 2V.

[0093] For example, in some embodiments, the maximum value of the threshold voltage in the plurality of first thin film transistors T1 of the plurality of first shift register units G11 and the plurality of second thin film transistors T2 of the plurality of second shift register units G21 is V thMAX , the minimum value is V thMIN , and 3δ2 = (V thMAX -V thMIN ) / (V thMAX +V thMIN ) is set, then: 3δ2 = 0.1-2.5.

[0094] For example, Figures 7A-7D Figures showing the threshold voltage data of the plurality of first thin film transistors T1 and the plurality of second thin film transistors T1 as output transistors under multiple tests. Corresponding to the direction of Figure 1 , Figures 7A-7D Figures showing the threshold voltage data of the first thin film transistors T1 and the second thin film transistors T1 at various positions, which are measured when the source-drain input voltage Vd = 10V-20V, for example 15.1V, and the on-current Id = 10 -8 A of the plurality of first thin film transistors T1 and the source-drain input voltage Vd = 10V-20V, for example 15.1V, and the on-current Id = 10 -8 A of the plurality of second thin film transistors T2, the unit of the data is volt (V), wherein Avg represents the average value of the threshold voltage of the plurality of first thin film transistors T1 and the plurality of second thin film transistors T1. It can be seen that each display substrate has the above design, and at this time, the display substrate has better display effect.

[0095] For example, Figures 8A-8D Figures showing the threshold voltage data of the plurality of first thin film transistors T1 and the plurality of second thin film transistors T1 as reset transistors under multiple tests. Corresponding to the direction of Figure 1 , Figures 7A-7D Figures showing the threshold voltage data of the first thin film transistors T1 and the second thin film transistors T1 at various positions, which are measured when the source-drain input voltage Vd = 10V-20V, for example 15.1V, and the on-current Id = 10 -8 A of the plurality of first thin film transistors T1 and the source-drain input voltage Vd = 10V-20V, for example 15.1V, and the on-current Id = 10 -8The data is measured at time A, and the unit of the data is volt (V), wherein Avg represents the average value of the threshold voltages of the plurality of first thin film transistors T1 and the plurality of second thin film transistors T2. As can be seen, each display substrate has the above design, and the display substrate has better display effect at this time.

[0096] For example, in some embodiments, the average lifespan of the plurality of first thin film transistors T1 of the plurality of first shift register units G11 is longer than the average lifespan of the plurality of second thin film transistors T2 of the plurality of second shift register units G21.

[0097] For example, in some embodiments, as viewed in the direction from the substrate 10 to the first gate scanning driving circuit G1, i.e. in the direction of the display substrate itself, the first side is the left side of the display area AA, and the second side is the right side of the display area AA. Alternatively, as viewed in the direction of the viewer facing the display substrate, i.e. when the display substrate displays a picture, the viewer faces the display substrate, at this time, the first side is the right side of the display area AA, and the second side is the left side of the display area AA, as shown in Figure 1 .

[0098] For example, in some embodiments, as shown in Figure 1 , the size of the display substrate in the second direction is greater than the size in the first direction. That is, when the viewer watches the display substrate, the size of the display substrate in the horizontal direction is greater than the size in the vertical direction.

[0099] For example, Figure 9 An exemplary circuit diagram of a first shift register unit in the display substrate provided by the embodiments of the present disclosure is shown, and the second shift register unit has the same circuit structure as the first shift register unit, at this time, the thin film transistors having the same function in the first shift register unit and the second shift register unit are basically located at the same position in the circuit, have substantially the same circuit connection relationship, and are used to realize the same function.

[0100] For example, as shown in Figure 9As shown, in some examples, the first shift register unit G11 includes an input sub-circuit 101, a first output sub-circuit 102, a second output sub-circuit 103, a reset sub-circuit 104, and a monitoring sub-circuit 105. The input sub-circuit 101 is configured to pre-charge the pull-up node PU by an input signal in response to the input signal; the pull-up node PU is a connection node between the input sub-circuit 101, the first output sub-circuit 102, the second output sub-circuit 103, and the reset sub-circuit 104; the first output sub-circuit 102 is configured to output a clock signal through the first output terminal Output1 in response to the potential of the pull-up node PU; the second output sub-circuit 103 is configured to output a synchronous signal with the first output terminal Output1 through the second output terminal Output2 in response to the potential of the pull-up node PU; the reset sub-circuit 104 is configured to reset the potential of the pull-up node PU by the second power voltage in response to a reset signal; and the monitoring sub-circuit 104 is configured to monitor the second output terminal Output2 and output the monitoring result through the third output terminal Output3.

[0101] Thus, in the above shift register unit, the first output sub-circuit 102 can output a GOA signal, such as a clock signal, through the first output terminal Output1, the second output sub-circuit 103 can output a synchronous signal with the first output terminal Output1 through the second output terminal Output2, and the monitoring sub-circuit 104 can monitor the second output terminal Output2 and output the monitoring result through the third output terminal Output3, so that the GOA signal output by the second output terminal Output2 can be monitored to determine whether the GOA signal output by the shift register is abnormal, and thus the real-time monitoring of the GOA signal can be realized, so that the change of the GOA working state can be monitored during the product reliability process, and thus the point at which the GOA signal is abnormal can be detected in the first time.

[0102] For example, in some examples, as Figure 9As shown, the first shift register can further include at least one pull-down control sub-circuit 106, at least one pull-down sub-circuit 107, at least one first noise reduction sub-circuit 108, at least one second noise reduction sub-circuit 109, and at least one third noise reduction sub-circuit 110. The pull-down control sub-circuit 106 is configured to control the potential of a pull-down node PD by the first power supply voltage in response to the first power supply voltage; the pull-down node PD is a connection node between the pull-down control sub-circuit 106 and the pull-down sub-circuit 107; the pull-down sub-circuit 107 is configured to pull down the potential of the pull-down node PD by the second power supply voltage in response to the potential of the pull-up node PU; the first noise reduction sub-circuit 108 is configured to reduce noise of a first output terminal Output1 by the second power supply voltage in response to the potential of the pull-down node PD; the second noise reduction sub-circuit 109 is configured to reduce noise of a second output terminal Output2 by the second power supply voltage in response to the potential of the pull-down node PD; and the third noise reduction sub-circuit 110 is configured to reduce noise of the pull-up node PU by the second power supply voltage in response to the potential of the pull-down node PD.

[0103] For example, in some embodiments, as Figure 9 As shown, the first shift register unit can further include an initialization sub-circuit 111; the initialization sub-circuit 111 is configured to initialize the potential of the pull-up node PU by the second power supply voltage in response to an initialization signal.

[0104] Specifically, as Figure 9 As shown, the input sub-circuit 101 includes a first transistor M1 (input transistor), the gate and source of the first transistor M1 are connected to an input signal terminal Input, and the drain is connected to a pull-up node PU. The reset sub-circuit 104 includes a second transistor M2 (i.e. the above-mentioned reset transistor), the gate of the second transistor M2 is connected to a reset control signal terminal Reset, the source is connected to a second power supply voltage terminal VSS, and the drain is connected to the pull-up node PU. The first output sub-circuit 102 includes a third transistor M3 (i.e. the above-mentioned output transistor) and a storage capacitor C, the gate of the third transistor M3 is connected to the pull-up node PU, the source is connected to a clock signal terminal CLK, and the drain is connected to a first output terminal Output1; one end of the storage capacitor C is connected to the pull-up node PU, and the drain is connected to the first output terminal Output1. The second output sub-circuit 103 includes a thirteenth transistor M13 (which is also an output transistor); the gate of the thirteenth transistor M13 is connected to the pull-up node PU, the source is connected to the clock signal terminal CLK, and the drain is connected to a second output terminal Output2.

[0105] In order to distinguish M3 and M13, M3 is the first output transistor and M13 is the second output transistor in the embodiments of the present disclosure.

[0106] In the input stage, the signal input terminal Input writes a high level signal, the first transistor M1 is opened, and the high level signal can pre-charge the pull-up node PU through the first transistor M1. In the output stage, since the potential of the pull-up node PU is pre-charged and pulled high, and the storage capacitor C is stored, the first transistor M1 is cut off in this stage, the storage capacitor C discharges to further pull up the potential of the pull-up node PU, the third transistor M3 and the thirteenth transistor M13 are both opened, and the first output terminal Output1 outputs the high level signal written by the clock signal terminal CLK, and the second output terminal Output2 outputs the synchronization signal output by the first output terminal Output1. In the reset stage, the reset control signal terminal Reset is written with a high level signal, the second transistor M2 is opened, and the low power voltage written by the second power supply voltage terminal VSS resets the potential of the pull-up node PU.

[0107] For example, the monitoring sub-circuit 105 includes a fourth transistor M4, the gate and the source of the fourth transistor M4 are connected to the second output terminal Output2, and the drain is connected to the third output terminal Output3.

[0108] It should be noted that the gate and the source of the fourth transistor M4 are connected to the second output terminal Output2, and the drain is connected to the third output terminal Output3. When the GOA signal output by the second output terminal Output2 is a high level signal, the fourth transistor M4 can be opened under the control of the high level signal, and the high level signal is output through the third output terminal Output3. By comparing the high level signal output by the third output terminal Output3 with the reference high level signal. If the signal output by the third output terminal Output3 is the same as the reference high level signal, it indicates that the GOA signal output by the second output terminal Output2 is normal; if the signal output by the third output terminal Output3 is different from the reference high level signal or the third output terminal Output3 has no output signal, it indicates that the GOA signal output by the second output terminal Output2 is abnormal, so the real-time monitoring of the GOA signal can be realized, so that the change of the GOA working state can be monitored in the product reliability process, and then the point where the GOA signal is abnormal can be detected in the first time, avoiding the occurrence of AD and other defects.

[0109] For example, the pull-down control sub-circuit 106 includes the ninth transistor M9 and the fifth transistor M5, the gate and the source of the ninth transistor M9 are connected with the first power voltage terminal VDD, and the drain is connected with the gate of the fifth transistor M5; the gate of the fifth transistor M5 is connected with the drain of the ninth transistor M9, the source is connected with the first power voltage terminal VDD, and the drain is connected with the pull-down node PD. The pull-down sub-circuit 107 includes the sixth transistor M6 and the eighth transistor M8, the gate of the sixth transistor M6 is connected with the pull-up node PU, the source is connected with the pull-down node PD, and the drain is connected with the second power voltage terminal VSS; the gate of the eighth transistor M8 is connected with the pull-up node PU, the source is connected with the drain of the ninth transistor M9, and the drain is connected with the second power voltage terminal VSS. The first noise reduction sub-circuit 108 includes the eleventh transistor M11, the gate of the eleventh transistor M11 is connected with the pull-down node PD, the source is connected with the first output terminal Output1, and the drain is connected with the second power voltage terminal VSS. The second noise reduction sub-circuit 109 includes the twelfth transistor M12, the gate of the twelfth transistor M12 is connected with the pull-down node PD, the source is connected with the second output terminal Output2, and the drain is connected with the second power voltage terminal VSS. The third noise reduction sub-circuit 110 includes the tenth transistor M10, the gate of the tenth transistor M10 is connected with the pull-down node PD, the source is connected with the pull-up node PU, and the drain is connected with the second power voltage terminal VSS.

[0110] It should be noted that, in the examples shown, Figure 9 In the examples shown, two pull-down control sub-circuits 106, two pull-down sub-circuits 107, two first noise reduction sub-circuits 108, two second noise reduction sub-circuits 109, and two third noise reduction sub-circuits 110 are taken as examples for illustration. It can be understood that the number of each sub-circuit described above can also be one or other numbers, and the implementation principle is the same, which will not be described here.

[0111] For example, in the examples shown, Figure 9In the figure, the fifth transistors in the first and second pull-down control sub-circuits 106 are denoted as M5 and M5' respectively, and the ninth transistors are denoted as M9 and M9' respectively; the sixth transistors in the first and second pull-down circuits 107 are denoted as M6 and M6' respectively, and the eighth transistors are denoted as M8 and M8' respectively; the eleventh transistors in the first and second first noise reduction circuits 108 are denoted as M11 and M11' respectively; the twelfth transistors in the first and second second noise reduction circuits 109 are denoted as M12 and M12' respectively; the tenth transistors in the first and second third noise reduction circuits 110 are denoted as M10 and M10' respectively; the first power supply voltage terminals connected with the first and second pull-down control sub-circuits 106 are denoted as VDD1 and VDD2 respectively. In addition, the first pull-down control sub-circuit 106 is connected with the first pull-down circuit 107, and the connection node between them is denoted as pull-down node PD1; the second pull-down control sub-circuit 106 is connected with the second pull-down circuit 107, and the connection node between them is denoted as pull-down node PD2; the first first noise reduction circuit 108 is connected with PD1, and the second first noise reduction circuit 108 is connected with PD2; the first second noise reduction circuit 109 is connected with PD1, and the second second noise reduction circuit 109 is connected with PD2; the first third noise reduction circuit 110 is connected with PD1, and the second third noise reduction circuit 110 is connected with PD2.

[0112] For example, during the scanning of a frame of image, the first pull-down control sub-circuit 106, the first first pull-down circuit 107, the first first noise reduction circuit 108, the first second noise reduction circuit 109, and the first third noise reduction circuit 110 work, or the second pull-down control sub-circuit 106, the second first pull-down circuit 107, the second first noise reduction circuit 108, the second second noise reduction circuit 109, and the second third noise reduction circuit 110 work. That is, the number of pull-down control sub-circuits 106, first pull-down circuits 107, first noise reduction circuits 108, second noise reduction circuits 109, and third noise reduction circuits 110 can be multiple, and only one of the sub-circuits with the same function works at a time during the scanning of a frame of image, and the other one can be switched to work at a preset time, so as to prolong the service life of the shift register. During the noise reduction stage, the pull-up node PU is pulled down to the low potential level during the reset stage; the fifth transistor M5 and the ninth transistor M9 are always controlled by the first power supply voltage VDD1 written by the first power supply voltage, and the potential of the pull-down node PD1 is a high-level signal at this time, the eleventh transistor M11 is opened, and the second power supply voltage written by the second power supply voltage end VSS is used to reduce the output of the first output end Output1. At the same time, the twelfth transistor M12 and the tenth transistor M10 are also opened, and the second power supply voltage written by the second power supply voltage end VSS is used to reduce the output of the second output end Output2 and the pull-up node PU respectively.

[0113] For example, the initialization sub-circuit 111 includes the seventh transistor M7, the gate of the seventh transistor M7 is connected to the initialization signal end STV, the source is connected to the pull-up node PU, and the drain is connected to the second power supply voltage end VSS.

[0114] It should be noted that when displaying the next frame of display image, the initialization signal end STV writes a high-level signal, the seventh transistor M7 is opened, and the low power supply voltage written by the second power supply voltage end VSS is used to initialize the potential of the pull-up node PU, so as to prevent the display images of adjacent frames from interfering with each other and affecting the display effect.

[0115] It can be understood that the first shift register unit and the second shift register unit provided by the embodiments of the present disclosure can be other circuit structures in addition to the 19T1C structure, for example, 17T1C structure, 18T2C structure, 21T1C structure, etc., and the embodiments of the present disclosure do not limit the specific structure of the first shift register unit and the second shift register unit. For example, when the structure of the first shift register unit and the second shift register unit is 17T1C structure, compared with the above-mentioned 19T1C structure, the 17T1C can not have the ninth transistor M9 and M9', but the implementation principle is the same as that of the above-mentioned 19T1C structure, which will not be repeated here.

[0116] At least one embodiment of the present disclosure provides a display panel, Figure 11 A cross-sectional schematic diagram of the display panel is shown, as Figure 11 shown, the display panel includes a display substrate 100 and a counter substrate 200 arranged opposite to each other, and a liquid crystal layer 300 sandwiched between the display substrate 100 and the counter substrate 200, so that the display panel can be realized as a liquid crystal display panel.

[0117] For example, the display substrate 100 is the display substrate provided by the embodiments of the present disclosure. At this time, as Figure 2A and Figure 2B shown, the first planarization layer 20 is arranged on the pixel driving circuit of the plurality of sub-pixels P of the display substrate, and the pixel driving circuit further includes a first driving electrode E1 and a second driving electrode E2 arranged on the side of the first planarization layer 150 away from the substrate substrate 10. The liquid crystal layer 300 includes a liquid crystal material which can be deflected under the driving of the above-mentioned first driving electrode E1 and second driving electrode E2, and then realize different light transmittance to realize display. For example, the first driving electrode E1 is electrically connected with the pixel driving circuit through the fifth source-drain electrode T33 of the third thin film transistor T3, and the second driving electrode E2 can be electrically connected with the power supply line (not shown).

[0118] For example, in some embodiments, as Figure 2A and Figure 2B shown, the second driving electrode E2 can be arranged in the same layer and spaced apart from the first driving electrode E1; or in another example, the second driving electrode E2 can also be arranged in different layers and spaced apart from the first driving electrode E1, as long as the first driving electrode E1 and the second driving electrode E2 can drive the liquid crystal material to deflect to realize different light transmittance, and the embodiments of the present disclosure do not limit the specific arrangement manner of the first driving electrode E1 and the second driving electrode E2.

[0119] For example, as Figure 2A and Figure 2BAs shown, the first driving electrode E1 is further provided with a second planarization layer 20 on the side away from the substrate 10. The first planarization layer 20 and the second planarization layer 30 can be made of organic insulating materials such as polyimide or acrylic resin. For example, the first driving electrode E1 and the second driving electrode E2 can be made of metal materials such as aluminum, molybdenum, titanium, copper or alloy materials thereof.

[0120] For example, in the embodiments of the present disclosure, the substrate 10 can be made of rigid substrates such as glass or quartz or flexible substrates such as polyimide, each gate can be made of metal materials such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo) or alloy materials, for example, in a single-layer metal layer structure or a multi-layer metal layer structure, for example, a multi-layer metal layer structure such as titanium / aluminum / titanium. Each active drain can be made of metal materials such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo) or alloy materials, for example, in a single-layer metal layer structure or a multi-layer metal layer structure, for example, a multi-layer metal layer structure such as titanium / aluminum / titanium. The embodiments of the present disclosure do not make specific limitations on the materials of each structure.

[0121] In the embodiments of the present disclosure, each thin film transistor can be a P-type thin film transistor or an N-type thin film transistor, and the structure can be a bottom gate type, a top gate type or a double gate type. The embodiments of the present disclosure do not make limitations on the specific forms of each thin film transistor.

[0122] For example, the display panel provided by the embodiments of the present disclosure can also be an organic light-emitting diode display panel or a quantum dot display panel or other types of display panels. The embodiments of the present disclosure do not make limitations on this.

[0123] The following points need to be explained:

[0124] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0125] (2) For the sake of clarity, the thickness of the layer or region is exaggerated or reduced in the drawings used to describe the embodiments of the present disclosure. It can be understood that when an element such as a layer, a film, a region or a substrate is referred to as being located "on" or "under" another element, it can be "directly" located on or under another element or there can be an intermediate element.

[0126] (3) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0127] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display substrate, comprising: a substrate and a first gate drive circuit and a second gate drive circuit disposed on the substrate, the display substrate comprises a display area, the first gate drive circuit and the second gate drive circuit are disposed on a first side and a second side of the display area respectively, the first side and the second side are opposite to each other; the first gate drive circuit comprises a plurality of first shift register units arranged along a first direction, each of the plurality of first shift register units comprises a first thin film transistor having a first function in the first gate drive circuit, the first thin film transistor comprises a first active layer, the first active layer comprises a metal oxide semiconductor material; the second gate drive circuit comprises a plurality of second shift register units arranged along the first direction, each of the plurality of second shift register units comprises a second thin film transistor having the same function as the first thin film transistor, the second thin film transistor comprises a second active layer, the second active layer comprises a metal oxide semiconductor material; An average on-current of the first thin film transistor of at least one of the first shift register units is I on1 An average on-current of the second thin film transistor of at least one of the second shift register units is I on2 , and I on1 > I on2 . 2.The display substrate of claim 1, wherein, the first thin film transistor and the second thin film transistor are output transistors, input transistors or reset transistors. 3.The display substrate of claim 2, wherein, the display area comprises a plurality of sub-pixels and a plurality of scan lines connected to the plurality of sub-pixels, the first thin film transistor and the second thin film transistor are output transistors configured to provide a gate scanning signal to the plurality of scan lines of the plurality of sub-pixels; the scan lines extend along a second direction, the second direction is substantially perpendicular to the first direction; the first side and the second side are opposite to each other in the second direction. 4.The display substrate of claim 3, wherein, I on1 -I on2 <I on2 x 20%. 5.The display substrate of claim 4, wherein, I on1 -I on2 <I on2 x 10%. 6.The display substrate of claim 3, wherein, the second side has a first region, a second region and a third region arranged in sequence along the first direction, An average on-current of the plurality of second thin film transistors located in the first region is I on21 An average on-current of the plurality of second thin film transistors located in the second region is I on22 An average on-current of the plurality of second thin film transistors located in the third region is I on23 I on21 > I on22 , and I on23 > I on22 . 7.The display substrate of claim 3, wherein, when a gate voltage Vg of the plurality of first thin film transistors is 10V-20V, an on-current of the plurality of first thin film transistors and an on-current of the plurality of second thin film transistors are greater than 1200μA. 8.The display substrate of claim 3, wherein, The maximum value of the on-current of the plurality of first thin film transistors is I on1MAX The minimum value of the on-current of the plurality of first thin film transistors is I on1MIN , I on1MAX -I on1MIN ≤ 1000 μA. The maximum value of the on-current of the plurality of second thin film transistors is I on2MAX when the gate voltage Vg of the plurality of second thin film transistors is 10V-20V. on2MIN The minimum value of the on-current of the plurality of second thin film transistors is I on2MAX -I on2MIN ≤1000μA. 9.The display substrate of claim 3, wherein, The maximum value of the on currents in the first thin film transistors of the first plurality of shift register units and the second thin film transistors of the second plurality of shift register units is I onMAX , the maximum value is I onMIN , Set 3δ1= (I onMAX - I onMIN ) / (I onMAX + I onMIN ), then: 3δ1= 50~700. 10.The display substrate of claim 2, wherein, the first thin film transistor and the second thin film transistor are reset transistors, a gate of the reset transistor is connected to a reset control signal terminal. 11.The display substrate of claim 10, wherein, I on1 -I on2 <I on2 x 30%. 12.The display substrate of claim 11, wherein, I on1 -I on2 <I on2 ×20% 13.The display substrate of claim 10, wherein, The maximum value of the on currents in the first thin film transistors of the first plurality of shift register units and the second thin film transistors of the second plurality of shift register units is I onMAX The minimum value is I onMIN , Set 3δ1= (I onMAX - I onMIN ) / (I onMAX + I onMIN ), then: 3δ1= 50~700.

14. The display substrate according to any one of claims 1-13, wherein, The average threshold voltage of the plurality of first thin film transistors of the plurality of first shift register units is V th1 The average threshold voltage of the plurality of second thin film transistors of the plurality of second shift register units is V th2 then: V th1 > V th2 . 15.The display substrate of claim 14, wherein, V th1 - V th2 <|V th2 |×30%. 16.The display substrate of claim 14, wherein, In the plurality of first thin film transistors, the source-drain input voltage Vd = 10V-20V, the on current Id = 10 -8 A, |V th1 |<2V, |V th2 |<2 V. 17.The display substrate of claim 16, wherein, a maximum value of threshold voltages of the plurality of first thin film transistors is V th1MAX a minimum value of threshold voltages of the plurality of first thin film transistors is V th1MIN , and V th1MAX - V th1MIN ≤ 2V. a maximum value of threshold voltage of the plurality of second thin film transistors is V th2MAX a minimum value of threshold voltage of the plurality of second thin film transistors is V th2MIN , and V th2MAX -V th2MIN ≤ 2V. 18.The display substrate of claim 14, wherein, a maximum value of threshold voltages in the first thin film transistors of the first shift register units and the second thin film transistors of the second shift register units is V thMAX , and a minimum value is V thMIN , Set 3δ2= (V thMAX - V thMIN ) / (V thMAX + V thMIN ), then: 3δ2= 0.1~2.

5.

19. The display substrate according to any one of claims 1-13, wherein, an average life of the plurality of first thin film transistors of the plurality of first shift register units is longer than an average life of the plurality of second thin film transistors of the plurality of second shift register units.

20. The display substrate according to any one of claims 1-13, wherein, in a direction from the substrate to the first gate drive circuit, the first side is a left side of the display area, and the second side is a right side of the display area.

21. The display substrate according to any one of claims 3-9, wherein, the first active layer and the second active layer are disposed in the same layer. 22.The display substrate of claim 21, wherein, each of the plurality of sub-pixels comprises a pixel drive circuit, the pixel drive circuit comprises a third thin film transistor, wherein the third thin film transistor comprises a third active layer, the third active layer is disposed in the same layer as the first active layer and the second active layer, and is a plurality of metal oxide semiconductor layers disposed in a stack, wherein The metal oxide semiconductor layer close to the gate electrode of the third thin film transistor is amorphous IGZO in which In:Ga:Zn is 1:1:1 or 4:2:3; and the metal oxide semiconductor layer away from the gate electrode of the third thin film transistor is crystalline IGZO in which In:Ga:Zn is 4:2:3 or 1:3:

6.

23. The display substrate of claim 3, wherein, The display substrate has a size along the second direction that is greater than a size along the first direction.

24. A display panel comprising a display substrate and a counter substrate disposed opposite to each other, and a liquid crystal layer interposed between the display substrate and the counter substrate, wherein, The display substrate is the display substrate according to any one of claims 1-23.

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