A display device, an image signal processing device, an acquisition device, and a display system

Abstract

The display device comprises a plurality of pixels arranged in an array, a plurality of scanning lines extending in a row direction and coupled to the plurality of pixels respectively, a plurality of data lines extending in the row direction and a plurality of control lines extending in a column direction, a data bus coupled to each data line, and a plurality of first switch circuits corresponding to one data line, a plurality of second switch circuits corresponding to each pixel, and the pixel comprises a pixel electrode, wherein: the first switch circuit is configured to control the coupling of the corresponding data line and the data bus in response to the signal of the corresponding scanning line; and the second switch circuit is configured to control the coupling of the pixel electrode of each pixel and the corresponding data line in response to the signal of the corresponding control line and the signal of the corresponding scanning line.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display device, an image signal processing device, an acquisition device, and a display system. Background Technology

[0002] With the development of intelligent science and technology, high technology offers various simulations of human senses, such as vision, hearing, taste, and touch. Among these, vision is a primary human need. Currently, cameras can act as human eyes, acquiring scene information from areas invisible to the naked eye, thus extending human vision. However, current technology suffers from significant time delays in the images captured by cameras. Taking Mixed Reality (MR) systems, which integrate the virtual and real worlds, as an example, existing MR systems typically include a camera and a display. The real-time image seen by the human eye through the display is often two or more frames older than the captured image. Clearly, existing display devices suffer from a technical problem of transmission delay between image acquisition and display. Summary of the Invention

[0003] This disclosure provides a display device, an image signal processing device, an acquisition device, and a display system, the specific solutions of which are as follows:

[0004] This disclosure provides a display device, comprising:

[0005] The array comprises multiple pixels, multiple scan lines extending along the row direction coupled to the multiple pixels, multiple data lines extending along the row direction and multiple control lines extending along the column direction, a data bus coupled to each data line, multiple first switching circuits corresponding to each data line, and multiple second switching circuits corresponding to each pixel. Each pixel includes a pixel electrode.

[0006] The first switching circuit is configured to control the coupling of the corresponding data line with the data bus in response to the signal of the corresponding scan line; the second switching circuit is configured to control the coupling of the pixel electrode of each pixel with the corresponding data line in response to the signal of the corresponding control line and the signal of the corresponding scan line.

[0007] Optionally, in embodiments of this disclosure, the display device further includes a row drive timing control circuit coupled to each scan line, and a data bus controller coupled to each control line, wherein:

[0008] The row drive timing control circuit is configured to output scan signals sequentially to each scan line and its corresponding first switch circuit; the data bus controller is configured to output control signals sequentially to each control line.

[0009] Optionally, in an embodiment of this disclosure, the first switching circuit includes a first transistor, the second switching circuit includes a second transistor and a third transistor, the gate of the first transistor and the gate of the third transistor are both coupled to a corresponding scan line, the first electrode of the first transistor is coupled to the data bus, the second electrode of the first transistor and the first electrode of the second transistor are both coupled to a corresponding data line, the gate of the second transistor is coupled to a corresponding control line, the second electrode of the second transistor is coupled to the first electrode of the third transistor, and the second electrode of the third transistor is coupled to the pixel electrode of the corresponding pixel.

[0010] Optionally, in this embodiment of the disclosure, the data bus controller includes multiple cascaded shift register units. The signal output terminal of each shift register unit is coupled to a corresponding control line. In every two adjacent shift register units, the signal input terminal of the next-level shift register unit is coupled to the signal output terminal of the previous-level shift register unit. The other signal input terminal of each shift register unit is coupled to a bus timing controller. The bus timing controller is configured to output a clock pulse signal and load the clock pulse signal to each shift register unit, thereby connecting the data bus controller and the corresponding column pixel on the corresponding row pixel to charge the corresponding pixel.

[0011] Optionally, in an embodiment of this disclosure, the display device further includes a first amplifier coupled to the data bus, the first amplifier being used to receive analog image signals from the data bus, amplify the analog image signals, and output the amplified analog signals to each data line.

[0012] Accordingly, embodiments of this disclosure provide an image signal processing apparatus, comprising:

[0013] A grayscale separation unit includes multiple voltage comparators, the input terminals of which are coupled together, and the output terminals of which are coupled together. The grayscale separation unit is used to output the input analog image signal from a target voltage comparator among the multiple voltage comparators that matches the grayscale voltage of the analog image signal. Each voltage comparator corresponds to a different grayscale voltage.

[0014] Optionally, in this embodiment of the present disclosure, the grayscale voltage corresponding to each voltage comparator decreases along the input direction of the analog image signal.

[0015] Optionally, in this embodiment of the disclosure, each voltage comparator includes a window comparator, which includes a first comparator, a second comparator, and a power supply terminal for providing operating power to the first comparator and the second comparator. The input terminal of the window comparator is coupled to the non-inverting input terminal of the first comparator and the inverting input terminal of the second comparator, respectively. The output terminals of the first comparator and the second comparator are both coupled to the output terminal of the window comparator. The inverting input terminal of the first comparator is coupled to a first threshold voltage terminal for providing a first threshold voltage through a first resistor. The non-inverting input terminal of the second comparator is coupled to a second threshold voltage terminal for providing a second threshold voltage through a second resistor. The analog image signal whose grayscale voltage is between the first threshold voltage and the second threshold voltage is output through the output terminal of the window comparator.

[0016] Among the plurality of voltage comparators, the first threshold voltage and the second threshold voltage corresponding to any two voltage comparators are different, and the voltage defined by the first threshold voltage and the second threshold voltage corresponding to each window comparator is the grayscale voltage of the corresponding voltage comparator.

[0017] Optionally, in embodiments of this disclosure, each voltage comparator further includes a voltage divider circuit coupled to the window comparator. The voltage divider circuit includes a third resistor coupled to the power supply terminal and the output terminal of the window comparator, and a fourth resistor coupled to the output terminal of the window comparator and ground, respectively. The voltage output by the analog image signal input through the input terminal of the window comparator after passing through the output terminal of the corresponding window comparator is the grayscale voltage of the analog image signal.

[0018] Optionally, in this embodiment of the present disclosure, a switching diode is further provided between the output terminals of each two adjacent voltage comparators. Along the input direction of the analog image signal, the cathode of the switching diode is coupled to the output terminal of the previous voltage comparator, and the anode of the switching diode is coupled to the output terminal of the next voltage comparator.

[0019] Optionally, in this embodiment of the present disclosure, the image signal processing device further includes a filter coupled to the input terminal of each voltage comparator, the filter being used to filter out noise in the analog image signal and input the noise-filtered analog signal to the grayscale separation unit.

[0020] Optionally, in this embodiment of the present disclosure, the image signal processing apparatus further includes a second amplifier coupled to the output terminal of each voltage comparator, the second amplifier being used to amplify the noise-filtered analog signal.

[0021] Accordingly, embodiments of this disclosure provide an image signal acquisition device, comprising:

[0022] The array comprises multiple pixel sensors, multiple first signal lines extending along the row direction and multiple second signal lines extending along the column direction, each coupled to the multiple pixel sensors; a row selection controller coupled to each first signal line; a column selection controller coupled to the first end of each second signal line; timing control circuits coupled to the row selection controller and the column selection controller, respectively; and an output bus coupled to the second end of each second signal line; wherein:

[0023] The plurality of image sensors are configured to acquire image information from the outside world and convert the image information into analog image signals; the row selection controller is configured to output scanning signals to a plurality of first signal lines in sequence; the column selection controller is configured to control a plurality of column control switches to open in sequence to output reference voltages to the corresponding first signal lines in order to extract the analog signals generated by exposure on the corresponding image sensors; the output bus is configured to output the analog signals after exposure.

[0024] Optionally, in embodiments of this disclosure, each pixel includes a photodiode and a line scan control switch.

[0025] Accordingly, embodiments of this disclosure provide a display system, comprising:

[0026] An image signal acquisition device, a display device, and an image signal processing device coupled to the image signal acquisition device and the display device respectively; wherein:

[0027] The image signal acquisition device is used to convert the acquired image information into analog image signals and transmit them to the image signal processing device;

[0028] The image signal processing device is used to determine the grayscale voltage of the analog image signal and transmit the analog image signal to the display device;

[0029] The display device is used to display based on the analog image signal.

[0030] Optionally, in an embodiment of this disclosure, the image signal processing apparatus includes:

[0031] A grayscale separation unit includes multiple voltage comparators, the input terminals of which are coupled together, and the output terminals of which are coupled together. The grayscale separation unit is used to output the input analog image signal from a target voltage comparator among the multiple voltage comparators that matches the grayscale voltage of the analog image signal. Each voltage comparator corresponds to a different grayscale voltage.

[0032] Optionally, in an embodiment of this disclosure, the display device includes:

[0033] The array comprises multiple pixels, and multiple scan lines extending in the row direction, multiple data lines extending in the row direction, and multiple control lines extending in the column direction, each coupled to the multiple pixels; a data bus coupled to each data line; multiple first switching circuits corresponding to each data line; and multiple second switching circuits corresponding to each pixel. Each pixel includes a pixel electrode.

[0034] The first switching circuit is configured to control the coupling of the data line with the data bus in response to the signal of the corresponding scan line; the second switching circuit is configured to control the coupling of the pixel electrode of each pixel with the corresponding data line in response to the signal of the corresponding control line and the signal of the corresponding scan line.

[0035] Optionally, in this embodiment of the disclosure, the image signal acquisition device includes:

[0036] The array comprises multiple pixel sensors, multiple first signal lines extending along the row direction and multiple second signal lines extending along the column direction, each coupled to the multiple pixel sensors; a row selection controller coupled to each first signal line; a column selection controller coupled to the first end of each second signal line; timing control circuits coupled to the row selection controller and the column selection controller, respectively; and an output bus coupled to the second end of each second signal line; wherein:

[0037] The plurality of image sensors are configured to acquire image information from the outside world and convert the image information into analog image signals; the row selection controller is configured to output scanning signals to a plurality of first signal lines in sequence; the column selection controller is configured to control a plurality of column control switches to open in sequence to output reference voltages to the corresponding first signal lines in order to extract the analog signals generated by exposure on the corresponding image sensors; the output bus is configured to output the analog signals after exposure.

[0038] Optionally, in this embodiment of the present disclosure, the display device further includes an application processor. If the display device is in a human-computer interaction mode, the application processor is used to render and generate virtual image data, obtain the rendered image data, and send the rendered image data to multiple pixels in the display device so that the multiple pixels display the rendered image data.

[0039] When the display system is in the mode of capturing external scenes, the plurality of pixels display the analog image signal. Attached Figure Description

[0040] Figure 1 This is a diagram of one of the architectures for the camera and display in an existing mixed reality system.

[0041] Figure 2 This is a schematic diagram of one structure of a display device provided in an embodiment of the present disclosure;

[0042] Figure 3 This is a schematic diagram of one structure of an image signal processing apparatus provided in an embodiment of the present disclosure;

[0043] Figure 4 This is a schematic diagram of one type of signal of a voltage comparator in an image signal processing apparatus provided in an embodiment of the present disclosure;

[0044] Figure 5 This is a schematic diagram of one structure of an image signal processing apparatus provided in an embodiment of the present disclosure;

[0045] Figure 6 This is a schematic diagram of one structure of an image signal processing apparatus provided in an embodiment of the present disclosure;

[0046] Figure 7 This is a schematic diagram of one structure of an image signal acquisition device provided in an embodiment of the present disclosure;

[0047] Figure 8 This is a schematic diagram of one structure of a display system provided in an embodiment of the present disclosure;

[0048] Figure 9 This is a schematic diagram of one structure of a display device in a display system provided by an embodiment of the present disclosure. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0050] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. As used in this disclosure, the words “comprising” or “including” and similar terms mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, but do not exclude other elements or objects.

[0051] like Figure 1The diagram illustrates one possible architecture of a camera terminal 01 and a display terminal 02 in an existing mixed reality system. Specifically, the camera terminal 01 acquires pixel information through a color filter, then performs photoelectric signal conversion and analog-to-digital conversion on the acquired pixel information to form image information. The image information is then transmitted to the image signal processor (ISP) 03 via protocols such as Universal Serial Bus (USB), Mobile Industry Processor Interface (MIPI), and Camera Serial Interface (CSI). The image signal processor 03 performs a series of processing operations on the image information, such as black level correction, bad pixel correction, noise reduction, automatic white balance, and data enhancement. After data processing, the data protocol is converted to the MIPI Display Serial Interface (DSI) protocol that can be accepted by the driver integrated circuit (Driver IC) 04 of the display terminal 02. The data is then sent to the Driver IC 04. 04. The data is parsed and then converted into an analog signal, which is the source signal. The source signal is then displayed by the display terminal 02.

[0052] Because mixed reality systems require an image signal processor 03 to perform image processing and data conversion, there is often a delay of at least two frames between the image acquisition from the camera 01 and the display 02. These two frames include one fixed frame for image rendering, and the remaining time is due to delays caused by image processing and protocol conversion. Therefore, existing display devices suffer from a technical problem of transmission delay from image acquisition to image display.

[0053] In view of this, embodiments of the present disclosure provide a display device, an image signal processing device, an acquisition device, and a display system to avoid transmission delay from image acquisition to image display by the display device, thereby improving the real-time performance of the display device from image acquisition to image display.

[0054] like Figure 2 The diagram shown is a schematic representation of one embodiment of a display device provided in this disclosure. Specifically, the display device includes:

[0055] The array comprises multiple pixels P, multiple scan lines G extending along the row direction, multiple data lines D extending along the row direction, and multiple control lines C extending along the column direction, all coupled to the multiple pixels P. A data bus B is coupled to each data line D, and multiple first switching circuits 10 corresponding to each data line D, and multiple second switching circuits 20 corresponding to each pixel P. Each pixel P includes a pixel electrode.

[0056] The first switching circuit 10 is configured to control the coupling of data line D with the data bus B in response to the signal of the corresponding scan line G; the second switching circuit 20 is configured to control the pixel electrode of each pixel P to be coupled with the corresponding data line D in response to the signal of the corresponding control line C and the signal of the corresponding scan line G.

[0057] In specific implementation, the display device can be a flexible display device or a rigid display device, and is not limited thereto. Furthermore, the display device can be a liquid crystal display (LCD) or an organic light-emitting diode (OLED), and is not limited thereto.

[0058] The display device includes multiple pixels P arranged in an array. The specific number of pixels P can be M*N, where M and N are both positive integers. The specific numbers of M and N can be determined according to the actual application and are not limited here. The display device includes multiple scan lines G extending in the row direction, multiple data lines D extending in the row direction, and multiple control lines C extending in the column direction, each coupled to the multiple pixels P. In practical applications, the specific number of scan lines G, data lines D, and control lines C can be set according to the arrangement of pixels P in the display device. For example, if the multiple pixels P form an array of M rows and N columns, the number of scan lines G and data lines D is M, and the number of control lines C is N columns.

[0059] The display device further includes a data bus B coupled to each data line D, a plurality of first switch circuits 10 corresponding to each data line D, and a plurality of second switch circuits 20 corresponding to each pixel P. The data bus B can carry analog signals and transmit these analog signals to each pixel P through the data lines D. The first switch circuit 10 is configured to control the coupling of the corresponding data line D to the data bus B in response to a signal from a corresponding scan line G. This ensures that when a row of pixels P is opened, the output path of that data line D is also opened, charging that row of pixels P. Thus, while controlling the transmission of analog signals from the data bus B to the corresponding row of pixels P, charging of a specific row of pixels P is achieved simultaneously. Furthermore, the second switch circuit 20 is configured to control the coupling of the pixel electrode of each pixel P to the corresponding data line D in response to signals from a corresponding control line C and a corresponding scan line G. This ensures that when a row of pixels P is opened, only one pixel P is charged at a time, thus achieving charging of a specific pixel P in a specific row. Since the display device can transmit analog signals to each pixel P through the data bus B, the entire process does not require analog-to-digital conversion, thus ensuring the real-time performance of the image display.

[0060] In this disclosed embodiment, it is still combined with Figure 2 As shown, the display device further includes a row drive timing control circuit 30 coupled to each scan line G, and a data bus controller 40 coupled to each control line C, wherein:

[0061] The row drive timing control circuit 30 is configured to sequentially output scan signals to each scan line G and its corresponding first switch circuit 10; the data bus controller 40 is configured to sequentially output control signals to each control line C.

[0062] The row drive timing control circuit 30 is configured to sequentially output scan signals to each scan line G and its corresponding first switch circuit 10. In this way, the row drive timing control circuit 30 can not only control the opening of the row path, but also simultaneously control the opening and closing of the data bus B output path. If the output path of the data bus B is opened, the corresponding row pixel P can be charged, thus achieving the purpose of row scanning. Furthermore, the data bus controller 40 is configured to sequentially output control signals to each control line C. In this way, the data bus controller 40 can control the on / off state of each pixel P in each row, ensuring that when a row of pixels P is opened, only one pixel P is charged at a time, thus achieving the charging of a specific pixel P in a specific row.

[0063] In this disclosed embodiment, it is still combined with Figure 2As shown, the first switching circuit 10 includes a first transistor 11, and the second switching circuit 20 includes a second transistor 21 and a third transistor 22. The gates of the first transistor 11 and the third transistor 22 are both coupled to the corresponding scan line G. The first electrode of the first transistor 11 is coupled to the data bus B. The second electrodes of the first transistor 11 and the second transistor 21 are both coupled to the corresponding data line D. The gate of the second transistor 21 is coupled to the corresponding control line C. The second electrode of the second transistor 21 is coupled to the first electrode of the third transistor 22. The second electrode of the third transistor 22 is coupled to the pixel P electrode of the corresponding pixel P.

[0064] It should be noted that the transistors mentioned above can be thin-film transistors (TFTs) or metal-oxide-semiconductor field-effect transistors (MOSs), and are not limited here. Depending on the direction of signal flow, the first terminal of the transistor can be used as its source, and correspondingly, the second terminal can be used as its drain; alternatively, the first terminal can be used as its drain, and correspondingly, the second terminal can be used as its source, and are not limited here.

[0065] In this disclosed embodiment, it is still combined with Figure 2 As shown, the data bus controller 40 includes multiple cascaded shift register units 41. The signal output terminal of each shift register unit 41 is coupled to the corresponding control line C. In every two adjacent shift register units 41, the signal input terminal of the next-level shift register unit 41 is coupled to the signal output terminal of the previous-level shift register unit 41. The other signal input terminal of each shift register unit 41 is coupled to the bus timing controller 50. The bus timing controller 50 is configured to output a clock pulse signal and load the clock pulse signal to each shift register unit 41, thereby connecting the data bus controller 40 and the corresponding column pixel P on the corresponding row pixel P to charge the corresponding pixel P.

[0066] The data bus controller 40 includes multiple cascaded shift register units 41. The number of shift register units 41 can be set according to actual application needs. If the multiple pixels P are M rows and N columns, the number of shift register units 41 can be N, and correspondingly, the number of control lines C is also N. The bus timing controller 50 can output a high-level clock pulse signal and load this clock pulse signal onto each shift register unit 41, connecting the data bus controller 40 and the corresponding column of pixels P in the corresponding row of pixels P to charge the corresponding pixels P. Since the clock pulse signal can sequentially turn on the data signal of each column of the data bus B, it can be ensured that only one second transistor 21 coupled to a control line C is turned on at a time. Figure 2 Q0, Q1, Q2, ... represent the control signals output from the output terminals of the shift register unit 41.

[0067] In this disclosed embodiment, it is still combined with Figure 2 As shown, the display device further includes a first amplifier 60 coupled to the data bus B. The first amplifier 60 is used to receive analog image signals from the data bus B, amplify the analog image signals, and output the amplified analog signals to each data line D.

[0068] The first amplifier 60 can receive analog image signals from the data bus B, amplify the analog image signals, and output the amplified analog signals to each data line D. In this way, before the display device displays the image, the first amplifier 60 amplifies the analog image signals transmitted from the data bus B, ensuring that the pixels P are fully charged, thereby ensuring the display effect of the display device.

[0069] It should be noted that since some noise is inevitable during signal transmission, affecting the charging effect and consequently the display effect, in practical implementation, an amplifier can be placed in each pixel P of the display device. Figure 2 The text does not show that, in this way, the image is magnified before the charging display, which effectively avoids the introduction of noise and ensures the display effect.

[0070] Based on the same publicly disclosed concept, such as Figure 3 As shown, this disclosure also provides an image signal processing apparatus, comprising:

[0071] The grayscale separation unit 70 includes multiple voltage comparators 71, the input terminals of each voltage comparator 71 are coupled to each other, and the output terminals of each voltage comparator 71 are coupled to each other. The grayscale separation unit 70 is used to output the input analog image signal from the target voltage comparator 71 among the multiple voltage comparators 71 that matches the grayscale voltage of the analog image signal, wherein each voltage comparator 71 corresponds to a different grayscale voltage.

[0072] In specific implementation, the number of the plurality of voltage comparators 71 can be set according to actual application needs, such as 256, and is not limited here. The input terminals of each voltage comparator 71 are coupled together, and the output terminals of each voltage comparator 71 are coupled together. The grayscale separation unit 70 can output the input analog image signal from the target voltage comparator 71 among the plurality of voltage comparators 71 that matches the grayscale voltage of the analog image signal. Since each voltage comparator 71 corresponds to a different grayscale voltage, multiple analog image signals input sequentially can flow sequentially into one of the voltage comparators 71 that matches its grayscale voltage. In this way, the grayscale voltages of the input analog image signals can be distinguished, thereby achieving effective processing of the analog image signal and ensuring the efficiency of signal processing.

[0073] In this disclosed embodiment, it is still combined with Figure 3 As shown, along the input direction of the analog image signal, the grayscale voltage corresponding to each voltage comparator 71 shows a decreasing trend. If the plurality of voltage comparators 71 includes 256 voltage comparators 71, including C0, C1, ..., C255, and the grayscale voltage corresponding to each voltage comparator 71 is G0, G1, ..., G255, along the input direction of the analog image signal, the magnitude of the grayscale voltage corresponding to each voltage comparator 71 shows a decreasing trend from G255 to G0. Furthermore, Figure 3 In the figure, v0, v1, ..., v255 are preset voltage values, and the magnitude of each voltage value decreases from v255 to v0. Since the grayscale values ​​of each voltage comparator 71 are different, the analog image signal can only be output from the voltage comparator 71 that matches its grayscale voltage. Therefore, the grayscale voltage of the analog image signal can be extracted by the grayscale separation unit 70 so that the processed signal can be directly used for display.

[0074] In an embodiment of the present disclosure, each voltage comparator 71 includes a window comparator 72. The window comparator 72 includes a first comparator 721, a second comparator 722, and a power supply terminal for providing a working power supply for the first comparator 721 and the second comparator 722. The input terminals of the window comparator 72 are respectively coupled to the non-inverting input terminal of the first comparator 721 and the inverting input terminal of the second comparator 722. The output terminals of the first comparator 721 and the second comparator 722 are both coupled to the output terminal of the window comparator 72. The inverting input terminal of the first comparator 721 is coupled to a first threshold voltage terminal for providing a first threshold voltage Ua through a first resistor R0. The non-inverting input terminal of the second comparator 722 is coupled to a second threshold voltage terminal for providing a second threshold voltage Ub through a second resistor R1. The analog image signal whose grayscale voltage is between the first threshold voltage Ua and the second threshold voltage Ub is output through the output terminal of the window comparator 72;

[0075] Among them, the first threshold voltage Ua and the second threshold voltage Ub corresponding to any two voltage comparators 71 among the multiple voltage comparators 71 are not the same. The voltage defined by the first threshold voltage Ua and the second threshold voltage Ub corresponding to each window comparator 72 is the grayscale voltage of the corresponding voltage comparator 71.

[0076] As Figure 4 shown is a schematic structural diagram of one of the voltage comparators 71 being a window comparator 72. The power supply terminal Vi is used to provide a working power supply for the first comparator 721 and the second comparator 722 in the window comparator 72. The analog image signal whose grayscale voltage is between the first threshold voltage Ua and the second threshold voltage Ub can be output through the output terminal of the window comparator 72. For example, Ui is an input signal. When Ub < Ui < Ua, the signal of Ui can pass through the window comparator 72 to the output terminal, and the voltage of the signal Uo output by the output terminal is equal to Ui. It should be noted that the magnitudes of the first threshold voltage Ua and the second threshold voltage Ub in the same window comparator 72 are not equal, the first threshold voltage Ua in different window comparators is not equal, and the second threshold voltage Ub is not equal either. Correspondingly, the voltages defined by the first threshold voltage Ua and the second threshold voltage Ub of each window comparator 72 are also not equal, that is, each window comparator 72 corresponds to a different grayscale voltage. In this way, it can be ensured that any analog image signal can be output from one of the window comparators 72, thereby realizing the separation of different analog image signals and improving the processing efficiency of the analog image signals.

[0077] In an embodiment of the present disclosure, still in combination with Figure 4As shown, each of the voltage comparators 71 further includes a voltage divider circuit coupled to the window comparator 72. The voltage divider circuit includes a third resistor R2 coupled to the power supply terminal Vi and the output terminal of the window comparator 72, respectively, and a fourth resistor R3 coupled to the output terminal of the window comparator 72 and ground, respectively. The voltage output by the analog image signal input through the input terminal of the window comparator 72 after passing through the output terminal of the corresponding window comparator 72 is the grayscale voltage of the analog image signal.

[0078] In the specific implementation process, the voltage Uo in the voltage divider circuit is the voltage of R3 after the voltage division by R2 and R3, that is, UR3=Vi / (R2+R3)*R3=Uo=Ui. In this way, it is ensured that there is no error between the output voltage Uo and the input voltage Ui, thereby ensuring the accuracy of data transmission. In practical applications, the first threshold voltage Ua and the second threshold voltage Ub of each voltage comparator 71 are different values. The first threshold voltage and the second threshold voltage of each voltage comparator 71 can be set as needed to ensure that the analog image signal of the corresponding gray level voltage passes through the corresponding voltage comparator 71. For example, for the voltage comparator 71 with a gray level of 180, its Ua is 180.5mV and its Ub is 179.5mV. Then, the input signal with a gray level of 180 and a voltage of 180mV meets the condition and passes through the voltage comparator 71, while voltages greater than or less than Ua and Ub cannot pass through.

[0079] In the embodiments disclosed herein, such as Figure 4 As shown, a switching diode 80 is also provided between the output terminals of each two adjacent voltage comparators 71. Along the input direction of the analog image signal, the cathode of the switching diode 80 is coupled to the output terminal of the previous voltage comparator 71, and the anode of the switching diode 80 is coupled to the output terminal of the next voltage comparator 71.

[0080] A switching diode 80 is also provided between the output terminals of each pair of adjacent voltage comparators 71. The switching diode 80 is essentially a reverse diode relative to the direction of current flow. The switching diode 80 can prevent the output of the voltage comparator 71 with high grayscale voltage from affecting the output of the low grayscale voltage, thereby ensuring the accuracy of signal transmission.

[0081] In the embodiments disclosed herein, such as Figure 5 As shown, the image signal processing device further includes a filter 90 coupled to the input terminal of each voltage comparator 71. The filter 90 is used to filter out noise in the analog image signal and input the noise-filtered analog signal to the grayscale separation unit 70.

[0082] In the specific implementation process, before inputting the analog image signal to be processed into the grayscale separation unit 70, noise in the analog image signal can be filtered out by a filter 90 coupled to the input terminal of each voltage comparator 71. Then, the noise-filtered analog signal is input into the grayscale separation unit 70, thereby ensuring the quality of signal transmission.

[0083] In the embodiments disclosed herein, such as Figure 6 As shown, the image signal processing device further includes a second amplifier 100 coupled to the output terminal of each voltage comparator 71, and the second amplifier 100 is used to amplify the noise-filtered analog signal.

[0084] In the specific implementation process, the noise-filtered analog signal output by the grayscale separation unit 70 can also be amplified by the second amplifier 100 coupled to the output terminal of each voltage comparator 71, thereby ensuring the reliability of subsequent signal transmission.

[0085] Based on the same publicly disclosed concept, such as Figure 7 As shown in the embodiments of this disclosure, an image signal acquisition device is also provided, comprising:

[0086] The array comprises multiple pixel sensors 110, multiple first signal lines 120 extending along the row direction and multiple second signal lines 130 extending along the column direction, each coupled to the multiple pixel sensors 110; a row selection controller 140 coupled to each first signal line 120; a column selection controller 150 coupled to the first end of each second signal line 130; timing control circuits coupled to the row selection controller 140 and the column selection controller 150, respectively; and an output bus 170 coupled to the second end of each second signal line 130; wherein:

[0087] The plurality of image sensors 110 are configured to acquire image information from the outside world and convert the image information into analog image signals; the row selection controller 140 is configured to sequentially output scanning signals to a plurality of first signal lines 120; the column selection controller 150 is configured to control a plurality of column control switches 180 to sequentially open to output reference voltages to the corresponding first signal lines 120 in order to extract the analog signals generated by exposure on the corresponding image sensors 110; the output bus 170 is configured to output the analog signals after exposure.

[0088] In practical implementation, the number of the plurality of image sensors 110 can be set according to actual application needs. For example, the number of the plurality of image sensors 110 can be set according to the acquisition resolution of the image signal acquisition device 300, which is not limited here. Correspondingly, the number of first signal lines 120 and second signal lines 130 coupled to the plurality of image sensors 110 can be set according to actual application needs, which is not limited here. The plurality of image sensors 110 can acquire image information from the outside world and convert the image information into analog image signals. The line selection controller 140 coupled to each of the first signal lines 120 can sequentially output scanning signals to the plurality of first signal lines 120. In this way, the image sensors 110 in the corresponding rows can be exposed line by line through the line selection controller 140. The column selection controller 150, coupled to the first terminal of each of the second signal lines 130, can control multiple column control switches 180 to sequentially open, thereby outputting a reference voltage to the corresponding first signal line 120 to extract the analog signal generated by exposure on the corresponding image sensor 110. This enables sequential exposure of each column of image sensors 110 in the same row. Furthermore, the output bus 170, coupled to the second terminal of each of the second signal lines 130, can output the analog signal after exposure, thus realizing the acquisition and output of image signals. Since only analog signals are transmitted during the entire image signal acquisition process, the real-time performance of image acquisition is improved.

[0089] In this embodiment of the disclosure, it is still as Figure 7 As shown, each image sensor 110 includes a photodiode 190 and a row scan control switch 200. By controlling the on and off of the row scan control switch 200 and the column control switch 180 through the row selection controller 140 and the column selection controller 150, the exposure control of the corresponding image sensor 110 is realized, thereby ensuring the acquisition performance of the image signal acquisition device.

[0090] It should be noted that the column selection controller 150 may include multiple cascaded shift register units, the output of each shift register unit being coupled to a corresponding second signal line 130. The row selection controller 140 may also include multiple cascaded shift register units, the output of each shift register unit being coupled to a corresponding first signal line 120. In this way, exposure control of the corresponding image sensor 110 can be achieved through the corresponding shift controllers. Furthermore, the gate of each row scan control switch 200 is coupled to the corresponding first signal line 120, its first electrode is coupled to the cathode of the photodiode 190, and its second electrode is coupled to the corresponding second signal line 130. The gate of each column control switch 180 is coupled to a corresponding shift register unit.

[0091] In specific implementation, the image signal acquisition device can be a complementary metal-oxide-semiconductor (CMOS) sensor, a charge-coupled device (CCD) sensor, or other devices with image acquisition functions, which are not limited here.

[0092] Based on the same publicly disclosed concept, such as Figure 8 As shown in the embodiments of this disclosure, a display system is also provided, comprising:

[0093] An image signal acquisition device 300, a display device 400, and an image signal processing device 500 coupled to the image signal acquisition device 300 and the display device 400, respectively; wherein:

[0094] The image signal acquisition device 300 is used to convert the acquired image information into analog image signals and transmit them to the image signal processing device 500;

[0095] The image signal processing device 500 is used to determine the grayscale voltage of the analog image signal and transmit the analog image signal to the display device 400;

[0096] The display device 400 is used to display the analog image signal.

[0097] In specific implementation, the image signal acquisition device 300 can be located on a non-display surface opposite the display surface of the display device 400, or it can be located in another position different from the display device 400 in the display system. The specific configuration can be determined according to the actual application and is not limited here. The image signal processing device 500 converts the acquired image information into an analog image signal and transmits it to the display device 400. Then, the image signal processing device 500 determines the grayscale voltage of the analog image signal and transmits it to the display device 400, which then displays the analog image signal. Because in the display system, after the image signal acquisition device 300 converts the acquired image information into an analog image signal, the image signal processing device 500 can directly determine the grayscale voltage of the analog image signal. Subsequently, the corresponding analog image signal is directly displayed by the display device 400. The entire process only involves the acquisition and transmission of analog signals, thereby avoiding the transmission delay from image acquisition to image display in the display system and improving the real-time performance of the display system from image acquisition to image display.

[0098] It should be noted that the display system can be a mixed reality system. The principle of the display system in solving the problem is similar to that of the aforementioned display device 400, image signal acquisition device 300 and image signal processing device 500. Therefore, the implementation of this display system can refer to the implementation in the foregoing section, and the repeated parts will not be described again.

[0099] In this embodiment of the disclosure, the image signal processing apparatus 500 includes:

[0100] The grayscale separation unit 70 includes multiple voltage comparators 71, the input terminals of each voltage comparator 71 are coupled to each other, and the output terminals of each voltage comparator 71 are coupled to each other. The grayscale separation unit 70 is used to output the input analog image signal from the target voltage comparator 71 among the multiple voltage comparators 71 that matches the grayscale voltage of the analog image signal, wherein each voltage comparator 71 corresponds to a different grayscale voltage.

[0101] It should be noted that if the image signal acquisition device 300 is an RGB array, a pixel P in the display device 400 is described according to RGB 24, that is, a pixel P can be described by three bytes, with eight bits each for red pixel r, green pixel g and blue pixel b. The grayscale separation unit 70 includes 256 voltage comparators 71, which correspond to grayscale voltages from 0 to 255 respectively.

[0102] In this embodiment of the disclosure, the display device 400 includes:

[0103] The array comprises multiple pixels P, and multiple scan lines G extending in the row direction, multiple data lines D extending in the row direction, and multiple control lines C extending in the column direction, all coupled to the multiple pixels P. A data bus B is coupled to each data line D, and multiple first switching circuits 10 corresponding to one data line D, and multiple second switching circuits 20 corresponding to each pixel P. Each pixel P includes a pixel electrode.

[0104] The first switching circuit 10 is configured to control the coupling of data line D with the data bus B in response to the signal of the corresponding scan line G; the second switching circuit 20 is configured to control the pixel electrode of each pixel P to be coupled with the corresponding data line D in response to the signal of the corresponding control line C and the signal of the corresponding scan line G.

[0105] In this embodiment of the disclosure, the image signal acquisition device 300 includes:

[0106] The array comprises multiple pixel sensors 110, multiple first signal lines 120 extending along the row direction and multiple second signal lines 130 extending along the column direction, each coupled to the multiple pixel sensors 110; a row selection controller 140 coupled to each first signal line 120; a column selection controller 150 coupled to the first end of each second signal line 130; a timing control circuit 160 coupled to the row selection controller 140 and the column selection controller 150; and an output bus 170 coupled to the second end of each second signal line 130; wherein:

[0107] The plurality of image sensors 110 are configured to acquire image information from the outside world and convert the image information into analog image signals; the row selection controller 140 is configured to sequentially output scanning signals to a plurality of first signal lines 120; the column selection controller 150 is configured to control a plurality of column control switches 180 to sequentially open to output reference voltages to the corresponding first signal lines 120 in order to extract the analog signals generated by exposure on the corresponding image sensors 110; the output bus 170 is configured to output the analog signals after exposure.

[0108] It should be noted that in the display system, the arrangement of the multiple pixel sensors 110 included in the image signal acquisition device 300 is the same as the arrangement of the multiple pixels P included in the display device 400, and the number of both is the same. For example, if the multiple pixel sensors 110 are arranged in M ​​rows and N columns, then the multiple pixels P are also arranged in M ​​rows and N columns. After the image signal acquisition device 300 exposes the s-th row of pixel sensors 110 sequentially from left to right, the grayscale separation unit 70 transmits the exposed analog signal to the corresponding s-th row of pixel P in the display device 400 according to the exposure order. The display device 400 also illuminates each pixel P in the s-th row of pixel P sequentially from left to right. In other words, the image signal acquisition device 300 adopts row-by-row exposure and row-by-row output, and the display device 400 correspondingly illuminates and displays row by row.

[0109] In the embodiments disclosed herein, such as Figure 9 As shown, the display device 400 also includes an application processor 410. If the display device 400 is in a human-computer interaction mode, the application processor 410 is used to render and generate virtual image data, obtain the rendered image data, and send the rendered image data to multiple pixels P in the display device 400 so that the multiple pixels P can display the rendered image data.

[0110] When the display system is in the mode of capturing external scenes, the plurality of pixels P display the analog image signal.

[0111] In practical implementation, the display system can have multiple display modes, such as a virtual display mode under the human-computer interaction mode, and a real-scene display mode under the external scene capture mode. To ensure compatibility between the human-computer interaction mode and the external scene capture mode, the display system, in addition to the image signal processing device 500, also includes an application processor 410. The display driver chip on the display device 400 can also have two interfaces, or a single interface that can be switched, allowing the display device 400 to display both the image processed by the image signal processing device 500 and the image processed by the application processor 410 in a time-division multiplexing manner, thus achieving compatibility between the human-computer interaction mode and the external scene capture mode. Furthermore, to enable switching between the human-computer interaction mode and the external scene capture mode, a physical button on the application processor 410 can be used for one-click switching between different modes.

[0112] If the display system is in human-computer interaction mode, the image signal processing device 500 is turned off. The application processor 410 can then render and generate virtual image data, which is then sent to multiple pixels P in the display device 400 for display. In this mode, the user can experience a virtual world through the display system and interact with it via the application processor 410.

[0113] When the display system is in the external scene capture mode, the image signal processing device 500 is activated. The image signal processing device 500 processes the image acquired by the image signal acquisition device 300, ensuring real-time image acquisition in the external scene capture mode. In this mode, the user can obtain real-time information about the real world through the display system. In practical applications, users can choose the display mode of the display system according to their actual needs, thus ensuring a good user experience.

[0114] Furthermore, besides being independently located in the display device 400, the image signal processing device 500 can also be integrated into the display driver chip of the display device 400. The data bus controller 40 and the line drive timing controller in the display device 400 can also be integrated into the display driver chip, thereby achieving an integrated design of the display system and ensuring a thin and light design. Of course, the specific design of the image signal acquisition device 300 and the image signal processing device 500 can be configured according to actual application needs and is not limited here.

[0115] It should be noted that the accompanying drawings provided in this disclosure only illustrate a portion of the circuit design in some pixels P of the image signal acquisition device 300 and the display device 400. Therefore, in specific implementations, the actual images of the image signal acquisition device 300 and the display device 400 are not limited to these drawings and can be flexibly designed according to actual applications, which will not be detailed here. Moreover, the display system may also include other devices besides the structures mentioned above, which can be referred to in the relevant descriptions in the prior art, and will not be repeated here.

[0116] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0117] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A display device, wherein, include: The array comprises multiple pixels, multiple scan lines extending along the row direction coupled to the multiple pixels, multiple data lines extending along the row direction and multiple control lines extending along the column direction, a data bus coupled to each data line, multiple first switching circuits corresponding to each data line, and multiple second switching circuits corresponding to each pixel. Each pixel includes a pixel electrode. The first switching circuit is configured to control the coupling of the corresponding data line with the data bus in response to the signal of the corresponding scan line; the second switching circuit is configured to control the pixel electrode of each pixel to be coupled with the corresponding data line in response to the signal of the corresponding control line and the signal of the corresponding scan line; the data bus is used to carry analog image signals and transmit the analog image signals to each pixel to directly drive the corresponding pixel display.

2. The apparatus of claim 1, wherein, The display device further includes a row drive timing control circuit coupled to each scan line, and a data bus controller coupled to each control line, wherein: The row drive timing control circuit is configured to output scan signals sequentially to each scan line and its corresponding first switch circuit; the data bus controller is configured to output control signals sequentially to each control line.

3. The apparatus of claim 2, wherein, The first switching circuit includes a first transistor, and the second switching circuit includes a second transistor and a third transistor. The gates of the first transistor and the third transistor are both coupled to corresponding scan lines. The first electrode of the first transistor is coupled to the data bus. The second electrodes of the first transistor and the first electrodes of the second transistor are both coupled to corresponding data lines. The gate of the second transistor is coupled to a corresponding control line. The second electrode of the second transistor is coupled to the first electrode of the third transistor. The second electrode of the third transistor is coupled to the pixel electrode of the corresponding pixel.

4. The apparatus of claim 3, wherein, The data bus controller includes multiple cascaded shift register units. The signal output terminal of each shift register unit is coupled to a corresponding control line. In every two adjacent shift register units, the signal input terminal of the next-level shift register unit is coupled to the signal output terminal of the previous-level shift register unit. The other signal input terminal of each shift register unit is coupled to a bus timing controller. The bus timing controller is configured to output a clock pulse signal and load the clock pulse signal to each shift register unit, thereby connecting the data bus controller and the corresponding column pixel on the corresponding row pixel to charge the corresponding pixel.

5. The apparatus according to any one of claims 1-4, wherein, The display device further includes a first amplifier coupled to the data bus, the first amplifier being used to receive analog image signals from the data bus, amplify the analog image signals, and output the amplified analog signals to each data line.

6. An image signal processing apparatus, wherein, include: A grayscale separation unit includes multiple voltage comparators, the input terminals of which are coupled to each other, and the output terminals of which are coupled to each other. The grayscale separation unit is used to output the target voltage comparator that matches the grayscale voltage of the input analog image signal from the multiple voltage comparators, and transmit it to each pixel in the display device through a data bus to directly drive the corresponding pixel display. Each voltage comparator corresponds to a different grayscale voltage. Each voltage comparator includes a window comparator, which comprises a first comparator, a second comparator, and a power supply terminal for providing operating power to the first and second comparators. The input terminal of the window comparator is coupled to the non-inverting input terminal of the first comparator and the inverting input terminal of the second comparator, respectively. The output terminals of the first and second comparators are both coupled to the output terminal of the window comparator. The inverting input terminal of the first comparator is coupled to a first threshold voltage terminal for providing a first threshold voltage through a first resistor. The non-inverting input terminal of the second comparator is coupled to a second threshold voltage terminal for providing a second threshold voltage through a second resistor. The analog image signal, whose grayscale voltage is between the first threshold voltage and the second threshold voltage, is output through the output terminal of the window comparator. Among the plurality of voltage comparators, the first threshold voltage and the second threshold voltage corresponding to any two voltage comparators are different, and the voltage defined by the first threshold voltage and the second threshold voltage corresponding to each window comparator is the grayscale voltage of the corresponding voltage comparator.

7. The apparatus of claim 6, wherein, Along the input direction of the analog image signal, the grayscale voltage corresponding to each voltage comparator shows a decreasing trend.

8. The apparatus of claim 6, wherein, Each voltage comparator also includes a voltage divider circuit coupled to the window comparator. The voltage divider circuit includes a third resistor coupled to the power supply terminal and the output terminal of the window comparator, and a fourth resistor coupled to the output terminal of the window comparator and ground, respectively. The voltage output by the analog image signal input through the input terminal of the window comparator after passing through the output terminal of the corresponding window comparator is the grayscale voltage of the analog image signal.

9. The apparatus of claim 8, wherein, A switching diode is also provided between the output terminals of each pair of adjacent voltage comparators. Along the input direction of the analog image signal, the cathode of the switching diode is coupled to the output terminal of the previous voltage comparator, and the anode of the switching diode is coupled to the output terminal of the next voltage comparator.

10. The apparatus of claim 9, wherein, The image signal processing device further includes filters coupled to the input terminals of each voltage comparator. The filters are used to filter out noise in the analog image signal to be input and input the noise-filtered analog image signal to the grayscale separation unit.

11. The apparatus of claim 10, wherein, The image signal processing device further includes a second amplifier coupled to the output of each voltage comparator. The second amplifier is used to amplify the analog image signal output by the grayscale separation unit to obtain an amplified analog signal.

12. An image signal acquisition device, wherein, include: The array comprises multiple pixel sensors, multiple first signal lines extending along the row direction and multiple second signal lines extending along the column direction, each coupled to the multiple pixel sensors; a row selection controller coupled to each first signal line; a column selection controller coupled to the first end of each second signal line; timing control circuits coupled to the row selection controller and the column selection controller, respectively; and an output bus coupled to the second end of each second signal line; wherein: The plurality of pixel sensors are configured to acquire image information from the outside world and convert the image information into analog image signals; the row selection controller is configured to sequentially output scanning signals to a plurality of first signal lines; the column selection controller is configured to control a plurality of column control switches to sequentially open to output reference voltages to the corresponding first signal lines to extract the analog signals generated by exposure on the corresponding pixel sensors; the output bus is configured to output the analog signals after exposure and transmit the analog signals after exposure to the image signal processing device as described in any one of claims 6-11, so that the grayscale separation unit in the image signal processing device transmits the analog signals after exposure to each pixel in the display device through the data bus to directly drive the corresponding pixel display.

13. The apparatus of claim 12, wherein, Each pixel includes a photodiode and a line scan control switch.

14. A display system, wherein, include: An image signal acquisition device, a display device, and an image signal processing device coupled to the image signal acquisition device and the display device respectively; wherein: The image signal acquisition device is used to convert the acquired image information into analog image signals and transmit them to the image signal processing device; The image signal processing device is used to determine the grayscale voltage of the analog image signal and transmit the analog image signal to the display device; The display device is used to carry the analog image signal through a data bus and transmit the analog image signal to each pixel to directly drive the corresponding pixel to display; The display device includes: The array comprises multiple pixels, and multiple scan lines extending in the row direction, multiple data lines extending in the row direction, and multiple control lines extending in the column direction, each coupled to the multiple pixels; a data bus coupled to each data line; multiple first switching circuits corresponding to each data line; and multiple second switching circuits corresponding to each pixel. Each pixel includes a pixel electrode. The first switching circuit is configured to control the coupling of the data line with the data bus in response to the signal of the corresponding scan line; the second switching circuit is configured to control the coupling of the pixel electrode of each pixel with the corresponding data line in response to the signal of the corresponding control line and the signal of the corresponding scan line.

15. The system of claim 14, wherein, The image signal processing device includes: A grayscale separation unit includes multiple voltage comparators, the input terminals of which are coupled together, and the output terminals of which are coupled together. The grayscale separation unit is used to output the input analog image signal from a target voltage comparator among the multiple voltage comparators that matches the grayscale voltage of the analog image signal. Each voltage comparator corresponds to a different grayscale voltage.

16. The system of claim 14, wherein, The image signal acquisition device includes: The array comprises multiple pixel sensors, multiple first signal lines extending along the row direction and multiple second signal lines extending along the column direction, each coupled to the multiple pixel sensors; a row selection controller coupled to each first signal line; a column selection controller coupled to the first end of each second signal line; timing control circuits coupled to the row selection controller and the column selection controller, respectively; and an output bus coupled to the second end of each second signal line; wherein: The plurality of image sensors are configured to acquire image information from the outside world and convert the image information into analog image signals; the row selection controller is configured to output scanning signals to a plurality of first signal lines in sequence; the column selection controller is configured to control a plurality of column control switches to open in sequence to output reference voltages to the corresponding first signal lines in order to extract the analog signals generated by exposure on the corresponding image sensors; the output bus is configured to output the analog signals after exposure.

17. The system according to any one of claims 14-16, wherein, The display device further includes an application processor. If the display device is in a human-computer interaction mode, the application processor is used to render and generate virtual image data, obtain the rendered image data, and send the rendered image data to multiple pixels in the display device so that the multiple pixels display the rendered image data. When the display system is in the mode of capturing external scenes, the plurality of pixels display the analog image signal.

Images