Memory device with vertical transistor and method of forming the same
By adopting vertical transistors and a three-dimensional memory architecture, the problems of high density and cost of planar memory cells are solved, achieving high efficiency in memory cell density and performance improvement.
CN116097914BActive Publication Date: 2026-06-02YANGTZE MEMORY TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2021-09-30
- Publication Date
- 2026-06-02
Smart Images
Figure CN116097914B_ABST
Abstract
In certain aspects, a memory device includes a semiconductor layer including a peripheral circuit of peripheral transistors in contact with the semiconductor layer, an array of memory cells disposed alongside the semiconductor layer and the peripheral circuit, and bit lines coupled to the memory cells. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage cell coupled to the vertical transistor. Each of the bit lines extends in a second direction perpendicular to the first direction. A respective one of the bit lines and a respective storage cell are coupled to opposite ends of each of the memory cells in the first direction.
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