A photolithography machine exposure dose control system

Abstract

The present application provides an exposure dose control system for a lithography machine, comprising: a variable attenuator, a beam stabilization unit, an energy harvesting unit, a laser, a control device and a host computer; the control device comprises a multi-core heterogeneous controller and an FPGA controller, and the multi-core heterogeneous controller comprises an ARM core and a DSP core; the ARM core is used to perform application logic control on the variable attenuator, the beam stabilization unit, the energy harvesting unit and the laser; the DSP core is used to drive and control the variable attenuator, the beam stabilization unit, the energy harvesting unit and the laser; the FPGA controller is used to perform parallel control and multi-channel AD high-speed acquisition on the variable attenuator, the beam stabilization unit, the energy harvesting unit and the laser; the host computer is used to issue functional commands related to exposure dose control to the ARM core; the present application adopts a multi-core heterogeneous controller (DSP core and ARM core) + FPGA architecture to simplify system links and the complexity of software and hardware, thereby improving the real-time performance of the control system and enabling the control system to implement complex functions.

Description

Technical Field

[0001] The present invention relates to the technical field of photolithography machines, and in particular to an exposure dose control system for a photolithography machine. Background Art

[0002] Exposure dose control is an essential component of stepper and scanner projection lithography systems. The Dose Control Board (DCB) is a key hardware component within the exposure dose control module. The DCB serves as the interface between the wafer scanning control system and its hardware illumination subsystem. Dose control is the DCB's most important task: when exposure is required, the DCB is responsible for triggering the laser and measuring the pulse energy. Specifically, the DCB's main functions include interacting with the host computer, executing commands sent by the host computer and returning data; triggering the excimer laser (LASER) to output pulsed laser light; controlling the transmittance of the variable attenuator (VA); acquiring laser pulse energy in real time through the energy monitoring unit (EDU) and point detector (ESS); and controlling the beam stabilization unit (BSTSA).

[0003] like Figure 1 As shown in the figure, the traditional exposure dose control system utilizes a DCB board 1 (FPGA + DSP) + DCB board 2 (FPGA + MCU) + VME bus chassis architecture. The exposure dose control system primarily coordinates and controls the VA, BSTSA, EDU / ESS, and LASER. Implementing these functions requires two DCB boards, one chassis, and four programmable chips. To control a single unit, the data transmission link is: host computer -> DCB board 2's MCU -> DCB board 2's FPGA -> VME chassis bus -> DCB board 1's FPGA -> DCB board 1's DSP -> DCB board 1's FPGA -> relevant unit. This indicates that to control a single unit, the data link must go through six steps to achieve the desired functional control.

[0004] Therefore, the traditional exposure dose control system has the following defects:

[0005] 1. The existing lithography machine exposure dose control system has shortcomings such as multiple boards, long communication links, decentralized software, and cumbersome electrical connections;

[0006] 2. The large number of boards and long communication links will limit the real-time performance of the dose control system, making it difficult to implement complex functions, such as the VA transmittance self-calibration function. Summary of the Invention

[0007] In response to the problems existing in the traditional exposure dose control system of a lithography machine, the present application provides an exposure dose control system for a lithography machine. It adopts the technology of combining multi-core heterogeneity and FPGA to solve the problems of long exposure dose control link, complex hardware, and cumbersome electrical connections in the lithography machine lighting, improves the real-time performance of the system, and can simultaneously realize functions such as self-calibration of the transmittance of the variable attenuator in the exposure dose control.

[0008] The technical solutions provided by the present invention are as follows:

[0009] The present invention provides an exposure dose control system for a photolithography machine, comprising: a variable attenuator, a beam stabilization unit, an energy collection unit, a laser, a control device, and a host computer;

[0010] The control device includes a multi-core heterogeneous controller and an FPGA controller, the multi-core heterogeneous controller includes an ARM core and a DSP core, and the ARM core, DSP core and FPGA controller are integrated on a DCB board;

[0011] The ARM core is used to perform application logic control on the variable attenuator, beam stabilization unit, energy harvesting unit and laser;

[0012] The DSP core is used to drive and control the variable attenuator, beam stabilization unit, energy collection unit and laser;

[0013] The FPGA controller is used to perform parallel control and multi-channel AD high-speed acquisition on the variable attenuator, beam stabilization unit, energy collection unit and laser;

[0014] The host computer is used to send function commands related to exposure dose control to the ARM core;

[0015] The ARM core performs network communication with the host computer, receives and parses the functional commands issued by the host computer, and performs real-time inter-core communication with the DSP core to send the parsed commands and parameters to the DSP core. The DSP core performs real-time data interaction with the FPGA controller through a high-speed bus to send the received commands and parameters to the FPGA controller. The FPGA controller controls the corresponding variable attenuator, beam stabilization unit, energy collection unit, and laser to perform corresponding functional operations according to the received commands and parameters.

[0016] Further preferably, the light emission period of the laser is 250 μs, and there is a limited relationship between the triggering timing of the laser and the synchronization timing of the energy collection unit and the synchronization timing of the beam stabilization unit for energy integration. The limited relationship enables the DSP core and the FPGA controller to complete the adjustment of the variable attenuator transmittance, the beam stabilization control of the beam stabilization unit, the beam energy collection of the energy collection unit, and the control of the laser light emission within the light emission period of the laser.

[0017] Further preferably, the limiting relationship between the trigger timing of the laser and the synchronization timing of the energy collection unit is: relative to the laser light emitting synchronization signal, the energy collection unit is triggered with a delay of 3.9us, and the time error of the delayed trigger relative to the laser light emitting synchronization signal is less than 40ns.

[0018] Further preferably, the DSP core writes the delayed trigger time 3.9 us into the FPGA controller by writing to the memory via a high-speed bus when powered on.

[0019] Further preferably, the energy harvesting unit includes an EDU and an ESS, and a synchronization error time between the EDU and the ESS is less than 20 ns.

[0020] Further preferably, the limiting relationship between the trigger timing of the laser and the synchronization timing of the beam stabilization unit for energy integration is: relative to the laser light emitting synchronization signal, the beam stabilization unit is synchronously triggered to perform energy integration, and the beam stabilization unit is triggered to reset the energy integration at an interval of 100us, and the time errors of the synchronous triggering and the interval triggering relative to the laser light emitting synchronization signal are both less than 40ns.

[0021] Further preferably, the DSP core writes the interval trigger time 100 us into the FPGA controller by writing to the memory via a high-speed bus when powered on.

[0022] Further preferably, during the light emission period of the laser, the DSP core is also used to self-calibrate the transmittance of the variable attenuator.

[0023] Further preferably, during the self-calibration of the transmittance of the variable attenuator by the DSP core, the rate of change of the motor position in the variable attenuator is automatically adjusted by the expert PID, so that the actual transmittance of the variable attenuator approaches the expected transmittance.

[0024] The lithography machine exposure dose control system provided by the present invention adopts an ARM core + DSP core + FPGA architecture to solve the problems of long exposure dose control links, complex hardware, and cumbersome electrical connections in traditional lithography machine lighting. It also solves the problem of limited real-time performance of the control system. At the same time, by optimizing the resource division and inter-core communication technology between the ARM core, DSP core and FPGA controller, the system performance is guaranteed to realize complex functions such as self-calibration of the variable attenuator transmittance in exposure dose control. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is the schematic diagram of the exposure dose control system of an existing lithography machine;

[0026] Figure 2 This is the schematic diagram of the exposure dose control system of the photolithography machine in this application;

[0027] Figure 3 Implement logic diagrams for ARM core, DSP core, and FPGA controller;

[0028] Figure 4 Figure 2 is the energy harvesting control timing diagram;

[0029] Figure 5 This is the timing diagram of the beam position control. DETAILED DESCRIPTION

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific embodiments of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings and other embodiments can be obtained based on these drawings without inventive work.

[0031] The terms involved in this application are explained as follows:

[0032] DCB: exposure dose control board;

[0033] VA: variable attenuator;

[0034] BSTSA: beam stabilization unit;

[0035] EDU: Energy Monitoring Unit;

[0036] LASER: laser;

[0037] ESS: point detector;

[0038] IPC: Inter-core processor communication.

[0039] The present application provides a lithography machine exposure dose control system to solve the problems of long exposure dose control link, complex hardware, and cumbersome electrical connections in traditional lithography machine lighting, and also solves the problem of limited real-time performance of the control system.

[0040] The schematic diagram of the exposure dose control system of the lithography machine provided in this application is as follows Figure 2 As shown, the device comprises a variable attenuator 100, a beam stabilization unit 200, an energy collection unit 300, a laser 400, a control device 500 and a host computer 600; wherein the control device 500 comprises a multi-core heterogeneous controller and an FPGA controller 503, the multi-core heterogeneous controller comprises an ARM core 501 and a DSP core 502, the ARM core 501, the DSP core 502 and the FPGA controller 503 are integrated on a DCB board; the ARM core 501 is used to control the variable attenuator 100, the beam stabilization unit 200, the energy collection unit 300, the laser 400, the control device 500 and the host computer 600; wherein, ... 0, energy collection unit 300 and laser 400 for application logic control; DSP core 502 is used to drive and control the variable attenuator 100, beam stabilization unit 200, energy collection unit 300 and laser 400; FPGA controller 503 is used to perform parallel control and multi-channel AD high-speed acquisition of the variable attenuator 100, beam stabilization unit 200, energy collection unit 300 and laser 400; the host computer 600 is used to send functional commands related to exposure dose control to the ARM core 501.

[0041] The ARM core 501 communicates with the host computer 600 over the network, receives and parses the functional commands issued by the host computer 600, and performs real-time inter-core communication with the DSP core 502 to send the parsed commands and parameters to the DSP core 502. The DSP core 502 performs real-time data interaction with the FPGA controller 503 through the high-speed bus to send the received commands and parameters to the FPGA controller 503. The FPGA controller 503 controls the corresponding variable attenuator 100, beam stabilization unit 200, energy collection unit 300, and laser 400 to perform corresponding functional operations according to the received commands and parameters.

[0042] Specifically, the ARM core mainly runs RTlinux, which is mainly used to implement TCP network communication with the host computer, application logic control of each unit, and high-speed inter-core IPC real-time communication with the DSP core;

[0043] The DSP core mainly implements the exposure dose control algorithm, high-speed inter-core data interaction with the ARM core, and high-speed GPMC bus communication with the FPGA controller;

[0044] FPGA controller mainly uses its parallel and high-speed characteristics to realize the control of multiple external devices and multi-channel synchronous AD analog-to-digital conversion.

[0045] That is, in this application, the DSP core of the multi-core heterogeneous controller is responsible for executing tasks with relatively high real-time requirements, including executing complex algorithm operations, realizing exposure dose control, realizing high-speed parallel communication with the FPGA controller, and performing real-time data interaction between cores with the ARM core to replace the original VME bus; the ARM core runs a real-time embedded system, which is mainly used to realize the application logic control of each device and network communication with the host computer, and realize real-time communication between cores with the DSP core; the FPGA controller mainly uses its parallel and high-speed characteristics to realize the control of multiple external devices and multi-channel AD high-speed acquisition functions, and performs real-time data interaction with the DSP core through the high-speed bus.

[0046] Further, by Figure 1 It can be seen that if the existing exposure dose control system wants to achieve unit control, the data transmission link is: host computer -> MCU of DCB board 2 -> FPGA of DCB board 2 -> VME chassis bus -> FPGA of DCB board 1 -> DSP of DCB board 1 -> FPGA of DCB board 1 -> relevant unit. It can be seen that to achieve the control of a unit, its data link must go through six steps to achieve the corresponding functional control.

[0047] To control a single unit, the exposure dose control system provided by this application requires a data transmission link: host computer -> multi-core heterogeneous chip -> FPGA -> related unit. Therefore, the exposure dose control system provided by this application has a short data link and high real-time performance.

[0048] Therefore, this application adopts a multi-core heterogeneous controller (DSP core and ARM core) + FPGA architecture to replace the original (DSP and FPGA) + VME chassis + (MCU and FPGA) architecture to achieve the purpose of simplifying system links and software and hardware complexity.

[0049] The working principle diagram of the ARM core, DSP core and FPGA controller in the lithography machine exposure dose control system provided in this application is as follows Figure 3 As shown, since the dosage control system controls many peripherals, each peripheral has many functions. Figure 3 This is the top-down implementation logic for the entire control system software. First, the host computer sends a function command to the ARM core via TCP network communication. The ARM core then parses the command and parameters and passes them to the DSP core via inter-core communication (IPC) and shared memory. The DSP core then calls the underlying driver and exchanges data with the FPGA controller by writing to memory via a high-speed bus. The FPGA controller performs corresponding operations based on the memory address and contents. The data is then returned to the DSP core via an interrupt trigger. The DSP core then sends it to the ARM core. Finally, the data returns to the host computer through the ARM core.

[0050] The variable attenuator 100, beam stabilization unit 200, energy collection unit 300, and laser 400 involved in this application are well known to those skilled in the art and are not described in detail in this application. For example, the variable attenuator 100 is used to attenuate the energy of the exposure beam; the beam stabilization unit 200 is used to monitor and adjust the position and direction of the exposure beam; the energy collection unit 300 is used to monitor the single pulse energy of the exposure beam in real time; and the laser 400 provides a light source for the exposure system.

[0051] In the present application, since the ARM core 501, the DSP core 502 and the FPGA controller 503 are integrated on a DCB board, the DCB board sends a command to the VA through the RS232 serial port to make the motor drive the variable transmittance plate to rotate to realize the attenuation of the laser energy, or obtain the feedback information of the VA; the DCB board provides the BSTSA with synchronization and reset signals according to the triggering and synchronization timing of the laser 400 so that the BSTSA integrates and amplifies the current beam position and pointing signal; at the same time, the DCB board can exchange data with the BSTSA core board through the RS422 serial port, send beam stabilization commands to the BSTSA or receive information; the DCB board collects the output voltage of the EDU&ESS through the analog-to-digital converter; the DCB board controls the excimer laser or obtains its current status information through the communication interface; monitors the laser status in real time through the parallel interface; and realizes the output triggering and synchronization of the laser through the optical fiber interface.

[0052] The laser 400 of this application has a frequency of 4 kHz and a light emission period of 250 μs. The control device 500 is required to process all peripheral control and requests within 250 μs. For example, the control device 500 must fully process all control and requests from the variable attenuator 100, beam stabilization unit 200, energy harvesting unit 300, and laser 400 within 250 μs.

[0053] Furthermore, in the present application, with the light emission period of the laser 400 being 250 μs, a restricted relationship is set between the trigger timing of the laser 400 and the synchronization timing of the energy collection unit 300 and the synchronization timing of the beam stabilization unit 200 for energy integration. This restricted relationship enables the DSP core 502 and the FPGA controller 503 to complete the adjustment of the transmittance of the variable attenuator 100, the beam stabilization control of the beam stabilization unit 200, the beam energy collection of the energy collection unit 300, and the control of the light emission of the laser 400 within the light emission period of the laser 400.

[0054] Specifically, the limiting relationship between the trigger timing of the laser 400 and the synchronization timing of the energy harvesting unit 300 is: relative to the laser 400 light synchronization signal, the energy harvesting unit 300 is triggered with a delay of 3.9us, and the time error of the delayed trigger relative to the laser light synchronization signal is less than 40ns.

[0055] Furthermore, when the DSP core 502 is powered on, the delayed trigger time 3.9 μs is written into the FPGA controller 503 via a high-speed bus memory.

[0056] Furthermore, the energy harvesting unit 300 of the present application includes an EDU and an ESS, and the synchronization error time between the EDU and the ESS is less than 20 ns.

[0057] The timing control diagram of the lithography machine exposure dose control system of the present application controlling the energy collection unit 300 to perform corresponding beam energy collection is shown in FIG. Figure 4 As shown, the specific control process includes the following:

[0058] 1. The DSP core initializes the variable attenuator and sets the transmittance value of the variable attenuator;

[0059] 2. The DSP core initializes the beam stabilization unit and sets the beam position;

[0060] 3. FPGA controller controls the laser light output;

[0061] 4. The FPGA controller prepares to obtain N sets of energy values ​​of the EDU / ESS, where N is a positive integer greater than 1;

[0062] a. FPGA controller captures the laser light synchronization signal;

[0063] b. Relative to the laser light synchronization signal, the FPGA controller triggers EDU / ESS high-speed synchronous sampling at an interval of 3.9us (error less than 40ns), and the EDU / ESS synchronization error time is less than 20ns;

[0064] c. The FPGA controller repeats steps a and b above N times according to the instructions;

[0065] 5. The FPGA controller and DSP core store EDU / ESS energy sampling values ​​respectively;

[0066] 6. The FPGA controller stops the laser from emitting light.

[0067] In the present application, the limiting relationship between the trigger timing of the laser 400 and the synchronization timing of the energy integration of the beam stabilization unit 200 is: relative to the laser light emitting synchronization signal, the beam stabilization unit is synchronously triggered to perform energy integration, and the beam stabilization unit is triggered to reset the energy integration at an interval of 100us, and the time errors of the synchronous triggering and the interval triggering relative to the laser light emitting synchronization signal are both less than 40ns.

[0068] Furthermore, when the DSP core 502 is powered on, the interval trigger time 100 us is written into the FPGA controller 503 by writing to the memory via the high-speed bus.

[0069] The timing control diagram of the lithography machine exposure dose control system of the present application controls the beam stabilization unit 200 to perform corresponding beam position stabilization control is shown in FIG. Figure 5 As shown, the specific control process includes the following:

[0070] 1. The DSP core initializes the variable attenuator and sets the VA transmittance value;

[0071] 2. The DSP core sets and verifies the position of the beam stabilization unit motor;

[0072] 3. FPGA controller controls the light output of the excimer laser;

[0073] 4. Set the beam position

[0074] a. FPGA controller captures the laser light synchronization signal;

[0075] b. Relative to the laser light synchronization signal, the FPGA controller synchronously triggers the beam stabilization unit to perform energy integration with an error of less than 40ns;

[0076] c. Relative to the laser light synchronization signal, the FPGA controller triggers the beam stabilization unit to reset the integral every 100us, with an error of less than 40ns;

[0077] Repeat steps a, b, and c above 100 times.

[0078] 5. Based on the feedback from the beam stabilization unit, the DSP core determines whether the beam position setting is successful;

[0079] 6. The FPGA controller stops the laser from emitting light.

[0080] Furthermore, in the lithography machine dose control system provided herein, the DSP core is also configured to self-calibrate the transmittance of the variable attenuator during the laser's emission cycle. Preferably, during this self-calibration of the variable attenuator's transmittance, the DSP core automatically adjusts the rate of change of the motor position in the variable attenuator using an expert PID controller, so that the actual transmittance of the variable attenuator approaches the desired transmittance.

[0081] The present application implements an automatic calibration algorithm for the transmittance of a variable attenuator in a dose control system, which simplifies the tedious calibration process and can automatically find and record the motor position at the corresponding transmittance value.

[0082] Specifically, the self-calibration algorithm will start searching from the input starting position. First, the energy value collected by the EDU is obtained when the laser is fully transmitted. Then, the motor position is set to the theoretically calculated position, and the energy value collected by the EDU is obtained. The actual transmittance at the current motor position is calculated and compared with the expected value. If the error is within the expected value, the motor position value corresponding to the transmittance at this time is recorded; if the error is outside the expected value, the system will automatically adjust the rate of change of the motor position value through the expert PID according to the size of the error to quickly approach the actual transmittance value, and finally record the motor position value and transmittance at this time after the system actually meets the error. Through the self-calibration algorithm, the original complete calibration time is reduced to a few minutes now, which greatly improves efficiency, and the calibration position value is more accurate than the original interpolation method.

[0083] This application adopts a multi-core heterogeneous controller (DSP core and ARM core) + FPGA architecture to replace the original (DSP and FPGA) + VME chassis + (MCU and FPGA) architecture to achieve the purpose of simplifying the system link and the complexity of software and hardware, improve the real-time performance of the control system, and enable the control system to realize complex functions, such as the variable attenuator transmittance self-calibration function.

[0084] The above examples are used to illustrate the present invention, which are only used to help understand the present invention and are not intended to limit the present invention. Those skilled in the art can make several simple deductions, modifications or substitutions based on the concept of the present invention.

Claims

1. A photolithography machine exposure dose control system, characterized in that: include: Variable attenuator, beam stabilization unit, energy harvesting unit, laser, control device and host computer; The control device includes a multi-core heterogeneous controller and an FPGA controller, the multi-core heterogeneous controller includes an ARM core and a DSP core, and the ARM core, DSP core and FPGA controller are integrated on a DCB board; The ARM core is used to perform application logic control on the variable attenuator, beam stabilization unit, energy harvesting unit and laser; The DSP core is used to drive and control the variable attenuator, beam stabilization unit, energy collection unit and laser; The FPGA controller is used to perform parallel control and multi-channel AD high-speed acquisition on the variable attenuator, beam stabilization unit, energy collection unit and laser; The host computer is used to send function commands related to exposure dose control to the ARM core; The ARM core performs network communication with the host computer, receives and parses the functional commands issued by the host computer, and performs real-time inter-core communication with the DSP core to send the parsed commands and parameters to the DSP core. The DSP core performs real-time data interaction with the FPGA controller through a high-speed bus to send the received commands and parameters to the FPGA controller. The FPGA controller controls the corresponding variable attenuator, beam stabilization unit, energy collection unit, and laser to perform corresponding functional operations according to the received commands and parameters.

2. The exposure dose control system of a lithography machine according to claim 1, wherein: The laser's light emission period is 250 μs, and a limited relationship exists between the laser's triggering timing and the synchronization timing of the energy collection unit and the synchronization timing of the beam stabilization unit for energy integration. The limited relationship enables the DSP core and FPGA controller to complete the adjustment of the variable attenuator transmittance, the beam stabilization control of the beam stabilization unit, the beam energy collection of the energy collection unit, and the control of the laser's light emission within the laser's light emission period.

3. The exposure dose control system of a lithography machine according to claim 2, wherein: The limiting relationship between the trigger timing of the laser and the synchronization timing of the energy harvesting unit is: relative to the laser light synchronization signal, the energy harvesting unit is triggered with a delay of 3.9us, and the time error of the delayed trigger relative to the laser light synchronization signal is less than 40ns.

4. The exposure dose control system of a lithography machine according to claim 3, wherein: When the DSP core is powered on, the delayed trigger time 3.9 μs is written into the FPGA controller by writing to the memory via a high-speed bus.

5. The exposure dose control system of a lithography machine according to claim 3, wherein: The energy collection unit includes an EDU and an ESS, and the synchronization error time between the EDU and the ESS is less than 20ns.

6. The exposure dose control system of a lithography machine according to claim 2, wherein: The limiting relationship between the trigger timing of the laser and the synchronization timing of the energy integration of the beam stabilization unit is: relative to the laser light emitting synchronization signal, the beam stabilization unit is synchronously triggered to perform energy integration, and the beam stabilization unit is triggered to reset the energy integration at an interval of 100us, and the time errors of the synchronous triggering and the interval triggering relative to the laser light emitting synchronization signal are both less than 40ns.

7. The exposure dose control system of a lithography machine according to claim 6, wherein: When the DSP core is powered on, the interval trigger time 100 us is written into the FPGA controller by writing to the memory via the high-speed bus.

8. The exposure dose control system of a lithography machine according to claim 5, wherein: During the laser's light emission period, the DSP core is also used to self-calibrate the transmittance of the variable attenuator.

9. The exposure dose control system of a lithography machine according to claim 8, characterized in that: During the self-calibration of the transmittance of the variable attenuator by the DSP core, the expert PID is used to automatically adjust the rate of change of the motor position in the variable attenuator so that the actual transmittance of the variable attenuator approaches the expected transmittance.

Images