A method for improving completeness of a chip verification test plan

Abstract

The application discloses a method for improving the completeness of a chip verification test plan, which comprises the following steps: firstly, unified rules are specified for the whole project, and unified keywords are used in chip architecture documents and chip design documents to identify points that need to be verified and specially paid attention to; then, for self-research design modules IP, the above-mentioned unified keywords are used by designers in the process of writing design documents to explicitly list places that need to be verified by use cases in the documents; then, for third-party IP, the keywords that are generally paid attention to are different for each IP. The application automatically analyzes and searches keywords in all input documents such as design architecture documents and detailed design documents, extracts corresponding table documents, and then verifies whether it is necessary to increase the verification plan by piece-by-piece analysis and confirmation, so as to improve and enhance the completeness of the verification plan, and further increase the success probability of the chip.

Description

Technical Field

[0001] This invention relates to the field of improving the completeness of chip verification test plans, specifically a method for improving the completeness of chip verification test plans. Background Technology

[0002] As chip manufacturing processes shrink and chip sizes increase, chip functions become more complex, chip development cycles become longer and costs increase, thus demanding higher chip quality. Verification plays a crucial role in chip design to ensure the quality of the chip design.

[0003] The chip verification process includes several sub-tasks, such as verification plan writing, verification environment development, test case development, coverage analysis, and gate-level post-simulation. The verification plan plays a guiding role in these aspects. However, in current chip project practices, most verification plans are extracted and written by verification personnel based on the input chip architecture and design documents. Due to the length of the design documents and the differences in the level of verification personnel, some key test points are easily overlooked. Summary of the Invention

[0004] The purpose of this invention is to provide a method for improving the completeness of chip verification test plans. This invention automatically analyzes and searches for keywords in all input documents, such as design architecture documents and detailed design documents, and extracts them into corresponding table documents. Then, verification personnel analyze and confirm each keyword to determine whether it needs to be added to the verification plan, thereby improving and enhancing the completeness of the verification plan and increasing the probability of chip success.

[0005] The objective of this invention can be achieved through the following technical solutions:

[0006] A method for improving the completeness of chip verification test plans, comprising the following steps:

[0007] Step 1: Define a consistent set of rules for the entire project, using consistent keywords in the chip architecture and chip design documents to identify points of special interest that require verification.

[0008] Step two: For self-developed design module IP, designers use the above-mentioned unified keywords to clearly list the areas that need to be verified by test cases in the design document.

[0009] Step 3: For third-party IPs, the keywords that are generally of interest are different for each IP.

[0010] Step four: After the verification personnel have extracted the verification plan in the traditional way, they use the program to analyze and search the chip architecture document and chip design document to extract the complete key information, and then output it to a spreadsheet document.

[0011] Step 5: Verification personnel review the spreadsheet from Step 4 to further confirm whether these verification test points are included in the verification plan. The principle of confirmation is to ensure the completeness of the verification to the greatest extent possible and to avoid omissions.

[0012] As a further aspect of the present invention: In step one, the verification of points of special concern specifically refers to the explanation of keywords for different levels of needs in the Internet Engineering Task Force (IETF) Draft for Comments RFC 2119.

[0013] As a further aspect of the present invention: in step four, the key information includes the page number of the specific source document, the document content, and priority-related information.

[0014] As a further aspect of the present invention: in step five, if the verification plan does not include this verification test point, then it is added to the verification plan; if the verification plan already includes this verification test point, then the next step is analyzed.

[0015] As a further aspect of the present invention: in step one, the chip design document includes the following steps:

[0016] Step 1: After the design documents are written according to the unified rules, they are converted into PDF format documents. These rules are divided into different priorities, such as high priority, medium priority and low priority. The specific priority division is based on the importance of different design features and the requirements of project nodes.

[0017] Step 2: For the design documents, you can refer to RFC2119 for processing;

[0018] Step 3: Develop software to batch analyze and search the converted PDF documents, and save them as comma-separated value format documents; use the keywords preset in Step 1 for searching.

[0019] Step 4: Verification personnel review the results from Step 3 and perform further analysis.

[0020] As a further aspect of the present invention: in step 3, the step of writing software for batch analysis and search includes:

[0021] Step 3.1: Use software to search for high-priority keywords in the design document, extract the complete sentences containing them, and then save them as a CSV file.

[0022] Step 3.2: The software iterates through the search for high-priority, low-priority keywords and other specially marked keywords, and saves the complete sentence containing the keywords as a CSV file.

[0023] Step 3.3: After collecting the complete CSV file information, convert the CSV into a table in the same format as the verification plan form required internally by the project and save it.

[0024] As a further solution of the present invention: In the said Step 1, the specific processing method of the keywords:

[0025] Step 2.1: The statement descriptions where the keywords "MUST", "REQUIRED", "SHALL", and "必须" are located indicate the absolute necessary conditions for the design module IP. The verification plan must include and cover these items, with the corresponding priority being high priority, and it is verified that the function point indeed exists and is correct during verification.

[0026] Step 2.2: The statement descriptions where the keywords "MUST NOT", "SHALL NOT", "必须不", and "禁止" are located indicate the absolute prohibited conditions for the design module IP. The verification plan must include and cover this item, with the corresponding priority being medium priority, and it is verified that the function point indeed does not exist during verification.

[0027] Step 2.3: The statement descriptions where the keywords "SHOULD", "RECOMMENDED", "推荐", and "建议" are located indicate that they are acceptable in certain specific scenarios. The verification plan should also include and cover this item, and it is checked whether it meets the requirements of the project application scenario, with the corresponding priority being medium priority; similar processing is done for the keywords "SHOULD NOT", "NOT RECOMMENDED", "不推荐", and "建议不".

[0028] Step 2.4: The statement descriptions where the keywords "MAY", "OPTIONAL", and "可能" are located indicate that they are optional, with a low priority. This item is included in the verification plan and checked, and it is decided whether to cover it according to the actual requirements of the project in the actual verification work.

[0029] As a further solution of the present invention: In the said Step 1, the rules are divided into high priority, medium priority, and low priority, and the division of priorities is based on the importance of different design characteristics and the requirements of project nodes.

[0030] The beneficial effects of the present invention: The present invention automatically analyzes and searches for keywords in all input documents such as the design architecture document and the detailed design document, extracts them into corresponding table documents, and then the verification personnel analyze and confirm item by item whether they need to be added to the verification plan, thereby improving and enhancing the completeness of the verification plan, further increasing the chip success probability, providing a good supplementary method for the verification personnel to check the verification plan written by the verification personnel and find and fill in the gaps, and further improving the verification completeness. Brief Description of the Drawings

[0031] For the convenience of those skilled in the art to understand, the present invention will be further described below in conjunction with the accompanying drawings.

[0032] Figure 1 is the overall flowchart of the present invention; Specific embodiments

[0033] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work belong to the scope of protection of the present invention.

[0034] Embodiment 1

[0035] As Figure 1 shown, a method for improving the completeness of the chip verification test plan, the specific steps include:

[0036] Step 1, specify unified rules for the entire project, and use unified keywords in the chip architecture document and the chip design document to identify the points that require special attention in verification. Specifically, refer to the description of keywords at different requirement levels in the Internet Engineering Task Force (IETF) Request for Comments (RFC) 2119. The statements described by the keywords "MUST", "REQUIRED", "SHALL" and "must" indicate absolute necessary conditions for the design module IP, and the priority is high; the statements described by the keywords "MUST NOT", "SHALL NOT", "must not" and "prohibited" indicate absolute prohibited conditions for the design module IP, and the priority is medium; the statements described by the keywords "SHOULD", "RECOMMENDED", "recommended" and "suggested" indicate that they can be accepted in certain specific scenarios; similar processing is done for the keywords "SHOULD NOT", "NOT RECOMMENDED", "not recommended" and "suggested not"; the priority is medium; the statements described by the keywords "MAY", "OPTIONAL" and "may" indicate that they are optional, and the priority is low; for special places, additional special remarks can be made;

[0037] Step 2, for the self-developed design module IP, during the process of writing the design document, the designer uses the above unified keywords to clearly list the places that need to be covered by the verification cases in the document;

[0038] Step 3, for third-party IP, and each IP is different;

[0039] In Step 4, after the verifier extracts the verification plan in the traditional way, the verifier uses a program to analyze and search the above chip architecture documents and chip design documents, extracts complete key information, and then outputs it to a spreadsheet document, including the page numbers of the specific source documents, the document content, and the priority-related information;

[0040] In Step 5, the verifier further confirms whether these verification test points are included in the verification plan by reviewing the spreadsheet in Step 4. The principle of confirmation is to ensure the completeness of verification to the greatest extent without omission; if this verification test point is not included in the verification plan, it will be added to the verification plan; if this verification test point is already included in the verification plan, continue to analyze the next one.

[0041] Example 2

[0042] Step 1: After the design document is written according to unified rules, it is uniformly converted into a PDF format document; these rules have different priorities, such as high priority, medium priority, and low priority. The specific priority division is based on the importance of different design characteristics and the requirements of project nodes;

[0043] Step 2: For third-party design documents, since they do not fill in keywords according to our preset rules, RFC2119 can be referred to for processing; specific processing methods:

[0044] Step 2.1: The statement descriptions where the keywords "MUST", "REQUIRED", "SHALL", and "must" are located indicate the absolute necessary conditions for the design module IP. The items must be included and covered in the verification plan, with the corresponding priority being high priority, and it is verified that the function point actually exists and is correct during verification;

[0045] Step 2.2: The statement descriptions where the keywords "MUST NOT", "SHALL NOT", "must not", and "prohibit" are located indicate the absolute prohibited conditions for the design module IP. The items must be included and covered in the verification plan, with the corresponding priority being medium priority, and it is verified that the function point actually does not exist during verification;

[0046] Step 2.3: The statement descriptions where the keywords "SHOULD", "RECOMMENDED", "recommended", and "suggested" are located indicate that they are acceptable in certain specific scenarios. The items should also be included and covered in the verification plan, and it is checked whether they meet the requirements of the project application scenario, with the corresponding priority being medium priority; similar processing is done for the keywords "SHOULD NOT", "NOT RECOMMENDED", "not recommended", and "suggest not";

[0047] Step 2.4: The statements described with the keywords "MAY", "OPTIONAL", and "possible" indicate that they are optional and of low priority. Include this entry in the verification plan and review it, and decide whether it needs to be covered in the actual verification work according to the actual requirements of the project.

[0048] Step 3: Write software to batch analyze and search the converted PDF documents, and save them as comma-separated value format documents; the keywords used for searching are the keywords preset in Step 1.

[0049] Step 3.1: The software searches for high-priority keywords in the design document, extracts the complete statements where they are located, and then saves them as a CSV message.

[0050] Step 3.2: Similar to Step 3.1, the software loops to search for medium-priority, low-priority keywords, and keyword information with other special marks, and saves the complete statements where the keywords are located as a CSV message.

[0051] Step 3.3: After collecting the complete CSV file information, convert the CSV into a table in the same format as the verification plan form required internally by the project and save it.

[0052] Step 4: The verification personnel review the results in Step 3 and conduct further analysis.

[0053] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and utilize the present invention well. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A method for improving the completeness of chip verification test plans, characterized in that, The specific steps include: Step 1: Specify unified rules for the entire project, and use unified keywords in the chip architecture document and chip design document to identify points that require special attention in verification; Step 2: For the self-developed design module IP, during the process of writing the design document, the designer uses the above unified keywords to clearly list the places that need to be covered by verification cases in the document; Step 3: For third-party IP, and each IP is different; Step 4: After the verification personnel extract the verification plan in the traditional way, use a program to analyze and search the above chip architecture document and chip design document, extract the complete key information, and then output it to a spreadsheet document; Step 5: The verification personnel check the spreadsheet in Step 4 to confirm whether these verification test points are included in the verification plan. The principle of confirmation is to ensure the completeness of verification to the greatest extent without omission.

2. The method for improving the completeness of chip verification test plan according to claim 1, characterized in that, In Step 1, for the points that require special attention in verification, specifically refer to the description of keywords for different requirement levels in the Internet Engineering Task Force (IETF) Request for Comments (RFC) 2119.

3. The method for improving the completeness of chip verification test plan according to claim 1, characterized in that, In Step 4, the key information includes the page number of the specific source document, the document content, and the priority-related information.

4. The method for improving the completeness of chip verification test plan according to claim 1, characterized in that, In Step 5, if this verification test point is not included in the verification plan, it will be added to the verification plan; if this verification test point is already included in the verification plan, continue to analyze the next one.

5. The method for improving the completeness of chip verification test plan according to claim 1, characterized in that, In Step 1, the chip design document includes the following steps: Step 1: After the design document is written according to the unified rules, it is uniformly converted into a PDF format document; these rules are divided into high priority, medium priority, and low priority, and the priority is divided according to the importance of different design characteristics and the requirements of project nodes; Step 2: For the design document, refer to RFC 2119 for processing; Step 3: Write software to batch analyze and search the converted PDF document, and save it as a comma-separated value format document; the keywords used for searching are the keywords preset in Step 1; Step 4: The verification personnel check the results in Step 3 and conduct further analysis.

6. The method for improving the completeness of a chip verification test plan according to claim 5, characterized in that, In Step 3, the steps of writing software to batch analyze and search include: Step 3.1: The software searches for high-priority keywords in the design document, extracts the complete sentence where they are located, and then saves it as a CSV message; Step 3.2: The software loops to search for medium-priority, low-priority keywords, and keyword information with other special marks, and saves the complete sentence where the keyword is located as a CSV message; Step 3.3: After collecting the complete CSV file information, convert the CSV into a table in the same format as the verification plan form required within the project and save it.

7. The method for improving the completeness of a chip verification test plan according to claim 5, characterized in that, In Step 1, the specific processing method of the keywords: Step 2.1: The statements where the keywords "MUST", "REQUIRED", "SHALL", and "必须" are located indicate the absolute necessary conditions of the design module IP. The verification plan must include and cover these items, and the corresponding priority is high priority. And in the verification, the function of this function point actually exists and is correct; Step 2.2: The statements containing the keywords "MUST NOT", "SHALL NOT", "must not", and "prohibit" indicate absolute prohibited conditions for the design module IP. These entries must be included and covered in the verification plan, with a medium priority, and it must be verified during verification that this function point does not exist. Step 2.3: The statements containing the keywords "SHOULD", "RECOMMENDED", "recommended", and "suggested" indicate that they are acceptable under certain specific scenarios. These entries are included and covered in the verification plan, and it is checked whether they meet the requirements of the project application scenarios, with a medium priority. The same applies to the keywords "SHOULD NOT", "NOT RECOMMENDED", "not recommended", and "suggest not". Step 2.4: The statements containing the keywords "MAY", "OPTIONAL", and "may" indicate that they are optional, with a low priority. These entries are included in the verification plan and checked, and it is decided whether to cover them according to the actual requirements of the project during actual verification work.

8. The method for improving the completeness of a chip verification test plan according to claim 5, characterized in that, The priority划分 in Step 1 is based on the importance of different design characteristics and the requirements of project nodes.

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