Method of fabricating fully surrounded gate device
By embedding cavities within a semiconductor substrate on an insulator, and combining dummy gate and post-gate processes to form a fully enclosed gate structure, the problems of complex fabrication processes and low etching precision in existing technologies are solved, achieving simplified processes and improved performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
- Filing Date
- 2023-03-31
- Publication Date
- 2026-05-15
AI Technical Summary
The existing technology for fully enclosed gate transistors has a complex fabrication process, many control points, and difficulty in improving the etching precision of floating channels, and is incompatible with advanced process nodes.
Using a semiconductor-on-insulator substrate with an embedded cavity, a fully enclosed gate structure is formed through a dummy gate structure and a post-gate process, including dummy gate deposition, etching, and self-aligned formation of source and drain regions. Combined with dry etching and chemical vapor deposition processes, a fully enclosed gate device is formed.
It simplifies the fabrication process, reduces costs, improves process stability and electrical performance, achieves compatibility with conventional CMOS processes, and expands the range of gate electrode materials that can be selected.
Smart Images
Figure CN116110795B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit design and manufacturing; in particular, it relates to a method for fabricating a complementary field-effect transistor. Background Technology
[0002] As microelectronic devices continue to shrink, existing FinFET technology is expected to face significant technical bottlenecks at the 5nm and 3nm nodes, where device performance will no longer see substantial improvements with further reductions in device size. This necessitates the introduction of new device structures to enhance performance while mitigating the short-channel effects resulting from size reduction.
[0003] Nanowire / nanosheet gate-around transistors (GOTOTs) are considered one of the most promising next-generation devices to replace FinFETs and achieve mass production below the 3nm technology node. The nanowire / nanosheet GOTOT structure, with its four-sided enclosure, allows for channel control from all four sides, fundamentally enhancing channel control capabilities. Currently, horizontal GOTOTs have various fabrication schemes. A common fabrication process involves etching a suspended nanowire structure onto an SOI substrate, thinning the nanowire structure, and then sequentially depositing a gate dielectric layer and a gate electrode layer to form the corresponding GOTOT transistor structure. However, this process struggles to precisely control the overlap capacitance between the sidewalls and gate electrode and the source / drain regions and their extensions. Furthermore, as the gate size continues to decrease, the difficulty of controlling the patterned gate increases significantly, and it is incompatible with the processes used in advanced process nodes. On the other hand, it limits the types of gate materials and the range of processes that can be selected.
[0004] Therefore, simplifying and improving the fabrication process of fully enclosed gate devices is one of the urgent problems to be solved. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for fabricating a fully enclosed gate device, which solves the problems of complex fabrication process, numerous control points, and difficulty in improving the etching accuracy of floating channels in the prior art.
[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating a fully enclosed gate device, the method comprising:
[0007] A semiconductor-on-insulator substrate with an embedded cavity is provided, the semiconductor-on-insulator substrate comprising a top semiconductor layer, an insulating layer and a back substrate, wherein the cavity is disposed in the insulating layer or between any two adjacent of the top semiconductor layer, the insulating layer and the back substrate;
[0008] A dummy gate structure is formed on the top semiconductor layer above the cavity. The dummy gate structure overlaps with the cavity in the vertical projection direction. The dummy gate structure has an extension direction consistent with the cavity and extends beyond the cavity along the extension direction.
[0009] The source and drain regions are formed based on the aforementioned pseudo-gate structure;
[0010] A channel mask pattern is defined above the dummy gate structure, and a suspended channel is formed based on the channel mask pattern;
[0011] The dummy gate structure is removed to expose the dummy gate trench, and a fully enclosed gate structure is formed based on the dummy gate trench and the embedded cavity;
[0012] A source electrode and a drain electrode are formed in the source region and the drain region, respectively.
[0013] Optionally, the preparation method further includes performing a pre-doping process on the top semiconductor layer of the semiconductor-on-insulator substrate.
[0014] Optionally, the preparation method further includes:
[0015] A stacked dummy gate dielectric layer and a sacrificial dummy gate are formed on the top semiconductor layer;
[0016] An isolation sidewall is formed on the outer side of the sacrificial dummy gate, wherein the material of the isolation sidewall includes SiO. x SiN x SiN x O y One of them.
[0017] Optionally, before or after the step of forming the isolation sidewall, a source / drain extension region is formed in the channel region of the top semiconductor layer.
[0018] Optionally, the preparation method further includes:
[0019] A hard mask layer is formed by covering the dummy gate structure;
[0020] A channel mask pattern is defined by photolithography on the surface of the hard mask layer. Using the channel mask pattern as a mask, the hard mask layer, the dummy gate structure, and the top semiconductor layer are sequentially patterned to form the dummy gate structure and a floating channel.
[0021] Optionally, the preparation method further includes: after forming the suspended channel, forming a protective layer by chemical vapor deposition, atomic layer deposition, or thermal oxidation, wherein the protective layer surrounds the patterned dummy gate structure and the suspended channel.
[0022] Optionally, the sacrificial dummy gate is removed by a wet etching process or an isotropic dry etching process, while the protective layer and the dummy gate dielectric layer covering the surface of the suspended channel are also removed, and the isolation sidewalls are retained on both sides of the dummy gate channel.
[0023] Optionally, the fully enclosed gate structure includes a gate electrode layer and a gate dielectric layer between the gate electrode layer and the suspended channel, wherein the material of the gate electrode layer includes one or more of polysilicon, Ti, Cu, Al, W, Ni, Cr, Ta, Mo, TiN, and TaN.
[0024] The present invention also provides a fully enclosed gate CMOS structure, wherein the fully enclosed gate CMOS structure is fabricated according to the aforementioned fully enclosed gate device fabrication method.
[0025] As described above, the method for fabricating the fully enclosed gate device of the present invention has the following beneficial effects:
[0026] 1) The fabrication method of the fully enclosed gate device of the present invention uses a semiconductor-on-insulator substrate with an embedded cavity, wherein the cavity is at least disposed in the insulating layer, and suspended semiconductor nanowires can be directly fabricated by dry etching based on the semiconductor-on-insulator substrate with the embedded cavity, thereby fabricating a horizontal ring gate transistor.
[0027] 2) This invention first performs a dummy gate process, which reduces the difficulty of dummy gate deposition and etching, thereby reducing the process complexity of fabricating ring gate transistors and effectively reducing the manufacturing cost of devices. Then, a floating channel is formed, and self-aligned source and drain regions are formed based on the dummy gate structure, which can effectively improve process stability and injection accuracy, and significantly improve the electrical performance of the all-around gate device.
[0028] 3) This invention employs a post-gate process, which, after activation annealing of the source and drain regions and repair annealing of the suspended channel, forms a fully enclosed gate structure within the dummy gate trench. This results in a fully enclosed gate structure with a lower thermal budget, thereby allowing for a wider range of gate electrode materials to meet different device performance requirements and ensuring good compatibility with conventional CMOS processes. Attached Figure Description
[0029] Figure 1 The diagram shows a process flow chart of the fabrication method of the fully enclosed gate device of the present invention.
[0030] Figures 2 to 28 This is a schematic diagram of the structure of each stage of the fabrication method of the fully enclosed gate device according to the present invention.
[0031] Figures 29a to 29j The diagram shown is an exemplary cross-sectional view of a semiconductor-on-insulator substrate with an embedded cavity, as described in an embodiment of the present invention.
[0032] Component designation explanation
[0033] 10 Semiconductor-on-Insulator Substrate
[0034] 110 Backing
[0035] 120 insulation layer
[0036] 122 Cavity
[0037] 130 top semiconductor layer
[0038] 132 Suspended Trench
[0039] 134 False gate trench
[0040] 140 hard mask layers
[0041] 142 Channel mask pattern
[0042] 20. Pseudo-gate structure
[0043] 202 Dummy gate dielectric layer
[0044] 204 Sacrificial Fence
[0045] 210 Isolation sidewall
[0046] 212 Protective Layer
[0047] 30 Fully Enclosed Grid Structure
[0048] 310 Gate dielectric layer
[0049] 320 gate electrode layer
[0050] 410 Metal silicides
[0051] Steps S1 to S8 Detailed Implementation
[0052] The embodiments of the present invention will then be illustrated through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. For clarity, components and steps well known to those skilled in the art have been omitted to avoid unnecessarily obscuring the elements of the present invention.
[0053] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.
[0054] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0055] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0056] See Figure 1 This invention provides a method for fabricating a fully enclosed gate device, which will be discussed later in conjunction with... Figures 2 to 28 The method for fabricating the fully enclosed gate device of the present invention will be described in detail below.
[0057] This embodiment provides a method for fabricating a fully enclosed gate device, including:
[0058] First, see Figures 2-4 In step 1), a semiconductor-on-insulator substrate 10 with an embedded cavity is provided. The semiconductor-on-insulator substrate 10 includes a back substrate 110, an insulating layer 120 and a top semiconductor layer 130. The cavity 122 is disposed in the insulating layer 120 or between any two adjacent of the top semiconductor layer 130, the insulating layer 120 and the back substrate 110.
[0059] Specifically, the back substrate 110 can be a semiconductor material or an insulating material, the insulating layer 120 can be a silicon dioxide layer or a similar insulating dielectric material, and the material of the top semiconductor layer 260 can be one of silicon, germanium, silicon-germanium, gallium nitride, aluminum nitride, gallium arsenide, silicon carbide, zinc oxide, gallium oxide, and indium phosphide. In this embodiment, the semiconductor-on-insulator substrate 10 is selected as a silicon-on-insulator substrate, the insulating layer 120 is selected as silicon dioxide, and the top semiconductor layer 130 is selected as lightly doped silicon of a first conductivity type.
[0060] For example, the cavity 122 may be located in the insulating layer 120 and may be configured to penetrate or not penetrate the insulating layer 120, or it may be partially disposed in the insulating layer 120 and extend to the top semiconductor layer 130 or the back substrate 110. Figures 29a to 29j The diagram shows an exemplary cross-sectional view of a semiconductor-on-insulator substrate with an embedded cavity, as shown in an embodiment of the present invention. In this embodiment, as... Figure 2 As shown, the dashed box indicates the opening position of cavity 122, combined with... Figures 3-4 The diagram shows the structure of the semiconductor-on-insulator substrate along cross sections A-A' and B-B'. The cavity 122 is embedded in the insulating layer adjacent to the top semiconductor layer. The top semiconductor layer 260, the intermediate semiconductor layer 230, and the inner wall of the insulating layer together form the cavity 122.
[0061] It should be noted that although the description uses the opening position and geometry of the cavity shown in the figure as an example, the position of the cavity can be flexibly adjusted according to the needs of the fabrication process.
[0062] In one specific embodiment, the formation process of the silicon-on-insulator substrate with the embedded cavity can be referred to relevant technical literature (e.g., Qiang Liu, Zhiqiang Mu, Chenhe Liu, Lantian Zhao, etc., “Gate-All-Around MOSFET Built on Void Embedded Silicon on Insulator Substrate”, IEEE Electron Device Letters, 2021, 42(5):657-660, and Lantian Zhao, Qiang Liu, Chenhe Liu, etc., “Total Ionizing Dose Effects on Nanosheet Gate-All-Around MOSFETs Built on Void Embedded Silicon on Insulator Substrate”, IEEE Electron Device Letters, 2021, 42(10):1428-1431), which will not be elaborated here.
[0063] like Figures 2-4 As shown, step S1 further includes performing a pre-doping process on the top semiconductor layer 130 to adjust the threshold voltage of the device.
[0064] Then, see Figures 5-7In step 2), a dummy gate structure 20 is formed on the top semiconductor layer 130. The dummy gate structure 20 overlaps with the cavity 122 in the vertical projection direction. The dummy gate structure 20 has an extension direction consistent with the cavity 122 and extends beyond the cavity along the extension direction.
[0065] like Figures 5-7 As shown, step 2) includes: 2-1) sequentially forming a dummy gate dielectric material layer and a sacrificial dummy gate material layer on the top semiconductor layer 130; 2-2) etching based on the dummy gate mask pattern to form a stacked dummy gate dielectric layer 202 and a sacrificial dummy gate 204, wherein the dummy gate mask pattern can be formed on top of the sacrificial dummy gate material layer using known photoresist spin coating, exposure, and development processes; 2-3) forming isolation sidewalls 210 on the outer sides of the dummy gate dielectric layer 202 and the sacrificial dummy gate 204. In a specific embodiment, the sacrificial dummy gate 204 may be a polysilicon dummy gate, and the dummy gate dielectric layer 202 may be SiO2. x SiN x and SiN x O y One of them.
[0066] Furthermore, in steps 2-3), before or after forming the isolation sidewall 210 on the outside of the dummy gate structure, shallow doping is performed in the defined channel region to form the source / drain expansion region.
[0067] Then, see Figures 8-10 Step 3) is performed to form a self-aligned source region and drain region based on the dummy gate structure 20.
[0068] like Figures 8-10 As shown, step 3) includes: performing self-aligned implantation using the dummy gate structure as a mask to form source and drain regions; subsequently, performing activation annealing, wherein the activation annealing can be performed using a rapid thermal annealing (RTA) process. Alternatively, in other embodiments, the source and drain regions are formed on the top semiconductor layer 130 by an epitaxial process. In this case, source and drain regions for improving device performance are formed on both sides of the dummy gate structure. The material of the source and drain regions can be the same as the material of the top semiconductor layer, for example, both being Si, or they can be different materials, such as one or a combination of SiGe, Si:C, Si:H, SiSn, GeSn, and SiGe:C with higher stress.
[0069] In one specific embodiment, after the source region and the drain region are formed, a hard mask layer 140 is formed over the dummy gate structure 20 and the insulating substrate.
[0070] Furthermore, the hard mask layer 140 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar deposition processes, or by thermal oxidation. The hard mask layer 140 can be an insulating dielectric layer commonly used in the art, such as SiN. x or SiN x O y A chemical mechanical polishing (CMP) process is performed on the hard mask layer 140 to obtain a flat top surface.
[0071] Then, see Figures 11-19 In step 4), a channel mask pattern 142 is defined by photolithography above the dummy gate structure 20, and a suspended channel 132 is formed based on the channel mask pattern 142.
[0072] like Figures 11-16 As shown, step 4) includes: 4-1) defining a channel mask pattern 142 in the photoresist layer above the hard mask layer 140; 4-2) using an isotropic etching process with the channel mask pattern 142 as a mask, sequentially etching the sacrificial dummy gate 204, the dummy gate dielectric layer 202, and the top semiconductor layer 130 to form the suspended channel 132. Alternatively, in other embodiments, the dummy gate structure 20 can be etched using an isotropic etching process with the channel mask pattern 142 as a mask; subsequently, the top semiconductor layer 130 can be etched using the patterned dummy gate structure 20 as a mask, thereby forming the suspended channel 132. Due to the introduction of hard mask technology, the suspended channel is formed by etching based on the pattern defined in the hard mask layer, which significantly reduces the line roughness of the nanowires and makes the process more stable.
[0073] It should be noted that this embodiment is described using the number, geometry and spacing of the suspended channels shown in the figure as an example, but it does not mean that the arrangement of the suspended channels of the present invention is limited to this. Moreover, it is conceivable that those skilled in the art can appropriately adjust, for example, the type and parameters of the etchant in the etching process to obtain the desired structure according to actual needs.
[0074] Furthermore, such as Figures 17-19 As shown, step 4) includes: after forming the suspended channel 132 in step 4-2), step 4-3) is performed to form a protective layer 212 by chemical vapor deposition, atomic layer deposition, or thermal oxidation. The protective layer 212 surrounds the patterned dummy gate structure 20 and the suspended channel 132 to protect the suspended channel 132.
[0075] Then, see Figures 20-25 Step 5) is performed to remove the dummy gate structure 20 to expose the dummy gate groove 134, and to form a fully enclosed gate structure 30 based on the dummy gate groove 134 and the embedded cavity 122.
[0076] like Figures 20-22 As shown, a fully enclosed gate structure 30 is formed around the suspended channel 132. Step 5) includes: 5-1) removing the sacrificial dummy gate 204 by a wet etching process or an isotropic dry etching process, while simultaneously removing the protective layer and the dummy gate dielectric layer covering the surface of the suspended channel, so that the isolation sidewall 210 is not laterally etched but remains on both sides of the dummy gate channel. Thus, the isolation sidewall is subsequently provided on the outside of the gate structure formed in the dummy gate channel, which can effectively reduce the parasitic capacitance between the gate and the source / drain regions. The wet etching process can be performed using an etchant with a high etch selectivity relative to the material of the isolation sidewall, such as HF solvent; or, by an isotropic dry etchant. Commonly used etching gases in the art are employed, including but not limited to: oxidizing gases and one or a combination of CF4, CH3F, CHF3, CH2F2, C4F8, and C4F6.
[0077] Further, step 5) also includes: 5-2) forming a fully enclosed gate structure 30 based on the dummy gate trench 134 and the embedded cavity 122; 5-3) pre-treating the structure obtained in step 5-2). The pre-treatment steps include: performing a surface cleaning process; performing an annealing pre-treatment process under O2, HCl, H2, NH3 or similar atmospheres to repair surface and internal defects of the suspended channel, for example, performing the annealing pre-treatment process at a temperature of 500℃~1200℃ for an annealing time of 10s~1h.
[0078] like Figures 23-25 As shown, the step of forming a fully enclosed gate structure 30 surrounding the suspended channel 132 includes: 5-3) forming a gate dielectric layer 310 surrounding the suspended channel 132 using metal oxide chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or physical vapor deposition (PVD); and 5-4) filling the dummy gate trench 134 with a gate electrode material, wherein the gate dielectric layer 310 is located between the gate electrode layer 320 and the suspended channel 132. In this embodiment, the gate dielectric layer 310 is selected as a high-k material, such as a material with a dielectric constant greater than 6.0, including but not limited to hafnium-based materials selected from HfO2, HfSiOx, HfSiON, HfAlOx, HfTaOx, HfLaOx, HfAlSiOx, and HfLaSiOx. Correspondingly, the gate electrode layer 320 includes one or more of Ti, Cu, Al, W, Ni, Cr, Ta, Mo, TiN, and TaN. In other examples, the gate dielectric layer 310 may be made of SiO2. x SiN x SiN x O yIn one of these cases, the gate electrode layer 320 may be selected as a polycrystalline silicon electrode.
[0079] In this embodiment, the gate dielectric layer 310 can be a high-k dielectric layer, and the gate electrode layer 320 can be a metal gate electrode, which can be formed by chemical vapor deposition (CVD) or physical vapor deposition. Since the source / drain regions are formed based on the dummy gate structure, the dummy gate structure is removed to expose the dummy gate trench 134. The dummy gate trench 134 and the cavity 122 are filled to form a fully enclosed gate structure 30. A high-k metal gate (HKMG) is formed through a post-gate process. The high-k metal gate is exempt from activation annealing of the source / drain regions and repair annealing of the channel regions, reducing the need for post-deposition heat treatment of the high-k metal gate and lowering the thermal budget of the HKMG. Therefore, the impact of heat treatment on the HKMG structure is reduced, for example, the impact of heat treatment on work function drift is reduced.
[0080] Furthermore, the metal gate electrode includes a work function metal layer. For example, for a PMOS device, the work function metal layer is TiN, and for an NMOS device, it is AlTi. The work function of the metal gate electrode can be flexibly adjusted according to the threshold voltage of the device.
[0081] Then, see Figures 23-28 Step 6) is performed to form a source electrode 40 and a drain electrode 50 in the source region and the drain region, respectively.
[0082] like Figures 23-25 Step 6) includes: 6-1) removing the passivation layer located above the source region and the drain region, and forming metal silicide 410 in the source region and the drain region respectively using a self-aligned process; 6-2) forming an interlayer dielectric layer (not shown) above the source region and the drain region, and forming contact vias on the interlayer dielectric layer.
[0083] Furthermore, a passivation layer is formed using a high-density plasma chemical vapor deposition (HDP-CVD) process, wherein the material of the passivation layer may be SiN. x .
[0084] like Figures 26-28 As shown, after step 6-2), step 6-3) is performed to form the source electrode 40 and the drain electrode 50, including: forming an electrode metal layer over the interlayer dielectric layer, the electrode metal layer filling the contact via to achieve the lead-out of the contact electrode.
[0085] This embodiment also provides a CMOS process-compatible fully enclosed gate device, which is preferably fabricated using the aforementioned fully enclosed gate device fabrication method.
[0086] In summary, the fabrication method of the fully enclosed gate device of the present invention has the following beneficial effects:
[0087] 1) The fabrication method of the fully enclosed gate device of the present invention uses a semiconductor-on-insulator substrate with an embedded cavity, wherein the cavity is at least disposed in the insulating layer, and suspended semiconductor nanowires can be directly fabricated by dry etching based on the semiconductor-on-insulator substrate with the embedded cavity, thereby fabricating a horizontal ring gate transistor.
[0088] 2) This invention first performs a dummy gate process, which reduces the difficulty of dummy gate deposition and etching, thereby reducing the process complexity of fabricating ring gate transistors and effectively reducing the manufacturing cost of devices. Then, a floating channel is formed, and self-aligned source and drain regions are formed based on the dummy gate structure, which can effectively improve process stability and injection accuracy, and significantly improve the electrical performance of the all-around gate device.
[0089] 3) This invention employs a post-gate process, forming a fully enclosed gate structure after activation annealing of the source and drain regions and repair annealing of the suspended channel. This results in a lower thermal budget for the obtained fully enclosed gate structure, allowing for a wider range of gate electrode materials to meet different device performance requirements, and ensuring good compatibility with conventional CMOS processes. Furthermore, the use of HKMG technology, which performs device thermal processing before HKMG deposition, reduces the need for post-HKMG thermal processing, thus lowering the thermal budget after the HKMG process. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.
[0090] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating a fully enclosed gate device, characterized in that, The preparation method includes: A semiconductor-on-insulator substrate with an embedded cavity is provided, the semiconductor-on-insulator substrate comprising a top semiconductor layer, an insulating layer and a back substrate, wherein the cavity is disposed in the insulating layer or between any two adjacent of the top semiconductor layer, the insulating layer and the back substrate; A dummy gate structure is formed on the top semiconductor layer above the cavity. The dummy gate structure overlaps with the cavity in the vertical projection direction. The dummy gate structure has an extension direction consistent with the cavity and extends beyond the cavity along the extension direction. Self-aligned source and drain regions are formed based on the aforementioned dummy gate structure; A channel mask pattern is defined above the dummy gate structure, and a suspended channel is formed based on the channel mask pattern; The dummy gate structure is removed to expose the dummy gate trench, and a fully enclosed gate structure is formed by surrounding the suspended channel based on the dummy gate trench and the embedded cavity; A source electrode and a drain electrode are formed in the source region and the drain region, respectively.
2. The method for fabricating a fully enclosed gate device according to claim 1, characterized in that, The preparation method further includes performing a pre-doping process on the top semiconductor layer of the semiconductor-on-insulator substrate.
3. The method for fabricating a fully enclosed gate device according to claim 1, characterized in that, The preparation method further includes: A stacked dummy gate dielectric layer and a sacrificial dummy gate are formed on the top semiconductor layer; An isolation sidewall is formed on the outside of the dummy gate structure, wherein the material of the isolation sidewall includes one of SiOx, SiNx, and SiNxOy.
4. The method for fabricating a fully enclosed gate device according to claim 3, characterized in that, The fabrication method further includes forming a source / drain extension region in the channel region of the top semiconductor layer before or after the step of forming the isolation sidewall.
5. The method for fabricating a fully enclosed gate device according to claim 3, characterized in that, The preparation method further includes: A hard mask layer is formed by covering the dummy gate structure; A channel mask pattern is defined by photolithography on the surface of the hard mask layer. Using the channel mask pattern as a mask, the hard mask layer, the dummy gate structure, and the top semiconductor layer are sequentially patterned to form the dummy gate structure and a floating channel.
6. The method for fabricating a fully enclosed gate device according to claim 5, characterized in that, The preparation method further includes: after forming the suspended channel, forming a protective layer by chemical vapor deposition, atomic layer deposition, or thermal oxidation, wherein the protective layer surrounds the patterned dummy gate structure and the suspended channel.
7. The method for fabricating a fully enclosed gate device according to claim 6, characterized in that, The preparation method further includes: removing the sacrificial dummy gate by a wet etching process or an isotropic dry etching process, while removing the protective layer and the dummy gate dielectric layer covering the surface of the suspended channel, while the isolation sidewalls are retained on both sides of the dummy gate channel.
8. The method for fabricating a fully enclosed gate device according to claim 7, characterized in that, The preparation method further includes: After removing the sacrificial dummy gate and the dummy gate dielectric layer, preprocessing is performed; The fully enclosed gate structure is formed within the dummy gate trench and the cavity.
9. The method for fabricating a fully enclosed gate device according to claim 8, characterized in that, The fully enclosed gate structure includes a gate electrode layer and a gate dielectric layer between the gate electrode layer and the suspended channel. The material of the gate electrode layer includes one or more of polysilicon, Ti, Cu, Al, W, Ni, Cr, Ta, Mo, TiN, and TaN.
10. A CMOS process-compatible fully enclosed gate device, characterized in that, The fully enclosed gate CMOS structure is fabricated according to the fabrication method of the fully enclosed gate device according to any one of claims 1 to 9.