Display panel and display device

Abstract

The present invention discloses a display panel and a display device. The display panel includes: a base substrate; at least one thin film transistor located on one side of the base substrate, the thin film transistor including an active layer, the active layer including a contact portion, a channel portion and a doping portion, the doping portion being located between the contact portion and the channel portion; a first metal layer located on the side of the thin film transistor away from the base substrate, the first metal layer including a first opening; the doping portion at least partially overlaps with the first opening in a direction perpendicular to the plane where the display panel is located. The doping portion can reduce the electric field in the area where the contact portion is located, thereby reducing the leakage current of the thin film transistor. The first opening is arranged to overlap with the doping portion in a direction perpendicular to the plane where the display panel is located, which can reduce the influence of the electric field of the first metal layer on the doping portion, improve the performance stability of the thin film transistor, and thereby improve the display performance of the display panel.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Display technology has permeated every aspect of our daily lives, and accordingly, an increasing number of materials and technologies are being used in display screens. Display panels, as a crucial component of display devices, are used to implement their display functions. Currently, display panels primarily include liquid crystal display (LCD) panels and organic light-emitting diode (OLED) panels.

[0003] In the prior art, thin film transistors (TFTs) are used as the main driving elements in LCD and OLED display panels. How to improve the stability of thin film transistors is an important research issue in the field of display technology. Summary of the Invention

[0004] In view of this, the present invention provides a display panel and a display device to enhance the stability of thin film transistors and improve display performance.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0006] substrate;

[0007] at least one thin film transistor located on one side of the substrate, the thin film transistor comprising an active layer, the active layer comprising a contact portion, a channel portion, and a doped portion, the doped portion being located between the contact portion and the channel portion;

[0008] The first metal layer is located on a side of the thin film transistor facing away from the base substrate, and the first metal layer includes a first opening; along a direction perpendicular to the plane where the display panel is located, the doped portion at least partially overlaps with the first opening.

[0009] In a second aspect, an embodiment of the present invention provides a display device, comprising the display panel according to the first aspect of the present invention.

[0010] In an embodiment of the present invention, a display panel includes a base substrate; at least one thin film transistor located on one side of the base substrate, the thin film transistor including an active layer, the active layer including a contact portion, a channel portion and a doping portion, the doping portion being located between the contact portion and the channel portion; a first metal layer located on a side of the thin film transistor facing away from the base substrate, the first metal layer including a first opening; the doping portion at least partially overlaps with the first opening in a direction perpendicular to the plane where the display panel is located. The doping portion can reduce the electric field in the area where the contact portion is located, thereby reducing the leakage current of the thin film transistor. Arranging the first opening to overlap with the doping portion in a direction perpendicular to the plane where the display panel is located can reduce the influence of the electric field of the first metal layer on the doping portion, prevent the electric field from affecting the threshold voltage and off-state voltage of the thin film transistor, and thus improve the performance stability of the thin film transistor, thereby improving the display performance of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of a top view of a display panel provided by an embodiment of the present invention;

[0012] Figure 2 for Figure 1 A schematic diagram of a partial cross-sectional structure of the display panel shown;

[0013] Figure 3 A schematic diagram of an IDVG curve of a thin film transistor provided by an embodiment of the present invention;

[0014] Figure 4 A schematic diagram of a partial cross-sectional structure of a display panel provided by an embodiment of the present invention;

[0015] Figure 5 A schematic diagram of a partial top view of a display panel provided by an embodiment of the present invention;

[0016] Figure 6 for Figure 5 Schematic diagram of the cross-section structure along the A-A' direction;

[0017] Figure 7 A schematic diagram of a partial top view of another display panel provided by an embodiment of the present invention;

[0018] Figure 8 for Figure 7 Schematic diagram of the cross-sectional structure along the B-B' direction;

[0019] Figure 9 A schematic diagram of a partial top view of another display panel provided by an embodiment of the present invention;

[0020] Figure 10 A schematic diagram of a partial cross-sectional structure of another display panel provided by an embodiment of the present invention;

[0021] Figure 11 A schematic diagram of a partial cross-sectional structure of another display panel provided by an embodiment of the present invention;

[0022] Figure 12 A schematic diagram of a partial cross-sectional structure of another display panel provided by an embodiment of the present invention;

[0023] Figure 13 A schematic diagram of a partial cross-sectional structure of another display panel provided by an embodiment of the present invention;

[0024] Figure 14 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0026] Based on the defects of the prior art mentioned in the background art, an embodiment of the present invention provides a display panel to enhance the performance stability of thin film transistors in the display panel, thereby improving the display performance of the display panel. Figure 1 A schematic diagram of a top view of a display panel provided by an embodiment of the present invention is shown. Figure 2 for Figure 1 The partial cross-sectional structure diagram of the display panel is shown in FIG. Figure 1 and Figure 2 As shown, the display panel includes: a base substrate 1; at least one thin film transistor 2, located on one side of the base substrate 1, the thin film transistor 2 includes an active layer 3, the active layer 3 includes a contact portion 4, a channel portion 5 and a doping portion 6, the doping portion 6 is located between the contact portion 4 and the channel portion 5; a first metal layer 7, located on the side of the thin film transistor 2 away from the base substrate 1, the first metal layer 7 includes a first opening 8; along a direction Z perpendicular to the plane of the display panel, the doping portion 6 and the first opening 8 at least partially overlap.

[0027] refer to Figure 1 and Figure 2 In the present application, the display panel includes a base substrate 1 and a thin film transistor 2 located on one surface of the base substrate 1. The base substrate 1 can be a rigid substrate, such as a glass substrate, or a flexible substrate, such as a polyimide substrate, but is not limited thereto. Other film layers, such as a buffer layer (not shown), may be disposed between the base substrate 1 and the film layer containing the thin film transistor 2. This embodiment of the present invention does not elaborate on or limit this aspect.

[0028] The display panel includes a display area AA and a non-display area NA surrounding the display area. A plurality of sub-pixel units 01 arranged in an array are provided in the display area AA. Each sub-pixel unit 01 includes a light-emitting structure (not shown) and a pixel driving circuit 02. The pixel driving circuit 02 is used to cause the light-emitting structure to emit light or drive the light-emitting structure to emit light. When the display panel is an LCD display panel, the light-emitting structure may include a stacked pixel electrode, liquid crystal molecules and a common electrode. The pixel driving circuit 02 may be electrically connected to the pixel electrode of the corresponding sub-pixel unit 01. The electric field formed between the pixel electrode and the common electrode causes the liquid crystal molecules in the sub-pixel unit 01 to deflect, so that the light emitted by the backlight source passes through the liquid crystal molecule layer to achieve normal display. When the display panel is an OLED display panel, the light-emitting structure may include a stacked anode, a light-emitting material and a cathode. The pixel driving circuit 02 may be electrically connected to the anode of the corresponding sub-pixel unit 01. The holes in the anode and the electrons in the cathode combine in the light-emitting material, and the light-emitting material emits light, thereby achieving normal display. In the embodiments of the present application, the display panel will be described as an OLED display panel as an example. For other types of display panels, adaptive adjustments can be made based on the technical solutions in this application.

[0029] At least one pixel drive control circuit 03 is provided in the non-display area NA of the display panel. The pixel drive control circuit 03 may include multiple shift register units (not shown) arranged in cascade. Each stage of the shift register unit is electrically connected to the pixel drive circuit 02 within the same row of sub-pixel units 01, and is used to provide a drive control signal to the pixel drive circuit 02, and the pixel drive circuit 02 operates according to the drive control signal. Figure 1 The top view only shows partial structures such as the pixel driving circuit 02 and the pixel driving control circuit 03 , and does not show other film layer structures such as the thin film transistor 2 and the first metal layer 7 .

[0030] The thin film transistor 2 described in the embodiment of the present application may be the thin film transistor 2 in the pixel driving circuit 02 or the thin film transistor 2 in the pixel driving control circuit 03 , and the present invention does not limit this.

[0031] refer to Figure 2The thin film transistor 2 includes an active layer 3, which may be a polycrystalline silicon active layer, such as, but not limited to, low temperature polycrystalline silicon (LTPS). The polycrystalline silicon thin film transistor 2 has the advantages of high switching speed, high mobility, and good stability. In the existing polycrystalline silicon thin film transistor 2, the electric field near the connection between the contact portion 4 and the channel portion 5 in the active layer 3 is very strong. The strong electric field accelerates electrons to become "hot electrons". The hot electrons will cause certain damage to the thin film transistor 2, and may cause leakage current in the thin film transistor 2 when it is in the off state, resulting in a decrease in the stability of the thin film transistor 2 and affecting the driving performance of the display panel.

[0032] To address the above issues, the present application provides an active layer 3 comprising a contact portion 4, a channel portion 5, and a doped portion 6. Along the plane in which the active layer 3 extends, the doped portion 6 is located between the contact portion 4 and the channel portion 5. The doped portion 6 can be a lightly doped region, which can reduce the electric field in the area where the contact portion 4 is located, thereby reducing leakage current.

[0033] Further, continue to refer to Figure 2 The display panel further includes a first metal layer 7 disposed on the surface of the thin film transistor 2 film layer on a side away from the base substrate 1. The first metal layer 7 can be used to form signal transmission lines, a light-shielding metal layer, or a connecting line between the thin film transistor 2 and the anode of the sub-pixel unit 01, but is not limited thereto. The film layer containing the thin film transistor 2 is the pixel drive circuit layer or the pixel drive control circuit layer. The film layer containing the thin film transistor 2 may include multiple stacked metal layers and insulating layers between adjacent metal layers. The metal layers are used to form the electrodes in the thin film transistor 2 and other electronic components in the circuit.

[0034] Among them, research has found that in the actual application of the display panel, the doped portion 6 of the thin film transistor 2 is more sensitive to the electric field. The doped portion 6 may generate a large number of electrons when excited by the electric field, affecting the charge distribution in the doped portion 6. Figure 3 Schematic diagram of a thin film transistor IDVG curve provided by an embodiment of the present invention, the IDVG curve is a characteristic curve of the drain current Id and the gate voltage Vg of the thin film transistor 2, as shown in FIG. Figure 3 As shown, curve 1 is the IDVG curve when thin film transistor 2 is not affected by the electric field, and curve 2 is the IDVG curve when thin film transistor 2 is affected by the electric field. It can be seen that under the action of the electric field, the gate voltage Vg decreases and the drain current Id increases, thereby causing the threshold voltage of thin film transistor 2 to decrease and the off-state voltage to increase.

[0035] To this end, the present application sets a plurality of first openings 8 in the first metal layer 7. Specifically, the first metal layer 7 in a partial area can be removed to form the first openings 8. Along the direction Z perpendicular to the plane where the display panel is located, the first opening 8 at least partially overlaps with the doping portion 6. The direction from the base substrate 1 to the first metal layer 7 can be defined as a downward-upward direction. Under this setting, the first opening 8 is located above the doping portion 6 in the active layer 3, and at least part of the area above the doping portion 6 is not covered by the first metal layer 7. In this way, the influence of the electric field of the first metal layer 7 on the doping portion 6 can be weakened, and the influence of the electric field generated by the first metal layer 7 on the threshold voltage and the off-state voltage of the thin film transistor 2 can be avoided, thereby improving the performance stability of the thin film transistor 2 and further improving the display performance of the display panel.

[0036] The embodiment of the present invention does not limit parameters such as the size and shape of the first opening 8 in the first metal layer 7 , and those skilled in the art may set them according to actual needs.

[0037] The pixel driving circuit 02 may also include electronic components such as capacitors (not shown in the figure). Figure 2 The cross-sectional view only illustrates one thin-film transistor 2 in pixel driver circuit 02. In practical applications, the pixel driver circuit may be a 2T1C circuit, a 7T1C circuit, or a 7T2C circuit, but is not limited thereto. A "2T1C circuit" refers to a pixel driver circuit 02 comprising two thin-film transistors 2 and one capacitor. Other circuits such as a "7T1C circuit," a "7T2C circuit," and so on can be deduced accordingly.

[0038] In an embodiment of the present invention, a display panel includes a base substrate; at least one thin film transistor located on one side of the base substrate, the thin film transistor including an active layer, the active layer including a contact portion, a channel portion and a doping portion, the doping portion being located between the contact portion and the channel portion; a first metal layer located on a side of the thin film transistor facing away from the base substrate, the first metal layer including a first opening; the doping portion at least partially overlaps with the first opening in a direction perpendicular to the plane where the display panel is located. The doping portion can reduce the electric field in the area where the contact portion is located, thereby reducing the leakage current of the thin film transistor. Arranging the first opening to overlap with the doping portion in a direction perpendicular to the plane where the display panel is located can reduce the influence of the electric field of the first metal layer on the doping portion, prevent the electric field from affecting the threshold voltage and off-state voltage of the thin film transistor, and thus improve the performance stability of the thin film transistor, thereby improving the display performance of the display panel.

[0039] Optional, you can continue to refer to Figure 2 In a possible embodiment, the display panel may further include an anode layer 9 located on the side of the first metal layer 7 facing away from the base substrate 1; the anode layer 9 includes a second opening 10, and along a direction Z perpendicular to the plane of the display panel, the doped portion 6 at least partially overlaps with the second opening 10.

[0040] Specifically, if Figure 2 As shown, the display panel is also provided with an anode layer 9, which is provided on the side of the first metal layer 7 away from the base substrate 1. The anode layer 9 includes a plurality of anodes, which are generally electrically connected to the driving transistor 2 in the pixel driving circuit for receiving the driving signal sent by the pixel driving circuit 02. Since the driving signal is transmitted in the anode, the electric field generated by the anode may also affect the doped part 6 during the display process of the display panel. Therefore, in this embodiment, a plurality of second openings 10 are provided in the anode layer 9, and specifically, the anode layer 9 in some areas can be removed to form the second openings 10. Along the direction Z perpendicular to the plane where the display panel is located, the second opening 10 at least partially overlaps with the doped part 6. Under this arrangement, the second opening 10 is located above the doped part 6 in the active layer 3, and at least part of the area above the doped part 6 is not covered by the anode layer 9. In this way, the influence of the electric field generated by the anode layer 9 on the doped part 6 can be weakened, further improving the performance stability of the thin film transistor 2.

[0041] Optionally, in other embodiments not shown, the side of the first metal layer 7 facing away from the base substrate 1 may be a FIAA routing layer, and the side of the FIAA routing layer facing away from the first metal layer 7 may be an anode layer 9. The FIAA routing is Fanout in AA (the fan-out routing is set in the display area), and part of the fan-out routing is set in the display area, thereby reducing the display panel frame. At this time, a plurality of third openings (not shown in the figure) may be set in the FIAA routing layer, and the projection of the third opening and the doping portion 6 in the direction Z perpendicular to the display panel overlap. Reduce the influence of the electric field generated by the FIAA routing on the doping portion 6.

[0042] Optionally, the embodiment of the present invention does not limit the relative positional relationship between the first opening 8 and the second opening 10 along the direction Z perpendicular to the plane where the display panel is located, and those skilled in the art may set it according to actual needs.

[0043] For example, please refer to Figure 2 In a possible embodiment, along a direction Z perpendicular to the plane where the display panel is located, the first opening 8 and the second opening 10 at least partially overlap.

[0044] like Figure 2 As shown, in this embodiment, the projections of the first opening 8 and the second opening 10 in the direction perpendicular to the plane of the display panel at least partially overlap, so that the overlapping area of ​​the first opening 8 and the second opening 10 is located above the doping portion 6, and at least part of the area above the doping portion 6 is neither blocked by the first metal layer 7 nor by the anode layer 9, and the anti-electric field interference effect is better.

[0045] in, Figure 2The diagram shows that, along a direction Z perpendicular to the plane of the display panel, the first opening 8 and the second opening 10 overlap, and both the first opening 8 and the second opening 10 overlap with the doped portion 6. The actual arrangement is not limited to this. With this arrangement, the doped portion 6 provides better resistance to electric field interference. Furthermore, the first opening 8 and the second opening 10 can be produced using the same mask, making the process relatively simple.

[0046] Optional, Figure 4 A partial cross-sectional structural diagram of a display panel provided by an embodiment of the present invention, with reference to Figure 4 In other possible embodiments, along a direction Z perpendicular to the plane where the display panel is located, the first opening 8 covers the second opening 10 .

[0047] like Figure 4 As shown, in this embodiment, the projection of the first opening 8 along a direction perpendicular to the plane of the display panel overlaps the projection of the second opening 10 along a direction perpendicular to the plane of the display panel. In other words, along the direction Z perpendicular to the plane of the display panel, the area of ​​overlap between the first opening 8 and the doped portion 6 is greater than the area of ​​overlap between the second opening 10 and the doped portion 6. Figure 4 The length of the first opening 8 (or the second opening 10) along the horizontal direction can be used to represent the area (or size) of the vertical projection of the first opening 8 (or the second opening 10). The longer the length of the first opening 8 (or the second opening 10) along the horizontal direction, the larger the area of ​​the first opening 8 (or the second opening 10) along the plane perpendicular to the display panel.

[0048] Because the distance between the anode layer 9 and the doped portion 6 is relatively large in a direction perpendicular to the plane of the display panel, the electric field of the anode layer 9 has a relatively small effect on the doped portion 6. Therefore, the area of ​​the second opening 10 can be appropriately reduced, so that a portion of the anode layer 9 overlaps the doped portion 6. In this way, the portion of the anode layer 9 that overlaps the doped portion 6 can act as a light shield, to a certain extent preventing light from above the anode layer 9 from reaching the doped portion 6, thus preventing the doped portion 6 from being exposed to light and generating photogenerated carriers, thereby further preventing the generation of leakage current.

[0049] Optional, Figure 5 A schematic diagram of a partial top view of a display panel provided by an embodiment of the present invention is shown. Figure 6 for Figure 5 Schematic diagram of the cross-section structure along the A-A' direction, Figure 5 In the illustrated embodiment, along a direction Z perpendicular to the plane of the display panel, the first opening 8 covers the doped portion 6 .

[0050] Specifically, if Figure 5 and Figure 6As shown, in an optional embodiment, the area of ​​the first opening 8 projected in a direction perpendicular to the plane of the display panel can be larger than the area of ​​the doped portion 6 projected in the same direction, so that the first opening 8 covers the doped portion 6. In this arrangement, the doped portion 6 is completely unobstructed by the first metal layer 7, which can largely prevent the electric field of the first metal layer 7 from affecting the doped portion 6.

[0051] Optional, Figure 7 A schematic diagram of a partial top view of another display panel provided by an embodiment of the present invention, Figure 8 for Figure 7 Schematic diagram of the cross-section structure along the B-B' direction, refer to Figure 7 and Figure 8 In another embodiment, the area of ​​the vertical projection of the first opening 8 on the plane where the active layer 3 is located can be set to be smaller than the area of ​​the doped portion 6.

[0052] Specifically, Figure 7 In the illustrated embodiment, the area of ​​the first opening 8 projected in a direction perpendicular to the plane of the display panel can be configured to be smaller than the area of ​​the doped portion 6 projected in the same direction. This allows the projection of the first opening 8 in a direction perpendicular to the plane of the display panel to lie within the projection of the doped portion 6 in the same direction. This configuration can simultaneously alleviate the issues of the doped portion 6 being affected by both electric field interference and light.

[0053] Further optional, Figure 9 A partial top view of another display panel provided by an embodiment of the present invention is shown. Figure 9 In the illustrated embodiment, when the projection area of ​​the first opening 8 is smaller than the projection area of ​​the doped portion 6 , the same doped portion 6 may overlap with at least two first openings 8 along a direction Z perpendicular to the plane of the display panel.

[0054] Specifically, if Figure 9 As shown, along the direction Z perpendicular to the plane of the display panel, the embodiment of the present invention can also be provided with the doped portion 6 overlapping with two or more first openings 8 at the same time. The first metal layer 7 is regarded as a plurality of resistors in parallel. Figure 7 As shown in FIG, each doping portion 6 is provided with only one first opening 8. Figure 9 The illustrated method is equivalent to increasing the number of parallel resistors, which is beneficial to reducing the impedance of the first metal layer 7 and improving the voltage transmission effect within the first metal layer 7 . Figure 9 FIG. 5 exemplarily shows two first openings 8 overlapping with the same doping portion 6 , but the actual arrangement is not limited thereto.

[0055] In the above embodiment, the areas of the first opening 8 and the doped portion 6 are not limited and can be set by those skilled in the art according to actual needs.

[0056] Optional, you can continue to refer to Figure 2 In a possible embodiment, the display panel may further include a light-shielding structure 11 , and the doped portion 6 is located within a vertical projection of the light-shielding structure 11 on the plane where the active layer 3 is located.

[0057] The presence of first opening 8 causes light to pass through first opening 8 and toward doped portion 6. As mentioned in the above embodiment, this light may generate photogenerated carriers within active layer 3, increasing leakage current. To avoid this problem, in the embodiment of the present application, a light shielding structure 11 is further provided within the display panel. Along a direction Z perpendicular to the plane of the display panel, the projection of light shielding structure 11 overlaps the projection of doped portion 6. Thus, along a direction Z perpendicular to the plane of the display panel, light shielding structure 11 at least covers the first opening 8 that overlaps with doped portion 6.

[0058] In this configuration, the light shielding structure 11 can block light from radiating toward the doped portion 6 through the first opening 8 , thereby preventing the doped portion 6 from generating leakage current under the irradiation of light, thereby further improving the stability of the thin film transistor 2 .

[0059] The embodiments of the present invention do not limit the specific configuration of the light-shielding structure 11 (including the film layer and structure, etc.), and those skilled in the art can configure it according to actual needs.

[0060] For example, please refer to Figure 2 The display panel may further include a first planarization layer 12 , which is located between the first metal layer 7 and the anode layer 9 ; the first planarization layer 12 is made of a black material, and the first planarization layer 12 is reused as the light shielding structure 11 .

[0061] like Figure 2 As shown, a first planarization layer 12 is further provided on the side of the first metal layer 7 facing away from the substrate 1 . The side of the first planarization layer 12 facing away from the first metal layer 7 is the anode layer 9 . The first planarization layer 12 can play the role of insulation and planarization.

[0062] In this embodiment, the first planarization layer 12 can be prepared using a black insulating material, so that the first planarization layer 12 is a black planarization layer. In this case, the first planarization layer 12 can be reused as the light-shielding structure 11. The advantage of reusing the first planarization layer 12 as the light-shielding structure 11 is that the light-shielding structure 11 (i.e., the first planarization layer 12) is provided as an entire layer. Along the direction Z perpendicular to the plane of the display panel, the light-shielding structure 11 can completely cover the first opening 8 and the second opening 10, thereby achieving a good light-shielding effect.

[0063] Among them, those skilled in the art can select a preparation method of the black planarization layer according to actual needs, and the embodiments of the present invention will not elaborate on this and will not limit this.

[0064] Optional, you can continue to refer to Figure 2 The first metal layer 7 also includes a non-opening portion 13, which is located between any two adjacent first openings 8; along the direction Z perpendicular to the plane of the display panel, the thickness d1 of the first planarization layer 12 overlapping with the first opening 8 is greater than or equal to the thickness d2 of the first planarization layer 12 overlapping with the non-opening portion 13.

[0065] like Figure 2 As shown, the unremoved area of ​​the first metal layer 7 is a non-opening portion 13, which is located between two adjacent first openings 8 in any direction parallel to the plane of the display panel. Because the non-opening portion 13 has a certain thickness in the direction perpendicular to the plane of the display panel, the thickness d1 of the portion of the first planarization layer 12 above the first opening 8 can be set to be greater than the thickness d2 of the portion of the first planarization layer 12 above the non-opening portion 13. This makes the surface of the first planarization layer 12 facing away from the first metal layer 7 relatively flat, which is conducive to the subsequent formation of other film layers. In addition, the thicker first planarization layer 12 at the first opening 8 can provide a better light-shielding effect, preventing light from passing through the first opening 8.

[0066] Optional, Figure 10 A partial cross-sectional structural diagram of another display panel provided in an embodiment of the present invention can be referred to Figure 10 In a possible embodiment, the display panel may further include a second planarization layer 14, which is located between the film layer where the thin film transistor 2 is located and the first metal layer 7. The second planarization layer 14 is made of black material, and the second planarization layer 14 is reused as the shading structure 11.

[0067] like Figure 10 As shown, in this embodiment, a second planarization layer 14 is further provided on the side of the film layer where the thin film transistor 2 is located away from the base substrate 1, and the side of the second planarization layer 14 away from the film layer where the thin film transistor 2 is located is the first metal layer 7, and the second planarization layer 14 can also play the role of insulation and planarization.

[0068] In this embodiment, the second planarization layer 14 can be made of a black insulating material, so that the second planarization layer 14 is a black planarization layer. In this case, the second planarization layer 14 can be reused as the light shielding structure 11. The second planarization layer 14 is also provided as a whole layer, so that the light shielding structure 11 completely covers the first opening 8 and the second opening 10 along the direction Z perpendicular to the plane of the display panel.

[0069] In other embodiments, the first planarization layer 12 and the second planarization layer 14 may both be made of black material, and both are reused as the light shielding structure 11 to further enhance the light shielding effect on the doped portion 6 .

[0070] Figure 11A partial cross-sectional structural diagram of another display panel provided in an embodiment of the present invention is shown in FIG. Figure 11 In other optional embodiments, the light shielding structure 11 may be filled in the first opening 8 and / or the second opening 10 .

[0071] Figure 11 In the embodiment shown, black light shielding material may be deposited only in the first opening 8 and / or the second opening 10 to form the light shielding structure 11. In this case, the planarization layers on both sides of the first metal layer 7 may be transparent planarization layers, which may be prepared using conventional processes. Figure 11 As shown in FIG, the first opening 8 is filled with a light shielding structure 11 , but the present invention is not limited thereto.

[0072] Optional, you can continue to refer to Figure 2 The thin film transistor 2 also includes a gate G, a source S and a drain D. The gate G is arranged in a different layer from the active layer 3. Along the direction Z perpendicular to the plane where the display panel is located, the gate G overlaps with the channel portion 5; the contact portion 4 overlaps with the source S and the drain D respectively; along the direction parallel to the plane where the active layer 3 is located, the doped portion 6 is located between the channel portion 5 and the contact portion 4.

[0073] Specifically, if Figure 2 As shown, the thin film transistor 2 is composed of a gate G, a source S, a drain D and an active layer 3. The source S and the drain D are respectively overlapped with the active layer 3, and the area of ​​the active layer 3 that overlaps with the source S and the drain D is a contact portion 4 of the active layer 3.

[0074] The gate G of the thin-film transistor 2 is disposed in a separate layer from the active layer 3. The thin-film transistor 2 shown in the figure has a top-gate structure, with the gate G located above the active layer 3. In other embodiments, the gate G may also be located below the active layer 3, forming a bottom-gate thin-film transistor 2. The region of the active layer 3 where the Z projection of the gate G overlaps perpendicular to the plane of the display panel is the channel portion 5 of the active layer 3. The portion of the active layer 3 between the channel portion 5 and the two contact portions 4 is the doped portion 6 of the active layer 3.

[0075] Optional, Figure 12 A partial cross-sectional structural diagram of another display panel provided in an embodiment of the present invention is shown in FIG. Figure 12In a possible embodiment, the contact portion 4 includes a first sub-contact portion 41 and a second sub-contact portion 42, the first sub-contact portion 41 overlaps the source S, and the second sub-contact portion 42 overlaps the drain D; the doped portion 6 includes a first sub-doped portion 61 and a second sub-doped portion 62, along a direction parallel to the plane where the active layer 3 is located, the first sub-doped portion 61 is located between the first sub-contact portion 41 and the channel portion 5, and the second sub-doped portion 62 is located between the second sub-contact portion 42 and the channel portion 5; the first opening 8 includes a first sub-opening 81 and a second sub-opening 82, along a direction perpendicular to the display In the direction Z of the plane where the panel is located, the first sub-opening 81 overlaps with the first sub-doped portion 61, and the second sub-opening 82 overlaps with the second sub-doped portion 62; wherein, the projection area of ​​the first sub-opening 81 along the direction Z perpendicular to the plane where the display panel is located is less than or equal to the projection area of ​​the second sub-opening 82 along the direction Z perpendicular to the plane where the display panel is located; and / or, along the direction Z perpendicular to the plane where the display panel is located, the thickness d3 of the shading structure 11 overlapping with the first sub-doped portion 61 is less than or equal to the thickness d4 of the shading structure 11 overlapping with the second sub-doped portion 62.

[0076] like Figure 12 As shown, in this embodiment, the contact portion 4 overlapping the source electrode S of the thin film transistor 2 can be defined as a first sub-contact portion 41, and the contact portion 4 overlapping the drain electrode D can be defined as a second sub-contact portion 42. Accordingly, the doped portion 6 between the channel portion 5 and the first sub-contact portion 41 can be defined as a first sub-doped portion 61, and the doped portion 6 between the channel portion 5 and the second sub-contact portion 42 can be defined as a second sub-doped portion 62. The first sub-doped portion 61 is closer to the source electrode S, and the second sub-doped portion 62 is closer to the drain electrode D.

[0077] refer to Figure 12 , the first opening 8 can be further divided into a first sub-opening 81 and a second sub-opening 82. The projection of the first sub-opening 81 along the direction perpendicular to the plane of the display panel overlaps with the projection of the first sub-doped portion 61 along the same direction; the projection of the second sub-opening 82 along the direction perpendicular to the plane of the display panel overlaps with the projection of the second sub-doped portion 62 along the same direction. Correspondingly, when a shading structure 11 is provided in the display panel, the shading structure 11 can also be divided into a first sub-shading structure 111 and a second sub-shading structure 112. Along the direction Z perpendicular to the plane of the display panel, the projection of the first sub-shading structure 111 covers the projection of the first sub-doped portion 61, and the projection of the second sub-shading structure 112 covers the projection of the second sub-doped portion 62.

[0078] Generally, the drain D of the thin film transistor 2 is the output terminal of the thin film transistor 2, and the second sub-doping portion 62 near the drain D is more sensitive to the electric field. To address this, in the embodiment of the present application, the size of the second sub-opening 82 overlapping with the second sub-doping portion 62 in the direction Z perpendicular to the plane of the display panel can be set to be larger than the size of the first sub-opening 81 overlapping with the first sub-doping portion 61, thereby improving the second doping portion 62's ability to prevent electric field interference. Alternatively, the thickness d4 of the second sub-light-shielding structure 112 overlapping with the second sub-doping portion 62 in the direction Z perpendicular to the plane of the display panel can be set to be larger than the thickness d3 of the first sub-light-shielding structure 111 overlapping with the first sub-doping portion 61, thereby improving the second sub-doping portion 62's ability to prevent light interference. Alternatively, the first sub-opening 81, the second sub-opening 82, the first sub-light-shielding structure 111, and the second sub-light-shielding structure 112 can be set to meet both of the above conditions to simultaneously enhance the second sub-doping portion 62's ability to prevent electric field interference and light interference.

[0079] One thing that needs to be explained is that Figure 12 The horizontal lengths of the first sub-opening 81 and the second sub-opening 82 represent their vertical projection areas. The horizontal length L1 of the second sub-opening 82 is greater than the horizontal length L2 of the first sub-opening 81, indicating that the second sub-opening 82 is larger in a direction perpendicular to the plane of the display panel.

[0080] Optional, Figure 13 A partial cross-sectional structural diagram of another display panel provided in an embodiment of the present invention is shown in FIG. Figure 13 In a possible embodiment, the thin film transistor 2 includes an N-type field effect transistor 21 and a P-type field effect transistor 22; along a direction Z perpendicular to the plane where the display panel is located, an area of ​​the first opening 8 overlapping with the doped portion 6 of the N-type field effect transistor 21 is larger than an area of ​​the first opening 8 overlapping with the doped portion 6 of the P-type field effect transistor 22; and / or, along a direction Z perpendicular to the plane where the display panel is located, a thickness of the shading structure 11 overlapping with the doped portion 6 of the N-type field effect transistor 21 is larger than a thickness of the shading structure 11 overlapping with the doped portion 6 of the P-type field effect transistor 22.

[0081] Specifically, in the present application, the thin film transistor 2 may be a complementary metal oxide semiconductor (CMOS) device, which includes both NMOS and PMOS transistors. The NMOS transistor is an N-type field effect transistor 21, and the PMOS transistor is a P-type field effect transistor 22. The contact portion 4 of the N-type field effect transistor 21 is heavily doped with N-type ions, and the contact portion 4 of the P-type field effect transistor 22 is heavily doped with P-type ions.

[0082] Those skilled in the art will appreciate that the carriers conducted in the N-type field-effect transistor 21 are electrons, while the carriers conducted in the P-type field-effect transistor 22 are holes. Electrons have a much greater mobility than holes and can obtain greater energy under the same electric field. Therefore, compared to the P-type field-effect transistor 22, the electric field of the contact portion 4 of the N-type field-effect transistor 21 is stronger, and the doped portion 6 has a more significant effect in suppressing the hot electron effect.

[0083] Based on the above reasons, embodiments of the present application may also provide differentiated configurations for the first opening 8 and / or light-shielding structure 11 in the N-type field-effect transistor 21 and the P-type field-effect transistor 22. In the direction Z perpendicular to the plane of the display panel, the first opening 8 overlapping the doped portion 6 of the N-type field-effect transistor 21 may be defined as a third sub-opening 83, and the first opening 8 overlapping the doped portion 6 of the P-type field-effect transistor 22 may be defined as a fourth sub-opening 84. The light-shielding structure 11 overlapping the doped portion 6 of the N-type field-effect transistor 21 may be defined as a third sub-light-shielding structure 113, and the light-shielding structure 11 overlapping the doped portion 6 of the P-type field-effect transistor 22 may be defined as a fourth sub-light-shielding structure 114. In the present application, compared to the P-type field-effect transistor 22, the third sub-opening 83 overlapping the doped portion 6 of the N-type field-effect transistor 21 in the direction Z perpendicular to the plane of the display panel may be larger, and / or the third sub-light-shielding structure 113 overlapping the doped portion 6 of the N-type field-effect transistor 21 may be thicker. This ensures that the doped portion 6 in the N-type field effect transistor 21 is not affected by the electric field and light, thereby ensuring the normal operation of the CMOS device.

[0084] Figure 13 The vertical projection areas of the third and fourth sub-openings 83 and 84 are represented by their horizontal lengths. The horizontal length L3 of the third sub-opening 83 is greater than the horizontal length L4 of the fourth sub-opening 84, indicating that the third sub-opening 83 is larger in a direction perpendicular to the plane of the display panel. Furthermore, the thickness d5 of the third sub-light-shielding structure 113 is greater than the thickness d6 of the fourth sub-light-shielding structure 114.

[0085] In other embodiments not shown, the first opening 8 may be provided only above the doped portion 6 of the N-type field effect transistor 21, and the doped portion 6 of the P-type field effect transistor 22 is still covered with the first metal layer 7, thereby simplifying the preparation process of the thin film transistor 2 array.

[0086] The display panel provided in the embodiment of the present invention may further include any structure known to those skilled in the art, such as a thin film encapsulation layer, etc., which will not be elaborated or limited in the embodiment of the present invention.

[0087] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Figure 14Schematic diagram of the structure of a display device provided by an embodiment of the present invention. Figure 14 As shown, the display device includes the display panel 100 provided by any embodiment of the present invention. Therefore, the display device provided by the embodiment of the present invention has the corresponding beneficial effects of the display panel provided by the embodiment of the present invention, which will not be described in detail here. Exemplarily, the display device can be an electronic device such as a mobile phone, a computer, a smart wearable device (for example, a smart watch), and an in-vehicle display device, which is not limited by the embodiment of the present invention.

[0088] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments herein, and that various obvious changes, readjustments, combinations, and substitutions are possible for those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: substrate; at least one thin film transistor located on one side of the substrate, the thin film transistor comprising an active layer, the active layer comprising a contact portion, a channel portion, and a doped portion, the doped portion being located between the contact portion and the channel portion; a first metal layer located on a side of the thin film transistor facing away from the base substrate, the first metal layer comprising a first opening; along a direction perpendicular to the plane of the display panel, the doped portion at least partially overlaps the first opening; At least a portion of the area above the doped portion is not covered by the first metal layer, so as to reduce the influence of the electric field of the first metal layer on the doped portion.

2. The display panel according to claim 1, wherein: It also includes an anode layer located on a side of the first metal layer away from the base substrate; the anode layer includes a second opening, and along a direction perpendicular to the plane where the display panel is located, the doped portion and the second opening at least partially overlap.

3. The display panel according to claim 2, wherein: Along a direction perpendicular to a plane where the display panel is located, the first opening and the second opening at least partially overlap.

4. The display panel according to claim 3, wherein: Along a direction perpendicular to a plane where the display panel is located, the first opening covers the second opening.

5. The display panel according to claim 1, wherein: Along a direction perpendicular to a plane where the display panel is located, the first opening covers the doped portion.

6. The display panel according to claim 1, wherein: An area of ​​a vertical projection of the first opening on a plane where the active layer is located is smaller than an area of ​​the doped portion.

7. The display panel according to claim 6, wherein: Along a direction perpendicular to the plane where the display panel is located, the same doped portion overlaps with at least two of the first openings.

8. The display panel according to claim 2, wherein: It also includes a light-shielding structure, and the doped portion is located within a vertical projection of the light-shielding structure on the plane where the active layer is located.

9. The display panel according to claim 8, wherein: It also includes a first planarization layer, which is located between the first metal layer and the anode layer; the first planarization layer is made of black material, and the first planarization layer is reused as the light-shielding structure.

10. The display panel according to claim 9, wherein: The first metal layer further includes a non-opening portion, and the non-opening portion is located between any two adjacent first openings; Along a direction perpendicular to the plane where the display panel is located, a thickness of a portion of the first planarization layer overlapping the first opening is greater than or equal to a thickness of a portion of the first planarization layer overlapping the non-opening portion.

11. The display panel according to claim 8, wherein It also includes a second planarization layer, which is located between the film layer where the thin film transistor is located and the first metal layer. The second planarization layer is made of black material and is reused as the light-shielding structure.

12. The display panel according to claim 8, wherein The light shielding structure is filled in the first opening and / or the second opening.

13. The display panel according to claim 8, wherein The thin film transistor further includes a gate, a source, and a drain, wherein the gate is arranged in a different layer from the active layer, and along a direction perpendicular to the plane where the display panel is located, the gate overlaps the channel portion; The contact portion is respectively overlapped with the source electrode and the drain electrode; Along a direction parallel to the plane where the active layer is located, the doped portion is located between the channel portion and the contact portion.

14. The display panel according to claim 13, wherein: The contact portion includes a first sub-contact portion and a second sub-contact portion, the first sub-contact portion overlaps the source electrode, and the second sub-contact portion overlaps the drain electrode; The doped portion includes a first sub-doped portion and a second sub-doped portion, wherein along a direction parallel to the plane where the active layer is located, the first sub-doped portion is located between the first sub-contact portion and the channel portion, and the second sub-doped portion is located between the second sub-contact portion and the channel portion; The first opening includes a first sub-opening and a second sub-opening, and along a direction perpendicular to the plane where the display panel is located, the first sub-opening overlaps with the first sub-doped portion, and the second sub-opening overlaps with the second sub-doped portion; In which, the projected area of ​​the first sub-opening along the direction perpendicular to the plane where the display panel is located is less than or equal to the projected area of ​​the second sub-opening along the direction perpendicular to the plane where the display panel is located; and / or, along the direction perpendicular to the plane where the display panel is located, the thickness of the shading structure overlapping with the first sub-doped portion is less than or equal to the thickness of the shading structure overlapping with the second sub-doped portion.

15. The display panel according to claim 8, wherein The thin film transistor includes an N-type field effect transistor and a P-type field effect transistor; along a direction perpendicular to the plane of the display panel, an area of ​​the first opening overlapping with the doped portion of the N-type field effect transistor is larger than an area of ​​the first opening overlapping with the doped portion of the P-type field effect transistor; and / or, Along a direction perpendicular to the plane of the display panel, a thickness of the light-shielding structure overlapping with the doped portion of the N-type field effect transistor is greater than a thickness of the light-shielding structure overlapping with the doped portion of the P-type field effect transistor.

16. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 15.

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