Semiconductor device and method of manufacturing the same

Abstract

In a semiconductor device, a first deep layer (15) disposed below and separated from the channel (25) of the channel gate structure in the drift layer (19) has a high concentration region (15a) and a low concentration region (15b) in the impurity concentration curve along the depth direction. The high concentration region has a high concentration peak with the largest impurity concentration and includes a region that is not depleted in the off state. The low concentration region (15b) is disposed closer to the high concentration layer (11) than the high concentration region, has a region where the impurity concentration change gradient is less than a predetermined value, and is depleted in the off state. The first length (L1) between the first position (P1) closest to the substrate layer in the first deep layer and the second position (P2) of the high concentration peak is less than the second length (L2) between the second position and the third position (P3) closest to the substrate layer in the low concentration region.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices having a channel gate structure and methods for manufacturing the same. Background Technology

[0002] For example, semiconductor devices having semiconductor elements such as metal-oxide-semiconductor field-effect transistors (MOSFETs) are known, for example in JP 2019-46908A. Such semiconductor devices include a semiconductor substrate having a drift layer, a base layer disposed near a surface of the semiconductor substrate, and a source region disposed in a surface portion of the base layer. The semiconductor substrate has a channel penetrating the source region and the base layer. A gate insulating film and a gate electrode are disposed in the channel, thereby forming a channel gate structure.

[0003] The drain region is located near the other surface of the semiconductor substrate. The upper electrode is located near one surface of the semiconductor substrate to electrically connect to the source region and the substrate layer. The lower electrode is located near the other surface of the semiconductor substrate to electrically connect to the drain region.

[0004] Furthermore, in this semiconductor device, the deep layer is disposed in the drift layer below the channel and is connected to the substrate layer while being separated from the channel. Therefore, in this semiconductor device, damage to the gate insulating film due to the depletion layer formed between the deep layer and the drift layer can be suppressed. Summary of the Invention

[0005] In such semiconductor devices, it is necessary to suppress the decrease in breakdown voltage while suppressing the damage to the gate insulating film, and to suppress the increase in size along the stacking direction of the drift layer and the substrate layer.

[0006] One object of this disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device, which can suppress the decrease in breakdown voltage while suppressing gate insulating film damage, and suppress the increase in size along the stacking direction of the drift layer and the substrate layer.

[0007] According to one aspect of this disclosure, a semiconductor device includes: a drift layer of a first conductivity type; a substrate layer of a second conductivity type disposed on a surface portion of the drift layer; an impurity region of the first conductivity type disposed on the surface portion of the substrate layer, and having an impurity concentration higher than that of the drift layer; a channel gate structure including a gate insulating film disposed on a channel wall, the channel penetrating the substrate layer and the impurity region and reaching the drift layer, and a gate electrode disposed on the gate insulating film; a first deep layer of a second conductivity type disposed below the channel in the drift layer and separated from the channel; a second deep layer of the second conductivity type connecting the substrate layer and the first deep layer; a high-concentration layer of the first or second conductivity type disposed opposite to the substrate layer relative to the drift layer, and having an impurity concentration higher than that of the drift layer; a first electrode electrically connected to the substrate layer and the impurity region; and a second electrode electrically connected to the high-concentration layer. The semiconductor device is configured to be in an on state when a gate voltage equal to or higher than a predetermined voltage is applied to the gate electrode, so as to generate a current between the first electrode and the second electrode, and is configured to be in an off state when a gate voltage lower than the predetermined voltage is applied to the gate electrode. The first deep layer has high-concentration and low-concentration regions in its impurity concentration curve along the depth direction, corresponding to the stacking direction of the drift layer and the substrate layer. The high-concentration region has a high-concentration peak with the largest impurity concentration and includes areas that are not depleted in the disconnected state. Compared to the high-concentration region, the low-concentration region is located closer to the high-concentration layer, has areas where the impurity concentration gradient is less than a predetermined value, and is depleted in the disconnected state. The position closest to the substrate layer in the first deep layer is called the first position. The position of the high-concentration peak is called the second position. The position closest to the substrate layer in the low-concentration region is called the third position. The high-concentration region is located between the first and third positions. Furthermore, the first length between the first and second positions is shorter than the second length between the second and third positions.

[0008] In this configuration, the first deep layer has a concentration profile including high-concentration and low-concentration regions. The high-concentration region has a high concentration peak, and its impurity concentration does not lead to depletion in the off-state. The low-concentration region has an impurity concentration that leads to depletion in the off-state. Therefore, the reduction in breakdown voltage can be suppressed while suppressing gate insulating film damage. Furthermore, the first deep layer is configured such that the first distance is shorter than the second distance. Therefore, compared to semiconductor devices with the same breakdown voltage where the first distance is equal to or greater than the second distance, the length of the first deep layer in the stacking direction can be reduced. Therefore, the possibility of increasing the size of the semiconductor device in the stacking direction is smaller.

[0009] According to one aspect of this disclosure, a method of manufacturing a semiconductor device of the above aspect includes: preparing a constituent substrate including a portion of a drift layer adjacent to a high-concentration layer; forming a first deep layer by ion implantation of the constituent substrate; and forming a drift layer having the first deep layer by epitaxially growing the constituent layer on the first deep layer.

[0010] In this method, the concentration profile of the formed first deep layer has a high-concentration region and a low-concentration region. The high-concentration region has a high-concentration peak, the impurity concentration of which does not lead to depletion in the off-state, while the low-concentration region has an impurity concentration that leads to depletion in the off-state. Therefore, a semiconductor device can be manufactured that suppresses breakdown voltage reduction while suppressing gate insulating film damage. Furthermore, the first deep layer is formed such that its first length is shorter than its second length. Therefore, compared to a semiconductor device with the same breakdown voltage where the first length is equal to or greater than the second length, the length of the first deep layer in the stacking direction can be shortened. Thus, a semiconductor device can be manufactured that suppresses dimensional increases in the stacking direction. Attached Figure Description

[0011] The purpose, features, and advantages of this disclosure will become more apparent from the following detailed description with reference to the accompanying drawings, in which:

[0012] Figure 1 These are perspective and cross-sectional views of a SiC semiconductor device according to the first embodiment;

[0013] Figure 2 This is a schematic diagram showing the concentration curves of the current-spreading layer and the first deep layer;

[0014] Figure 3A This is a cross-sectional view showing the manufacturing process of SiC semiconductor devices;

[0015] Figure 3B It shows from Figure 3A The diagram shows a cross-sectional view of the SiC semiconductor device manufacturing process, which continues the manufacturing process.

[0016] Figure 3C It shows from Figure 3B The diagram shows a cross-sectional view of the manufacturing process of SiC semiconductor devices, continuing the manufacturing process.

[0017] Figure 3D shows the transition from... Figure 3C The diagram shows a cross-sectional view of the manufacturing process of SiC semiconductor devices, continuing the manufacturing process.

[0018] Figure 3E It shows from Figure 3D The diagram shows a cross-sectional view of the manufacturing process of SiC semiconductor devices, continuing the manufacturing process.

[0019] Figure 3FIt shows from Figure 3E The diagram shows a cross-sectional view of the manufacturing process of SiC semiconductor devices, continuing the manufacturing process.

[0020] Figure 4A This is a schematic diagram showing the concentration curves of the current-spreading layer and the first deep layer according to a modified example of the first embodiment; and

[0021] Figure 4B This is a schematic diagram showing the concentration curves of the current-spreading layer and the first deep layer according to another modification of the first embodiment. Detailed Implementation

[0022] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the embodiments described below, the same or equivalent components will be designated by the same reference numerals.

[0023] (First Embodiment)

[0024] A semiconductor device according to a first embodiment will be described with reference to the accompanying drawings. For example, the semiconductor device of this embodiment is mounted in a vehicle such as an automobile and used as a device for driving various electronic devices of the vehicle. As an example of a semiconductor device, a silicon carbide (hereinafter also referred to as SiC) semiconductor device will be described, in which a reverse MOSFET with a channel gate structure is formed. In this embodiment, the construction of the cell region forming the MOSFET will be described. However, SiC semiconductor devices actually have an outer peripheral region formed with a field confinement ring (FLR) structure, etc., to surround the cell region.

[0025] In the following text, the direction along the surface of substrate 11, i.e., the direction along the plane of substrate 11, is defined as the X-axis direction, and another direction along the plane of substrate 11 that intersects with the X-axis direction is defined as the Y-axis direction. Furthermore, a direction orthogonal to both the X-axis and Y-axis directions is defined as the Z-axis direction. In this embodiment, the X-axis and Y-axis directions are orthogonal to each other. The Z-axis direction in this embodiment corresponds to the depth direction of semiconductor substrate 10 (which will be described later) and also corresponds to the stacking direction of drift layer 19 and base layer 21 (which will be described later).

[0026] SiC semiconductor devices are constructed using a semiconductor substrate 10, such as... Figure 1 As shown. Specifically, SiC semiconductor devices include n made of SiC. + Substrate 11. In this embodiment, substrate 11 has a deflection angle of 0 to 8 degrees relative to, for example, a (0001) Si plane. Furthermore, substrate 11 has, for example, a nitrogen or phosphorus substrate of 1.0 × 10⁻⁶. 19 / cm 3The substrate 11 has an n-type impurity concentration and a thickness of approximately 300 micrometers (μm). In this embodiment, the substrate 11 forms the drain region and corresponds to the high-concentration layer.

[0027] n made of SiC - An n-type impurity layer 12 is disposed on the surface of the substrate 11. The buffer layer 12 is formed by epitaxial growth on the surface of the substrate 11. The buffer layer 12 has an n-type impurity concentration between that of the substrate 11 and the low-concentration layer 13, and has a thickness of about 1 μm.

[0028] n - A low-concentration layer 13 is disposed on the surface of the buffer layer 12. The low-concentration layer 13 is made of SiC and has, for example, a density of 5.0 × 10⁻⁶. 15 Up to 10.0×10 15 / cm 3 The low-concentration layer 13 has an n-type impurity concentration and a thickness of approximately 10 μm to 15 μm. The low-concentration layer 13 can have a constant impurity concentration along the Z-axis. However, the low-concentration layer 13 preferably has a concentration distribution gradient, such that the concentration is higher on the side closer to the substrate 11 than on the side farther from the substrate 11. For example, in the low-concentration layer 13, a portion approximately 3 μm to 5 μm separated from the surface of the substrate 11 can have an impurity density approximately 2.0 x 10⁻⁶ higher than that of the other portion. 15 / cm 3 The impurity concentration. With the above configuration, the internal resistance of the low-concentration layer 13 can be reduced, and the on-resistance can also be reduced.

[0029] JFET portion 14 and first deep layer 15 are disposed on the surface portion of low-concentration layer 13. In this embodiment, JFET portion 14 and first deep layer 15 extend along the X-axis direction and have linear portions that are alternately and repeatedly arranged along the Y-axis direction. That is, JFET portion 14 and first deep layer 15 are arranged as strips extending along the X-axis direction and alternately arranged in the Y-axis direction. In other words, in a plan view orthogonal to the surface of substrate 11, i.e., when viewed along a direction orthogonal to the surface of substrate 11, JFET portion 14 and first deep layer 15 are arranged as strips extending along the X-axis direction and alternately arranged in the Y-axis direction. The direction orthogonal to the surface of substrate 11 corresponds to the stacking direction of drift layer 19 and base layer 21, which will be described later.

[0030] JFET portion 14 has a higher n-type impurity concentration than the low-concentration layer 13 and a depth of 0.3 μm to 1.5 μm. In this embodiment, the n-type impurity concentration of JFET portion 14 is 7.0 × 10⁻⁶. 16 Up to 5.0×10 17 / cm 3 The impurity concentration in the first deep layer 15 will be described in detail later.

[0031] In this embodiment, the first deep layer 15 is shallower than the JFET portion 14. That is, the first deep layer 15 is formed such that the bottom of the first deep layer 15 is located inside the JFET portion 14. In other words, the first deep layer 15 is formed such that the JFET portion 14 is located between the first deep layer 15 and the low-concentration layer 13.

[0032] The current spreading layer 17, the second deep layer 18, the base layer 21, the source region 22, the contact region 23, etc. are all formed on the JFET portion 14 and the first deep layer 15.

[0033] The current spreading layer 17 has an n-type conductivity and is formed to connect to the JFET portion 14. Therefore, in this embodiment, the low-concentration layer 13, the JFET portion 14, and the current spreading layer 17 are interconnected. The low-concentration layer 13, the JFET portion 14, and the current spreading layer 17 form a drift layer 19. A first deep layer 15 is disposed in the drift layer 19.

[0034] The second deep layer 18 is p-type conductive and has the same thickness as the current spreading layer 17. The second deep layer 18 is formed to connect to the first deep layer 15.

[0035] The current spreading layer 17 and the second deep layer 18 extend in a direction intersecting the longitudinal direction of the strip portion of the JFET portion 14 and the first deep layer 15. In this embodiment, the current spreading layer 17 and the second deep layer 18 are positioned such that the current spreading layer 17 and the second deep layer 18 extend in the Y-axis direction as the longitudinal direction and are alternately arranged in the X-axis direction. The formation pitch of the current spreading layer 17 and the second deep layer 18 corresponds to the formation pitch of the channel gate structure, which will be described later. The second deep layer 18 is positioned between each channel 25, which will also be described later.

[0036] The substrate 21 has a p-type conductivity and is disposed on the current spreading layer 17 and the second deep layer 18. Therefore, the first deep layer 15 is connected to the substrate 21 via the second deep layer 18.

[0037] The conductivity type of source region 22 is n. + The source region 22 is disposed on the surface portion of the substrate layer 21. The conductivity type of the contact region 23 is p. + The substrate layer 21 has a contact region 23 disposed on the surface portion thereof. Specifically, the source region 22 is configured to contact the side surface of the channel 25, which will be described later, and the contact region 23 is disposed opposite the source region 22 to the channel 25. In this embodiment, the source region 22 corresponds to the impurity region.

[0038] The base layer 21 has, for example, 3.0 × 10⁻⁶. 17 / cm3 Or even lower p-type impurity concentration. The substrate layer 21 in this embodiment is formed, for example, by ion implantation. For example, the source region 22 has an n-type impurity concentration of 1.0 × 10⁻⁶ in its surface portion. 21 / cm 3 The surface concentration. For example, contact region 23 has a p-type impurity concentration in the surface portion, i.e., 1.0 × 10⁻⁶. 21 / cm 3 Surface concentration.

[0039] In this embodiment, as described above, the semiconductor substrate 10 is configured to include a substrate 11, a buffer layer 12, a low-concentration layer 13, a JFET portion 14, a first deep layer 15, a current spreading layer 17, a second deep layer 18, a base layer 21, a source region 22, a contact region 23, etc. Therefore, since the semiconductor substrate 10 is configured as described above, it can be said that the semiconductor substrate 10 is made of SiC. In this embodiment, the first surface 10a of the semiconductor substrate 10 is provided by the source region 22 and the contact region 23, and the second surface 10b of the semiconductor substrate 10, opposite to the first surface 10a, is provided by the substrate 11.

[0040] A channel 25 is formed in the semiconductor substrate 10, which penetrates the source region 22, the substrate layer 21, etc., and reaches the current spreading layer 17, such that the bottom surface of the channel 25 is located within the current spreading layer 17. For example, the width of the channel 25 is, for example, 1.4 to 2.0 μm. The channel 25 is configured not to reach the JFET portion 14 and the first deep layer 15. That is, the channel 25 is configured such that the JFET portion 14 and the first deep layer 15 are located below the bottom surface and separated from the channel 25.

[0041] although Figure 1 Only one channel 25 is shown, but the semiconductor substrate 10 actually has multiple channels 25 formed therein. These multiple channels 25 actually extend in the Y-axis direction and are arranged in a strip shape at regular intervals in the X-axis direction. That is, in this embodiment, the channels 25 are formed such that the longitudinal direction of the channels 25 is orthogonal to the longitudinal direction of the first deep layer 15. Moreover, in a plan view along the stacking direction of the drift layer 19 and the base layer 21, the channels 25 are formed between the second deep layers 18.

[0042] A gate insulating film 26 is disposed on the inner wall surface of the channel 25, and a gate 27 made of doped polysilicon is disposed on the gate insulating film 26. Thus, a channel gate structure is formed. Although not particularly limited, the gate insulating film 26 is formed by thermal oxidation of the inner wall surface of the channel 25 or by performing a chemical vapor deposition (CVD) method. The gate insulating film 26 has a thickness of approximately 100 nm on both the sidewalls and bottom wall of the channel 25.

[0043] A gate insulating film 26 is also formed on a surface other than the inner wall surface of the channel 25. Specifically, the gate insulating film 26 is formed such that it also partially covers the first surface 10a of the semiconductor substrate 10. More specifically, the gate insulating film 26 is formed such that it also partially covers the surface of the source region 22. In other words, the gate insulating film 26 has contact holes 26a for exposing the source region 22 and the contact region 23 at locations different from the location of the gate 27.

[0044] An interlayer insulating film 28 is disposed on the first surface 10a of the semiconductor substrate 10 to cover the gate electrode 27, the gate insulating film 26, etc. The interlayer insulating film 28 is made of borosilicate glass (BPSG) or the like.

[0045] The interlayer insulating film 28 has a contact hole 28a formed therein, which connects to contact hole 26a and exposes source region 22 and contact region 23. The contact hole 28a of the interlayer insulating film 28 connects to the contact hole 26a of the gate insulating film 26, thus the contact hole 28a of the interlayer insulating film 28 and the contact hole 26a of the gate insulating film 26 together serve as a single contact hole. Hereinafter, contact hole 26a and contact hole 28a are collectively referred to as contact hole 26b. Contact hole 26b can have any pattern. For example, contact hole 26b can have a pattern of arranging multiple square holes, a pattern of arranging rectangular linear holes, or a pattern of arranging linear holes. In this embodiment, contact hole 26b has a linear shape along the longitudinal direction of channel 25.

[0046] The upper electrode 29 is disposed on the interlayer insulating film 28. The upper electrode 29 is electrically connected to the source region 22 and the contact region 23 through the contact hole 26b. In this embodiment, the upper electrode 29 corresponds to the first electrode.

[0047] In this embodiment, the upper electrode 29 is made of various metals such as Ni and Al. A portion of the various metals that contacts the portion forming n-type SiC (i.e., the source region 22) is made of a metal capable of making ohmic contact with n-type SiC. Furthermore, at least a portion of the various metals that contacts the portion forming p-type SiC (i.e., the substrate layer 21) is made of a metal capable of making ohmic contact with p-type SiC.

[0048] The lower electrode 30 is arranged adjacent to the second surface 10b of the semiconductor substrate 10. The lower electrode 30 is electrically connected to the substrate 11. In this embodiment, the lower electrode 30 corresponds to the second electrode.

[0049] In the SiC semiconductor device of this embodiment, this structure forms an n-channel reverse-channel gate MOSFET. In this embodiment, n-type, n... + type and n - Type corresponds to the first conductivity type, p-type and p-type. + The type corresponds to the second conductivity type.

[0050] In such a SiC semiconductor device, as will be described in detail later, when the gate voltage applied to the gate electrode 27 is equal to or higher than the threshold voltage of the insulated gate structure, a current is induced between the upper electrode 29 and the lower electrode 30, causing the SiC semiconductor device to be in a conducting state. Furthermore, when the gate voltage applied to the gate electrode 27 is lower than the threshold voltage, the current between the upper electrode 29 and the lower electrode 30 is interrupted, causing the SiC semiconductor device to be in a disconnected state.

[0051] Next, we will refer to Figure 2 This embodiment describes the concentration profile of the first deep layer 15 along the Z-axis (i.e., the depth direction). Hereinafter, the interface between the first deep layer 15 and the current spreading layer 17 will also be simply referred to as the interface. Furthermore, in the semiconductor substrate 10, the location of the interface is defined as a first location P1. In other words, the interface between the first deep layer 15 and the current spreading layer 17 can be considered the portion of the first deep layer 15 closest to the substrate layer 21.

[0052] First, such as Figure 2 As shown, the first deep layer 15 has a concentration profile including a high-concentration region 15a with a high-concentration peak. The high-concentration region 15a has a maximum concentration on the side adjacent to the interface and near the first location P1, and has an impurity concentration that does not lead to depletion in the disconnected state. Furthermore, the first deep layer 15 has a concentration profile including a low-concentration region 15b on the side adjacent to the substrate 11 compared to the high-concentration region 15a. The impurity concentration gradient along the Z-axis in the low-concentration region 15b is less than a predetermined value, and it is depleted in the disconnected state. In other words, the first deep layer 15 has a concentration profile with a low-concentration region 15b on the side adjacent to the substrate 11 compared to the high-concentration region 15a, wherein the low-concentration region 15b includes a region where the impurity concentration does not substantially change along the Z-axis, and it is depleted in the disconnected state. Note that although a portion of the first deep layer 15 near the substrate 11 has a large gradient in impurity concentration, this portion is included in the low-concentration region 15b upon depletion.

[0053] The high-concentration peak has an impurity concentration higher than the maximum impurity concentration of the current spreading layer 17. The impurity concentration of the high-concentration peak is, for example, 1.0 x 10⁻⁶. 18 / cm 3 Or higher. For example, the current spreading layer 17 is configured such that the maximum impurity concentration is approximately 3.0 x 10⁻⁶. 17 / cm 3 In the low-concentration region 15b, the impurity concentration in the region where the gradient of impurity concentration along the Z-axis is less than a predetermined value (i.e., the region where the impurity concentration is essentially constant) is approximately the same as the maximum impurity concentration in the current-spreading layer 17, and is, for example, about 3.0 x 10⁻⁶. 17 / cm 3 .

[0054] In the semiconductor substrate 10, as described above, the location (i.e., depth) of the interface is defined as a first location P1. Furthermore, in the semiconductor substrate 10, the location of the high concentration peak is defined as a second location P2, and the location closest to the substrate layer 21 in the low concentration region 15b is defined as a third location P3. In other words, the third location P3 can be considered the boundary between the high concentration region 15a and the low concentration region 15b, or the location where the impurity concentration increases sharply from the low concentration region 15b to the high concentration peak. Furthermore, the third location P3 can also be considered the intersection between a region where the impurity concentration gradient is equal to or greater than a predetermined value and a region where the gradient is less than a predetermined value. Moreover, it can be said that the first deep layer 15 is formed with a concentration profile having a high concentration region 15a between the first location P1 and the third location P3, and a low concentration region 15b in the portion closer to the substrate 11 than the third location P1.

[0055] In this embodiment, the first length L1 between the first position P1 and the second position P2 is shorter than the second length L2 between the second position P2 and the third position P3. In other words, since the high concentration region 15a is located between the first position P1 and the third position P3, in the Z-axis direction, the second position P2 is closer to the first position P1 than the center of the high concentration region 15a.

[0056] The structure of the SiC semiconductor device in this embodiment is as described above. Next, the operation and beneficial effects of the SiC semiconductor device will be described.

[0057] First, in the off-state of the SiC semiconductor device before a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode 27, no reverse layer is formed in the substrate layer 21. Therefore, even if a positive voltage of, for example, 1600V is applied to the lower electrode 30, electrons will not flow from the source region 22 into the substrate layer 21. Thus, the SiC semiconductor device is in the off-state, and current does not flow between the upper electrode 29 and the lower electrode 30.

[0058] When the SiC semiconductor device is in the off state, an electric field is applied between the drain and the gate, and the electric field concentration can occur at the bottom of the gate insulating film 26. However, in the SiC semiconductor device described above, the first deep layer 15 and the JFET portion 14 are located deeper than the channel 25. Furthermore, the impurity concentration of the first deep layer 15 prevents the high concentration peak from being depleted. Therefore, the depletion layer formed between the first deep layer 15 and the JFET portion 14 suppresses the rise of the equipotential line due to the influence of the drain voltage and makes it difficult for the high electric field to penetrate the gate insulating film 26. Therefore, in this embodiment, damage to the gate insulating film 26 can be suppressed.

[0059] The low-concentration region 15b in the first deep layer 15 has an impurity concentration that can lead to depletion. Therefore, when the SiC semiconductor device is in the off state, the portion of the first deep layer 15 including the low-concentration region 15b is also depleted. Thus, the reduction in the breakdown voltage of the SiC semiconductor device due to the formation of the first deep layer 15 can be suppressed.

[0060] In this embodiment, the first length L1 is less than the second length L2. Therefore, compared to a SiC semiconductor device with the same breakdown voltage where the first length L1 is equal to or greater than the second length L2, the length of the first deep layer 15 in the Z-axis direction can be reduced. Thus, the increase in the size of the SiC semiconductor device in the Z-axis direction can be suppressed.

[0061] When a gate voltage (e.g., 20V) higher than the threshold voltage is applied to the gate electrode 27, a reverse layer is formed on the surface of the substrate layer 21 in contact with the channel 25. Therefore, a current is induced between the upper electrode 29 and the lower electrode 30, and the SiC semiconductor device enters a conducting state. In this embodiment, since electrons that have passed through the reverse layer flow to the substrate 11 via the current spreading layer 17, the JFET portion 14, and the low-concentration layer 13, the drift layer 19 can be configured to include the current spreading layer 17, the JFET portion 14, and the low-concentration layer 13.

[0062] Next, we will refer to Figures 3A to 3F A method for manufacturing a SiC semiconductor device according to this embodiment is described. Figures 3A to 3F It is a cross-sectional view defined along the XZ plane, that is, having a cross-sectional view along the XZ plane. Figure 1 A cross-sectional view of the Y-axis direction.

[0063] First, such as Figure 3A As shown, a constituent substrate 100 is fabricated having a buffer layer 12, a low-concentration layer 13, and a JFET portion 14 on the surface of a substrate 11. The buffer layer 12, the low-concentration layer 13, and the JFET portion 14 are made of SiC. In other words, a constituent substrate 100 including a portion of a drift layer 19 on the substrate 11 side is fabricated.

[0064] Next, as Figure 3B As shown, a first deep layer 15 is formed by performing ion implantation of p-type impurities on a constituent substrate 100 using a mask (not shown). Specifically, a layer with p-type impurities is formed by performing ion implantation multiple times while varying the acceleration energy. Figure 2 The first deep layer 15 of the concentration curve shown. That is, a first deep layer 15 is formed having a concentration curve including a high concentration region 15a and a low concentration region 15b, wherein the first length L1 is shorter than the second length L2.

[0065] Next, as Figure 3CAs shown, a constituent layer 17a for forming a current spreading layer 17, etc., is epitaxially grown on the JFET portion 14 and the first deep layer 15 to form a semiconductor substrate 10. By arranging the constituent layer 17a after the formation of the first deep layer 15 in this manner, the constituent layer 17a (i.e., the current spreading layer 17) can be protected from the influence of p-type impurities in the first deep layer 15. Therefore, the decrease in the effective concentration of the current spreading layer 17a can be suppressed during the formation of the current spreading layer 17, thereby suppressing the increase in on-resistance.

[0066] Next, as Figure 3D As shown, the current spreading layer 17 is formed by performing ion implantation of n-type impurities using a mask (not shown) on the constituent layer 17a. Therefore, the drift layer 19 is formed. That is, the impurity concentration at the interface with the first deep layer 15 is adjusted. Furthermore, the second deep layer 18 is formed by performing ion implantation of p-type impurities using a mask (not shown) on the constituent layer 17a.

[0067] Next, as Figure 3E As shown, the substrate 21, source region 22 and contact region 23 are all formed by appropriately implanting impurity ions again into the constituent layer 17a using a mask (not shown).

[0068] After that, as Figure 3F As shown, the channel gate structure, interlayer insulating film 28, upper electrode 29, lower electrode 30, etc., are all formed by performing a predetermined semiconductor manufacturing process, although detailed descriptions of these processes are omitted. Thus, the SiC semiconductor device of this embodiment is produced.

[0069] In the above embodiment, the first deep layer 15 has a concentration profile including a high-concentration region 15a and a low-concentration region 15b. The high-concentration region has a high-concentration peak, and its impurity concentration does not lead to depletion in the off-state, while the impurity concentration in the low-concentration region leads to depletion in the off-state. As a result, the breakdown of the gate insulating film 26 can be suppressed while suppressing the decrease in breakdown voltage. Furthermore, the first deep layer 15 is formed such that the first length L1 is shorter than the second length L2. Therefore, compared to the case where the first length L1 is equal to or greater than the second length L2 in a SiC semiconductor device with the same breakdown voltage, the length of the first deep layer 15 in the Z-axis direction can be shortened. Therefore, the increase in the size of the SiC semiconductor device in the Z-axis direction can be suppressed.

[0070] In this embodiment, the semiconductor substrate 10 is formed by arranging the constituent layer 17a on the constituent substrate 100 after forming the first deep layer 15 in the constituent substrate 100. Therefore, the influence of p-type impurities forming the first deep layer 15 on the constituent layer 17a (i.e., the current spreading layer 17) can be suppressed. Therefore, when the current spreading layer 17 is formed, the decrease in the effective concentration of the current spreading layer 17 can be suppressed, and the increase in on-resistance can be suppressed.

[0071] (Modification of the first embodiment)

[0072] The following describes a modification of the first embodiment. In the first embodiment described above, as long as the first depth layer 15 has a concentration curve with a first length L1 less than a second length L2, the specific shape of the concentration curve can be appropriately modified. For example, as... Figure 4A As shown, the first depth layer 15 can have a concentration curve, where the second position P2 coincides with the first position P1, and the first length L1 is 0. As another example, such as... Figure 4B As shown, the first deep layer 15 may have a concentration curve with a step C between the second position P2 and the first position P1.

[0073] (Other embodiments)

[0074] Although this disclosure has been described with reference to embodiments, it is to be understood that this disclosure is not limited to these embodiments or structures. This disclosure includes various modifications and variations within the equivalent scope. Furthermore, various combinations or forms, as well as other combinations or forms comprising only one element, one or more elements, or one or fewer elements, fall within the scope or spirit of this disclosure.

[0075] For example, in the first embodiment described above, an n-channel MOSFET with a channel gate structure is described as an example of a semiconductor switching element, where n-type is the first conductivity type and p-type is the second conductivity type. However, this configuration is merely an example; another type of semiconductor switching element, such as a p-channel MOSFET with a channel gate structure, where the conductivity type of each element is opposite to that of the n-channel type, is also applicable. Furthermore, in addition to MOSFETs, semiconductor devices can be formed from IGBTs with similar structures. In the case of IGBTs, besides the n-channel MOSFET in the first embodiment… + Type substrate 11 is p + Aside from replacing the collector layer, the configuration is similar to that of the MOSFET in the first embodiment.

[0076] Furthermore, in the first embodiment described above, the semiconductor substrate 10 is exemplary made of SiC. However, the semiconductor substrate 10 can be configured using a silicon substrate, other compound semiconductor substrates, etc.

[0077] Furthermore, although, as an example, the first deep layer 15 extends along the X-axis direction in the first embodiment, the first deep layer 15 may extend along the Y-axis direction.

[0078] In the first embodiment described above, the current spreading layer 17 is formed by exemplarily performing ion implantation after the formation of the constituent layer 17a. However, when the constituent layer 17a is arranged by epitaxial growth, the current spreading layer 17 can be formed by arranging the constituent layer 17a while adjusting the impurity concentration. That is, instead of ion implantation, the current spreading layer 17 can be formed simultaneously with the step of arranging the constituent layer 17a.

[0079] Furthermore, in the first embodiment described above, the semiconductor substrate 10 can be formed by arranging the constituent layer 17a before forming the first deep layer 15, and then the first deep layer 15 can be formed by ion implantation of the semiconductor substrate 10.

Claims

1. A method for manufacturing a semiconductor device, the semiconductor device comprising: Drift layer of the first conductivity type; A second type of conductive substrate layer is disposed on the surface portion of the drift layer; The first type of conductivity impurity region is disposed on the surface portion of the substrate layer, and the impurity concentration of the impurity region is higher than that of the drift layer; A channel gate structure includes a gate insulating film disposed on the wall of a channel and a gate electrode disposed on the gate insulating film, wherein the channel penetrates the substrate layer and the impurity region and reaches the drift layer; The first deep layer of the second conductivity type is disposed below the channel in the drift layer and is separated from the channel; A second deep layer of the second conductivity type, which connects the base layer and the first deep layer; A high-concentration layer of the first conductivity type or the second conductivity type is disposed opposite to the substrate layer relative to the drift layer, and the high-concentration layer has a higher impurity concentration than the drift layer; A first electrode is electrically connected to the substrate layer and the impurity region; and The second electrode is electrically connected to the high-concentration layer, wherein The semiconductor device is configured to be in a conducting state when a gate voltage equal to or higher than a predetermined voltage is applied to the gate electrode, thereby generating a current between the first electrode and the second electrode; and the semiconductor device is configured to be in a disconnected state when a gate voltage lower than the predetermined voltage is applied to the gate electrode. The first deep layer has high-concentration and low-concentration regions in the impurity concentration curve along the depth direction, which corresponds to the stacking direction of the drift layer and the substrate layer. The high-concentration region has a high-concentration peak with the highest impurity concentration, and includes a region that is not depleted in the disconnected state. The low-concentration region is located adjacent to the high-concentration layer compared to the high-concentration region, and has a region where the gradient of the impurity concentration change is less than a predetermined value, and is depleted in the disconnected state. The position closest to the basal layer in the first deep layer is called the first position, the position of the high concentration peak is called the second position, and the position closest to the basal layer in the low concentration region is called the third position. The high concentration region is located between the first position and the third position. The first length between the first position and the second position is shorter than the second length between the second position and the third position. The method for manufacturing the semiconductor device includes: Prepare a substrate comprising a portion of the drift layer adjacent to the high-concentration layer; The first deep layer is formed by performing ion implantation on the constituent substrate; The drift layer is formed by epitaxially growing a constituent layer on the first deep layer.

2. The method according to claim 1, wherein The formation of the drift layer includes adjusting the impurity concentration of a portion of the interface between the drift layer and the first deep layer by performing ion implantation on the constituent layer.

3. The method according to claim 1, wherein The formation of the drift layer includes adjusting the impurity concentration of a portion of the interface between the constituent layer and the first deep layer during the epitaxial growth of the constituent layer.

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