A semiconductor device and a manufacturing method thereof

Abstract

The application discloses a semiconductor device and a manufacturing method thereof. The doping concentration of a P column of an epitaxial layer of the semiconductor device near a substrate part is greater than the doping concentration of an N column. Thus, under high-temperature processes such as annealing and oxidation, part of impurities in the substrate diffuse to the P column at the bottom of the N column region epitaxial layer, and the doping concentration of the P column is equivalent to the doping concentration of the N column, so that the positive carriers and the negative carriers of the P column and the N column are as possible as possible to be exhausted to each other at the bottom of the epitaxial layer, and the performance of the semiconductor device is further improved.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more particularly to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] The key design feature of traditional superjunction VDMOS devices is the alternating arrangement of N (negative) pillars and P (positive) pillars, which have the same lateral width and doping concentration, satisfying the charge balance condition (Qn = Qp).

[0003] In the off-state of a superjunction VDMOS device, the positive carriers and load carriers of the P-pillar and N-pillar deplete each other, which reduces the carrier concentration in the drain region of the superjunction VDMOS device, increases the resistance, and increases the breakdown voltage capability of the device in the off-state.

[0004] However, during the manufacturing process of superjunction VDMOS devices, heating processes such as annealing and oxidation are performed. During heating, impurities in the highly doped substrate region diffuse upwards, increasing the impurity concentration of the N pillars, thus preventing the drain from being completely depleted. Summary of the Invention

[0005] In response to the aforementioned technical problems, the applicant has creatively provided a semiconductor device and a method for manufacturing the same.

[0006] According to a first aspect of the present application, a semiconductor device is provided, the semiconductor device including a substrate, an epitaxial layer, and N-pillars and P-pillars alternately arranged within the epitaxial layer, wherein the epitaxial layer includes a first epitaxial layer and a second epitaxial layer, the second epitaxial layer being located below the first epitaxial layer and adjacent to the substrate; within the first epitaxial layer, the doping concentration of the P-pillars is equal to the doping concentration of the N-pillars; within the second epitaxial layer, the doping concentration of the P-pillars is greater than the doping concentration of the N-pillars.

[0007] According to one embodiment of this application, the P-pillar includes a first P-pillar located in a first epitaxial layer and a second P-pillar located in a second epitaxial layer; the doping concentration of the second P-pillar is greater than the doping concentration of the first P-pillar.

[0008] According to one embodiment of this application, the doping concentration includes the doping concentration using impurity boron.

[0009] According to one embodiment of this application, the N-pillar includes a first N-pillar located in a first epitaxial layer and a second N-pillar located in a second epitaxial layer; the doping concentration of the second N-pillar is less than that of the first N-pillar.

[0010] According to one embodiment of this application, the thickness of the second epitaxial layer is 10% to 15% of the epitaxial layer thickness.

[0011] According to one embodiment of this application, in the second epitaxial layer, the doping concentration of the P pillars is 100 times that of the N pillars.

[0012] According to one embodiment of this application, the semiconductor device is a superjunction VDMOS device.

[0013] According to a second aspect of the present application, a method for manufacturing a semiconductor device is provided. The method includes: forming a second epitaxial layer on a substrate, the doping concentration of the second epitaxial layer being a first doping concentration; etching grooves on the second epitaxial layer to obtain a second P-groove; implanting a P-pillar material with a second doping concentration into the second P-groove to obtain a second P-pillar; forming a first epitaxial layer on the second epitaxial layer, the doping concentration of the first epitaxial layer being the same as the doping concentration of the second epitaxial layer; etching grooves on the first epitaxial layer to obtain a first P-groove; and implanting a P-pillar material with a first doping concentration into the first P-groove to obtain a first P-pillar; wherein the first doping concentration is less than the second doping concentration.

[0014] According to one embodiment of this application, injecting a second P-pillar material with a second doping concentration into a second P-groove to obtain a second P-pillar includes: injecting gaseous P-pillar material into the second P-groove using a chemical vapor deposition process, and adjusting the gas flow rate of the P-pillar material and / or adjusting the rate of the doping gas flow to make the P-pillar material reach a second doping concentration.

[0015] According to a third aspect of the present application, a method for manufacturing a semiconductor device is provided. The method includes: forming a second epitaxial layer on a substrate, such that the doping concentration of the second epitaxial layer reaches a fourth doping concentration; forming a first epitaxial layer on the second epitaxial layer, such that the doping concentration of the first epitaxial layer reaches a third doping concentration; grooving a groove from the first epitaxial layer, passing through the first epitaxial layer and entering the second epitaxial layer to obtain a P-groove; and injecting a P-pillar material with a third doping concentration into the P-groove to obtain a P-pillar; wherein the third doping concentration is greater than the fourth doping concentration.

[0016] This application discloses a semiconductor device and its manufacturing method, wherein the doping concentration of the P-pillars near the substrate in the epitaxial layer of the semiconductor device is greater than that of the N-pillars. Thus, during high-temperature processes such as annealing and oxidation, some impurities in the substrate diffuse into the N-pillar region, making the doping concentration of the P-pillars at the bottom of the epitaxial layer comparable to that of the N-pillars. This allows the positive carriers and loaded carriers of the P-pillars and N-pillars to deplete each other as much as possible, thereby further improving the performance of the semiconductor device.

[0017] It should be understood that the implementation of the embodiments of this application does not need to achieve all the above-mentioned beneficial effects, but a specific technical solution can achieve a specific technical effect, and other implementation methods of the embodiments of this application can also achieve beneficial effects not mentioned above. Attached Figure Description

[0018] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, in which:

[0019] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0020] Figure 1 This diagram shows a cross-sectional view of a superjunction VDMOS device in the prior art.

[0021] Figure 2 A schematic cross-sectional view of the structure of an embodiment of the semiconductor device of this application is shown;

[0022] Figure 3 A schematic cross-sectional view of another embodiment of the semiconductor device of this application is shown;

[0023] Figure 4 An embodiment of the present application is shown. Figure 2 A schematic diagram of the manufacturing process of the semiconductor device shown.

[0024] Figure 5 This application shows Figure 2 One of the schematic cross-sectional views of the structure at a certain stage in the manufacturing process of the semiconductor device shown;

[0025] Figure 6 This application shows Figure 2 The second schematic diagram of the structural cross-section of a certain stage in the manufacturing process of the semiconductor device shown;

[0026] Figure 7 Another embodiment of the manufacturing process described in this application is shown. Figure 3 A schematic diagram of the manufacturing process of the semiconductor device shown.

[0027] Figure 8 This application shows Figure 3 One of the schematic cross-sectional views of the structure at a certain stage in the manufacturing process of the semiconductor device shown;

[0028] Figure 9 This application shows Figure 3 The second schematic diagram of the structural cross-section of a certain stage in the manufacturing process of the semiconductor device shown;

[0029] Figure 10 This application shows Figure 3 The third schematic diagram of the structural cross-section of a certain stage in the manufacturing process of the semiconductor device shown.

[0030] Attachment part number explanation:

[0031] 101 – Substrate;

[0032] 102 – Epitaxial layer;

[0033] 103–P column;

[0034] 104 – Source;

[0035] 105–N column;

[0036] 106 – Gate.

[0037] 201 – Substrate;

[0038] 202 – Epitaxial layer;

[0039] 2021 – First epitaxial layer;

[0040] 2022 – Second epitaxial layer;

[0041] 203–P column;

[0042] 2031 – First P-column;

[0043] 2032 – Second P-column;

[0044] 204 – First electrode;

[0045] 205–N column;

[0046] 206 – Second electrode;

[0047] 301 – Substrate;

[0048] 302 – Epitaxial layer;

[0049] 3021 – First epitaxial layer;

[0050] 3022 – Second epitaxial layer;

[0051] 303–P column;

[0052] 304 – Source;

[0053] 305–N column;

[0054] 3051 – First N-pillar;

[0055] 3052 – Second N-pillar;

[0056] 306 – Gate. Detailed Implementation

[0057] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0058] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0059] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0060] To describe the three-dimensional structure of semiconductor devices from multiple perspectives, this application refers to the structural schematic diagram obtained by vertically cutting the semiconductor device as a structural cross-sectional schematic diagram. The structural schematic diagram obtained by horizontally cutting the semiconductor device is referred to as a structural section schematic diagram.

[0061] Figure 1 The structure of a conventional superjunction VDMOS device is shown. For example... Figure 1 As shown, the superjunction VDMOS device structure includes a substrate 101 and an epitaxial layer 102, in which alternating P-pillars 103 and N-pillars 105 are disposed. The P-pillars 103 are connected to the source 104, and the N-pillars 105 are connected to the gate 106. The P-pillars 103 and N-pillars 105 have the same lateral width and doping concentration, but the doped impurities can be different.

[0062] In the off state, the positive carriers and load carriers of the P-pillar 103 and N-pillar 105 of the superjunction VDMOS device are mutually depleted, resulting in extremely low drain carrier concentration, increased resistance, and improved breakdown voltage.

[0063] However, as high-temperature processes such as annealing and oxidation proceed, impurities in the substrate 101 region diffuse upwards, increasing the impurity concentration in the N-pillar 105, thus preventing complete depletion of the drain. Consequently, the effective depth of the P-pillar 103 is often lower than the design depth, reducing the depletion region length and lowering the breakdown voltage, thereby affecting the performance of the superjunction VDMOS device. Increasing the depth of the P-pillar 103 would increase the device height, which is not conducive to meeting miniaturization requirements.

[0064] Therefore, this application provides a semiconductor device and a method for manufacturing the same.

[0065] Figure 2 A schematic cross-sectional view of an embodiment of the semiconductor device of this application is shown. Figure 2 As shown, the semiconductor device includes a substrate 201, an epitaxial layer 202, and N-pillars 205 and P-pillars 203 arranged alternately within the epitaxial layer 202.

[0066] The epitaxial layer 202 includes a first epitaxial layer 2021 and a second epitaxial layer 2022, with the second epitaxial layer 2022 located below the first epitaxial layer 2021 and adjacent to the substrate 201. The P-pillars 203 include a first P-pillar 2031 located in the first epitaxial layer 2021 and a second P-pillar 2032 located within the second epitaxial layer 2022. Within the first epitaxial layer 2021, the doping concentration of the first P-pillar 2031 is equal to the doping concentration of the N-pillar 205. Within the second epitaxial layer 2022, the doping concentration of the second P-pillar 2032 is greater than the doping concentration of the first P-pillar 2031, thereby making the doping concentration of the second P-pillar 2032 greater than that of the N-pillar 205.

[0067] In this embodiment, substrate 201 is a substrate in a broad sense, referring to the substrate on which the epitaxial layer 202 is deposited, as well as the components and circuits already on the substrate. Substrate 201 has a high concentration of doped impurities, which diffuse upwards during high-temperature processes such as annealing and oxidation.

[0068] Epitaxial layer 202 is a dielectric layer deposited on substrate 201, used to alternately arrange N-pillars 205 and P-pillars 203. Typically, epitaxial layer 202 and N-pillars 205 are made of the same material.

[0069] The first epitaxial layer 2021 and the second epitaxial layer 2022 are formed in two separate steps, typically using the same material. In this embodiment, the doping concentrations of the first epitaxial layer 2021 and the second epitaxial layer 2022 are also the same.

[0070] N-pillars 205 in epitaxial layer 202 are connected to the first electrode 206. P-pillars 203 in epitaxial layer 202 are connected to the second electrode 204. Both N-pillars 205 and P-pillars 203 are formed by doping impurities with specific semiconductor materials. For example, P-pillars 203 are typically formed by doping pure silicon crystal with a trivalent element (e.g., boron). Doping concentration refers to the proportion of the doped impurity to the total mass of the dopant.

[0071] In this embodiment, the portion of the P-pillar 203 closest to the substrate 201, i.e., the second P-pillar 2032 in the second epitaxial layer 2022, has a higher doping concentration than the portion of the N-pillar 205 in the second epitaxial layer 2022. Thus, when high-temperature processes such as annealing and oxidation cause some impurities in the substrate 201 to diffuse into the N-pillar region, the doping concentration of the second P-pillar 2032 becomes comparable to that of the N-pillar 205. This results in more positive carriers and loaded carriers in both the P-pillars and N-pillars mutually depleting each other, reducing the carrier concentration in the drain region, increasing the resistance, and increasing the breakdown voltage in the off-state. Even without increasing the length of the P-pillars, the performance of the semiconductor device can be further improved.

[0072] Ideally, the doping concentration of the second P-pillar can be the same as the N-type impurity concentration formed by thermal diffusion from the highly doped substrate 201 after heat treatment of the second epitaxial layer 2022. The N-type impurity concentration formed after thermal diffusion from the highly doped substrate 201 mainly depends on factors such as the doping concentration of the highly doped substrate 201, the N-pillar 203 before heat treatment, and the temperature and duration of the heat treatment process. This ensures that the positive carriers and loaded carriers of the P-pillars and N-pillars are completely depleted, resulting in optimal semiconductor device performance. In one embodiment of this application, the inventors discovered through experiments that when the thickness of the second epitaxial layer 2022 is 10% to 15% of the thickness of the epitaxial layer 202, the impurities diffused upwards from the substrate 201 during the manufacturing process can be essentially controlled within the second epitaxial layer. Therefore, in this embodiment, the thickness of the second epitaxial layer 2022 is designed to be 10% to 15% of the thickness of the epitaxial layer 202.

[0073] In other embodiments of this application, the ratio of the thickness of the second epitaxial layer 2022 to the thickness of the first epitaxial layer 2021 may also be different. The implementer may determine this ratio based on specific implementation requirements and conditions, as well as the extent of upward diffusion of impurities in the substrate 201.

[0074] In one embodiment of this application, the inventors have experimentally discovered that within the second epitaxial layer, when the doping concentration of the second P-pillar 2032 is 100 times that of the N-pillar 203, the positive carriers and loaded carriers of the P-pillar 2032 and N-pillar 203 can mutually deplete each other. Therefore, in this embodiment, the doping concentration of the second P-pillar 2032 is designed to be 100 times that of the N-pillar 203. In other embodiments of this application, the ratio of the doping concentration of the second P-pillar 2032 to that of the N-pillar 203 may also differ, particularly influenced by factors such as the doping concentration of the substrate 201 and the temperature and duration of the heat treatment process. Implementers can determine this ratio based on specific implementation requirements, implementation conditions, and experimental results.

[0075] exist Figure 2 In the illustrated embodiment, four P-pillars and three N-pillars are shown. This is merely an illustrative example and not a limitation on the embodiments of this application. In practical applications, the number of P-pillars or N-pillars in the embodiments of this application is not limited, as long as the P-pillars and N-pillars are arranged alternately.

[0076] Figure 3 Another embodiment of the semiconductor integrated device of this application is shown. For example... Figure 3 The semiconductor device includes a substrate 301, an epitaxial layer 302, and N-pillars 305 and P-pillars 203 arranged alternately within the epitaxial layer 302.

[0077] The epitaxial layer 302 includes a first epitaxial layer 3021 and a second epitaxial layer 3022, with the second epitaxial layer 3022 located below the first epitaxial layer 3021 and adjacent to the substrate 301. The N-pillars 305 include a first N-pillar 3051 located in the first epitaxial layer and a second N-pillar 3052 located within the second epitaxial layer. Within the first epitaxial layer 3021, the doping concentration of the first N-pillar 3051 is equal to the doping concentration of the P-pillar 303. Within the second epitaxial layer 3022, the doping concentration of the second N-pillar 3052 is less than the doping concentration of the first N-pillar 3051, thereby making the doping concentration of the second N-pillar 3052 less than the doping concentration of the P-pillar 303.

[0078] In this embodiment, substrate 301 is a substrate in a broad sense, referring to the substrate on which the epitaxial layer 302 is deposited, as well as the components and circuits already on the substrate. Substrate 301 has a high concentration of doped impurities, which diffuse upwards during high-temperature processes such as annealing and oxidation.

[0079] Epitaxial layer 302 is a dielectric layer deposited on substrate 301, used to alternately arrange N-pillars 305 and P-pillars 303. Typically, epitaxial layer 302 and N-pillars 305 are made of the same material.

[0080] The first epitaxial layer 3021 and the second epitaxial layer 3022 are formed in two separate steps, typically using the same material. In this embodiment, the doping concentrations of the first epitaxial layer 3021 and the second epitaxial layer 3022 are different, with the doping concentration of the first epitaxial layer 3021 being greater than that of the second epitaxial layer 3022.

[0081] In the epitaxial layer 302, the N-pillar 305 is connected to the gate 306. The P-pillar 303 in the epitaxial layer 302 is connected to the source 304. Both the N-pillar 305 and the P-pillar 303 are formed by doping with impurities and specific semiconductor materials.

[0082] In this embodiment, the portion of N-pillar 305 closest to substrate 301, i.e., the second N-pillar 3052 in the second epitaxial layer 3022, has a lower doping concentration than P-pillar 303. Thus, when high-temperature processes such as annealing and oxidation cause some impurities in substrate 301 to diffuse into the N-pillar region of the second epitaxial layer 3022, the doping concentration of the second N-pillar 3052 becomes comparable to that of the P-pillar 303. This allows the positive carriers and loaded carriers of P-pillar 303 and N-pillar 305 to deplete each other as much as possible in the second epitaxial layer 3022, thereby reducing the carrier concentration in the drain region of the superjunction VDMOS device, increasing the resistance, and increasing the breakdown voltage in the off-state. Even without increasing the length of the P-pillar, the device performance can be further improved.

[0083] It should be noted that, Figure 2 and Figure 3 The semiconductor devices shown are for illustrative purposes only and are not intended to limit the semiconductor devices described in this application. In practical applications, the semiconductor devices described in this application can be any superjunction semiconductor device that includes P-pillars and N-pillars and has the above-described structural features.

[0084] Furthermore, this application also provides a method for manufacturing a semiconductor device, which can be used to manufacture... Figure 2 The semiconductor device shown. (As shown) Figure 4 As shown, the manufacturing method includes:

[0085] In step S410, a second epitaxial layer 2022 is formed on the substrate 201, and the doping concentration of the second epitaxial layer is the same as the first doping concentration.

[0086] In one embodiment of this application, the second epitaxial layer is an N-type epitaxial layer.

[0087] Forming a second epitaxial layer 2022 on substrate 201 can be achieved by:

[0088] 1) Obtain substrate 201, and grow a second epitaxial layer 2022 on substrate 201; or,

[0089] 2) This can be achieved by directly obtaining an epitaxial wafer with an existing epitaxial layer 2022 on the substrate 201.

[0090] The thickness of the second epitaxial layer 2022 can be determined based on the substrate doping concentration and the time and temperature of the heating process. It is generally set to the thickness to which substrate impurities can diffuse during the heating process.

[0091] In one embodiment of this application, the inventors discovered that substrate impurities can diffuse to a thickness of 10% to 15% of the thickness of the epitaxial layer 202 during the heating process. For example, the thickness of a 650V superjunction device is about 10 μm.

[0092] In one embodiment of this application, the second epitaxial layer 2022 is an N-type impurity (phosphorus) doped material.

[0093] In step S420, grooves are etched on the second epitaxial layer 2022 to obtain the second P-groove.

[0094] When creating grooves, any applicable etching method can be used, such as wet etching, dry etching, or photolithography.

[0095] Step S430: P-pillar material with a second doping concentration is injected into the second P-groove to obtain the second P-pillar 2032, as shown below. Figure 5 As shown.

[0096] The second doping concentration is greater than the doping concentration of the second epitaxial layer 2022. The specific value is mainly determined by the N-type impurity concentration formed by thermal diffusion of the highly doped substrate 201 after the second epitaxial layer 2022 undergoes thermal treatment.

[0097] In one embodiment of this application, the doping concentration of the highly doped substrate 201 arsenic is 1×10⁻⁶. 19 cm -3 The doping concentration of phosphorus in the second epitaxial layer is 5 × 10⁻⁶. 15 cm -3 Experiments have shown that after heat treatment, the N-type impurity concentration formed by thermal diffusion from the highly doped substrate 201 in the second epitaxial layer 2022 is approximately 100 times the original doping concentration of the second epitaxial layer 2022 before heating, specifically 1 × 10⁻⁶. 17 cm -3 Therefore, 1×10 17 cm -3 As the second doping concentration.

[0098] In actual production, implementers can adjust and experiment based on the above doping concentration according to specific implementation conditions, such as the substrate concentration, heat treatment temperature, heat treatment time, etc., to determine the appropriate second doping concentration.

[0099] Any applicable process can be used to inject P-pillar material with a second doping concentration into the second P-groove.

[0100] In one embodiment of this application, the doping is mainly carried out by the following method: gaseous P-pillar material is injected into the second P-groove using a chemical vapor deposition process, while triethyl borate gas is introduced, and the second doping concentration is reached by adjusting the gas flow rate of the gaseous P-pillar material and / or adjusting the doping rate of the triethyl borate gas.

[0101] In step S440, a first epitaxial layer 2021 is formed on the second epitaxial layer 2022, and the doping concentration of the first epitaxial layer is the same as that of the second epitaxial layer.

[0102] When forming the first epitaxial layer 2021 on the second epitaxial layer 2022, any applicable epitaxial growth process can be used to grow the epitaxial layer to the designed thickness.

[0103] In step S450, grooves are etched on the first epitaxial layer 2021 to obtain the first P-groove.

[0104] In one embodiment of this application, a dry etching technique is used to etch a deep trench in the first epitaxial layer 2021.

[0105] Step S460: P-pillar material with a first doping concentration is injected into the first P-groove to obtain the first P-pillar 2031. The first doping concentration is less than the second doping concentration.

[0106] In one embodiment of this application, a P-type epitaxial layer is grown using chemical vapor deposition to form a P-pillar, the doping concentration of which is the same as that of the first epitaxial layer 2021.

[0107] Afterwards, following standard semiconductor device flow charts, the subsequent process steps are completed to obtain... Figure 2 The semiconductor device shown.

[0108] It should be noted that, Figure 4 The steps shown above are only the main steps in manufacturing the semiconductor device according to the embodiments of this application, and not all steps. In the process of manufacturing the semiconductor device, other steps may also be included, depending on the product design of the semiconductor device, such as grinding and removing top coatings, depositing an oxygen storage layer, depositing a dielectric layer, wiring, and soldering.

[0109] This application also provides a method for manufacturing a semiconductor device, which can be used to manufacture... Figure 3 The semiconductor device shown. (As shown) Figure 7 As shown, the manufacturing method includes:

[0110] In step S710, a second epitaxial layer 3022 is formed on the substrate 301, and the doping concentration of the second epitaxial layer 3022 reaches the fourth doping concentration, resulting in the following... Figure 8 The structure shown.

[0111] The formation of the second epitaxial layer 3022 on the substrate 301 can be achieved using any applicable epitaxial growth process.

[0112] In one embodiment of this application, the doping concentration of the second epitaxial layer 3022 is controlled by controlling the flow rate of triethyl phosphate or phosphine gas introduced during the deposition of the second epitaxial layer 3022, until a fourth doping concentration is reached.

[0113] In this embodiment, the fourth doping concentration is lower than the epitaxial layer doping concentration (i.e., the third doping concentration) of a typical semiconductor device. The value of the fourth doping concentration is mainly determined by factors such as the substrate 301 doping concentration, the third doping concentration, the heat treatment temperature, and the heat treatment time. Specifically, the doping concentration of the second epitaxial layer 3022, i.e., the fourth doping concentration, can be determined by the fact that after the second epitaxial layer 3022 is heated, it absorbs the impurities diffused from the substrate 301 and reaches a doping concentration that is exactly equivalent to that of the first epitaxial layer 3021.

[0114] In this way, the doping concentration of the second epitaxial layer 3022 can be comparable to that of the third epitaxial layer after heating. Since the doping concentration of the P-pillar is the same as that of the first epitaxial layer 3021, the doping concentration of the second epitaxial layer 3022 can be comparable to that of the P-pillar after heating. In the off-state of the superjunction VDMOS device, the positive carriers and load carriers of the P-pillar and N-pillar deplete each other, reducing the carrier concentration in the drain region of the superjunction VDMOS device, increasing the resistance, and increasing the breakdown voltage of the device in the off-state.

[0115] Step S720: A first epitaxial layer 3021 is formed on the second epitaxial layer 302, such that the doping concentration of the first epitaxial layer 3021 reaches a third doping concentration, wherein the third doping concentration is greater than the fourth doping concentration, resulting in the following... Figure 9 The structure shown.

[0116] Step S730: Grooves are etched from the first epitaxial layer 3021, passing through the first epitaxial layer 3021 and entering the second epitaxial layer 3022 to obtain P-grooves.

[0117] Step S740: P-pillar material with a third doping concentration is injected into the P-groove to obtain P-pillar 303, as shown. Figure 10 As shown.

[0118] Afterwards, following the standard manufacturing process for superjunction VDMOS devices, the subsequent process steps are completed to obtain... Figure 3The semiconductor device shown.

[0119] In another embodiment of this application, the process is to manufacture the product by obtaining an epitaxial wafer. Figure 3 The semiconductor device is shown. In this case, since the fourth doping concentration is already determined, the third doping concentration can be increased. The third doping concentration is determined based on the doping concentration of the second epitaxial layer 3022 in the epitaxial wafer after heating, and the first epitaxial layer 3021 and P-pillar are grown using the third doping concentration.

[0120] Specifically, the doping concentration of the first epitaxial layer 3021 can be controlled by controlling the flow rate of triethyl phosphate or phosphine gas introduced during the deposition of the first epitaxial layer 3021, until the third doping concentration is reached; by injecting gaseous P-pillar material into the P-groove using a chemical vapor deposition process, while simultaneously introducing triethyl borate gas, and by adjusting the gas flow rate of the gaseous P-pillar material and / or adjusting the doping rate of the triethyl borate gas, until the third doping concentration is reached.

[0121] It should be noted that, in the above embodiments of the semiconductor devices of this application, including the process of manufacturing each embodiment using the semiconductor device manufacturing method of this application, the materials used for each component are not limited.

[0122] For example, the substrate and N-type epitaxy can both be made of trajectory materials or silicon carbide-based materials, and the doping can be done with N-type donor impurities such as arsenic or phosphorus; the P-pillars can also be made of silicon or silicon carbide, and the doping can be done with P-type donor impurities such as boron or gallium.

[0123] Furthermore, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0124] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another device, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0125] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The semiconductor device is a superjunction VDMOS device, and the manufacturing method includes: A second epitaxial layer is formed on the substrate, and the doping concentration of the second epitaxial layer is the same as that of the first epitaxial layer; the second epitaxial layer is an N-type epitaxial layer. Grooves are etched on the second epitaxial layer to obtain multiple second P-grooves; P-pillar material with a second doping concentration is injected into each of the second P-grooves to obtain spaced-apart second P-pillars; the second epitaxial layer portion between the second P-pillars constitutes the second N-pillar; A first epitaxial layer is formed on top of the second epitaxial layer, and the doping concentration of the first epitaxial layer is the same as that of the second epitaxial layer; the first epitaxial layer is an N-type epitaxial layer; Grooves are etched on the first epitaxial layer to obtain multiple first P-grooves; P-pillar material with the first doping concentration is injected into each of the first P-grooves to obtain spaced-apart first P-pillars; the first epitaxial layer portion between the first P-pillars constitutes the first N-pillar; Wherein, the first doping concentration is less than the second doping concentration.

2. The manufacturing method according to claim 1, characterized in that, The step of injecting P-pillar material with a second doping concentration into the second P-groove to obtain the second P-pillar includes: Gaseous P-pillar material is injected into the second P-groove using a chemical vapor deposition process. By adjusting the gas flow rate of the P-pillar material and / or adjusting the rate of the doping gas flow, the P-pillar material reaches a second doping concentration.

3. A method for manufacturing a semiconductor device, characterized in that, The semiconductor device is a superjunction VDMOS device, and the manufacturing method includes: A second epitaxial layer is formed on the substrate, such that the doping concentration of the second epitaxial layer reaches a fourth doping concentration; the second epitaxial layer is an N-type epitaxial layer; A first epitaxial layer is formed on top of the second epitaxial layer, such that the doping concentration of the first epitaxial layer reaches the third doping concentration; the first epitaxial layer is an N-type epitaxial layer; Grooves are etched into the first epitaxial layer, passing through the first epitaxial layer and entering the second epitaxial layer to obtain multiple P-grooves; P-pillar material with the third doping concentration is implanted into each of the P-grooves to obtain P-pillars arranged at intervals; the first epitaxial layer portion between the P-pillars constitutes a first N-pillar; the second epitaxial layer portion between the P-pillars constitutes a second N-pillar; The third doping concentration is greater than the fourth doping concentration.

4. A semiconductor device comprising a substrate, an epitaxial layer, and alternating N-pillars and P-pillars within the epitaxial layer, characterized in that, The semiconductor device is prepared using the manufacturing method described in any one of claims 1-3; The epitaxial layer includes a first epitaxial layer and a second epitaxial layer, wherein the second epitaxial layer is located below the first epitaxial layer and adjacent to the substrate; Within the first epitaxial layer, the doping concentration of the P-pillars is equal to that of the N-pillars; Within the second epitaxial layer, the doping concentration of the P-pillars is greater than that of the N-pillars.

5. The semiconductor device according to claim 4, characterized in that, The P-pillar includes a first P-pillar located in the first epitaxial layer and a second P-pillar located in the second epitaxial layer; the doping concentration of the second P-pillar is greater than that of the first P-pillar.

6. The semiconductor device according to claim 5, characterized in that, The doping concentration includes the doping concentration using impurity boron.

7. The semiconductor device according to claim 4, characterized in that, The N-pillar includes a first N-pillar located in the first epitaxial layer and a second N-pillar located in the second epitaxial layer; the doping concentration of the second N-pillar is less than that of the first N-pillar.

8. The semiconductor device according to claim 4, characterized in that, The thickness of the second epitaxial layer is 10% to 15% of the thickness of the epitaxial layer.

9. The semiconductor device according to claim 4, characterized in that, Within the second epitaxial layer, the doping concentration of the P-pillar is 100 times that of the N-pillar.

10. The semiconductor device according to any one of claims 4-9, characterized in that, The semiconductor device is a superjunction VDMOS device.

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