Microchip with on-chip debugging and tracing engine

Abstract

A microchip is disclosed, including a central processing unit (CPU) for executing software applications. The microchip also includes an Ethernet interface for sending and receiving Ethernet packets to and from an external debugging entity. Furthermore, the microchip includes an on-chip debug and trace module for converting debug data and trace data from the CPU into an Ethernet packet stream and providing the Ethernet packet stream to the Ethernet interface for transmission to the external debugging entity. Similarly, the on-chip debug and trace module is used to receive debug commands from the external debugging entity in the form of Ethernet packets and convert the debug commands into instructions for debugging the software application running on the CPU.

Description

Technical Field

[0001] This invention relates to on-chip debugging and tracing functions in microchips or system-on-a-chip devices composed of single-core or multi-core CPUs. Background Technology

[0002] For example, developing software for electronic control units (ECUs) for automotive applications embedded in microchips (such as microprocessors, microcontrollers, or system-on-a-chip devices) is often challenging because these applications are inherently real-time and require continuous interaction with the environment, such as sensors and actuators. Testing begins in simulated environments and on hardware test benches, followed by comprehensive field testing, which typically involves driving the vehicle for considerable distances to ensure proper device operation. Furthermore, embedded applications running in automotive ECUs are often real-time applications that operate at high frequencies and interact directly with the environment. Generally, these types of applications cannot be stopped or slowed down for easier software debugging, as this would interfere with system timing and disrupt its behavior.

[0003] For debugging software applications, the Joint Test Action Group (JTAG) and / or Embedded Trace Macrocell (ETM) tracing ports integrated into the microchip can be used to achieve good observability, traceability, and controllability of the software application. Generally, low-end automotive microchips rarely include ETM, but mid-to-high-end chips usually do. Because JTAG and / or ETM utilize hardware mechanisms implemented within the chip, software can be debugged, traced, and fine-tuned.

[0004] JTAG typically provides debug access and boundary scan: (i) debug access is used by debugger tools to access the internals of a microchip, making its resources and functions available and modifiable, such as registers, memory, and system state; (ii) boundary scan is used by hardware test tools to test the physical connections of a device, such as connections on a printed circuit board (PCB).

[0005] ETM typically provides code traceability, which means that all instructions executed by the CPU can be traced without affecting the system's execution.

[0006] However, due to technical limitations (such as mechanical and physical constraints), JTAG / ETM is only available in laboratory environments and not in the field (i.e., in actual vehicles). One reason is that JTAG / ETM signals are high-frequency signals, requiring the cables of debugging equipment connected to the JTAG / ETM pins to be shortened. This poses a significant challenge if the microchip is placed in inaccessible locations (such as an automotive ECU installed near the vehicle's engine).

[0007] Another approach to software debugging is through software monitoring and tooling, such as using low-frequency COM buses (e.g., UART, CAN) and leveraging AUTOSAR-compliant Diagnostic Communication Manager (DCM) and Diagnostic Event Manager (DEM) modules. This approach typically involves (intrusive) software modifications that may result in additional overhead or slightly different behavior from the final production software version (debug mode vs. target mode). Summary of the Invention

[0008] The purpose of this invention is to provide an improved microchip with on-chip debugging and tracing capabilities.

[0009] The above and other objectives are achieved through the subject matter claimed in the independent claims. Other implementations are apparent in the dependent claims, the specification, and the drawings.

[0010] The embodiments disclosed herein provide a microchip with improved on-chip debugging and tracing capabilities, for example, by utilizing high-speed Ethernet-based communication (which can route low-level debug data generated by the per-core JTAG / ETM line) to debug the microchip in the field.

[0011] More specifically, according to a first aspect, a microchip is provided, wherein the microchip includes a central processing unit (CPU) for executing a debuggable software application. The microchip may be a system-on-a-chip (SoC) or a component thereof. Furthermore, the microchip includes a physical layer Ethernet interface, which may include an Ethernet controller for sending Ethernet packets to and receiving Ethernet packets from an external debugging entity (e.g., a personal computer (PC) running a debugging software framework). Additionally, the microchip includes an on-chip debug and trace module, specifically involving an Ethernet JTAG / ETM engine, for converting debug data, particularly JTAG debug data from the CPU executing the software application, and trace data, particularly ETM trace data from the CPU, into an Ethernet packet stream and providing the Ethernet packet stream to the Ethernet interface for transmission to the external debugging entity or software framework. In one implementation, the on-chip debug and trace module is also configured to receive debug commands from an external debugging entity / framework in the form of one or more Ethernet packets for debugging the software application running on the CPU.

[0012] While in a typical microchip, the JTAG port is used by external debugger tools or debugging software frameworks to connect to the chip to debug one or more kernels, in the microchip embodiments disclosed herein, the external interface used by the microchip is not a JTAG port, but an Ethernet port.

[0013] In yet another possible implementation of the first aspect, the debugging and tracing module includes a JTAG decoder for decoding the debug data from the CPU.

[0014] In another possible implementation of the first aspect, the JTAG decoder is also used to control the JTAG clock signal and the JTAG data signal for executing debug commands sent to the CPU.

[0015] In another possible implementation of the first aspect, the debugging and tracing module includes a JTAG protocol engine for converting debugging commands from the external debugging entity into a sequence of JTAG commands and providing the sequence of JTAG commands to the JTAG decoder.

[0016] In yet another possible implementation of the first aspect, the debugging and tracing module includes a JTAG packet forwarder for receiving Ethernet packets containing debugging commands from the external debugging entity via the Ethernet interface and forwarding the debugging commands to the JTAG protocol engine.

[0017] In yet another possible implementation of the first aspect, the debugging and tracing module includes an ETM decoder for decoding the tracing data from the CPU.

[0018] In yet another possible implementation of the first aspect, the ETM decoder is further configured to control one or more ETM clock signals and extract the tracking data from one or more ETM data signals received from the CPU.

[0019] In yet another possible implementation of the first aspect, the debugging and tracing module further includes a RAM buffer for storing the tracing data.

[0020] In another possible implementation of the first aspect, the debugging and tracing module further includes an ETM protocol engine for distributing tracing data stored in the RAM buffer to multiple Ethernet packets.

[0021] In yet another possible implementation of the first aspect, the ETM protocol engine is also used to determine the sequence of the plurality of Ethernet packets.

[0022] In another possible implementation of the first aspect, the debug and trace module further includes an ETM packet forwarder for sending the plurality of Ethernet packets from the RAM buffer to an external debug entity or debug software framework via the Ethernet interface, based on the sequence of the plurality of Ethernet packets determined by the ETM protocol engine.

[0023] In yet another possible implementation of the first aspect, the microchip may include multiple CPUs connected to the on-chip debug and trace module. More specifically, in yet another possible implementation of the first aspect, the microchip includes at least one other CPU for executing another debuggable software application and a communication bus for communicating between the CPU and the other CPU and the debug and trace module, wherein the debug and trace module is configured to convert additional debug data from the other CPU executing the other software application and additional trace data from the other CPU into additional Ethernet packet streams, and provide the additional Ethernet packet streams to the Ethernet interface for transmission to the external debug entity or debug software framework. In one implementation, the on-chip debug and trace module is further configured to receive debug commands from an external debug entity in the form of one or more Ethernet packets for debugging the software application running on the CPU.

[0024] In yet another possible implementation of the first aspect, the microchip may include more than one CPU and more than one on-chip debug and trace module, wherein at least two CPUs are connected to their respective dedicated on-chip debug and trace modules. More specifically, in yet another possible implementation of the first aspect, the microchip includes at least one other CPU for executing another debuggable software application and at least one other on-chip debug and trace module, wherein the other debug and trace module is configured to convert additional debug data from the other CPU executing the other software application and additional trace data from the other CPU into additional Ethernet packet streams and provide the additional Ethernet packet streams to the Ethernet interface for transmission to the external debug entity, wherein the Ethernet interface is configured to transmit the Ethernet packet streams provided by the debug and trace module and / or the Ethernet packet streams provided by the other debug and trace module to the external debug entity. In one implementation, the other on-chip debug and trace module is further configured to receive debug commands from the external debug entity in the form of one or more Ethernet packets for debugging the software application running on the CPU.

[0025] In yet another possible implementation of the first aspect, the microchip further includes a JTAG interface, specifically involving multiple JTAG pins.

[0026] According to a second aspect, a debugging system is provided, comprising a microchip according to a first aspect and a debugging entity, wherein the debugging entity is configured to send and receive Ethernet packets from the Ethernet interface of the microchip via an Ethernet connection.

[0027] The following drawings and description illustrate one or more embodiments in detail. Other features, objects, and advantages will be apparent from the description, drawings, and claims. Attached Figure Description

[0028] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings, wherein:

[0029] Figure 1 A schematic diagram of a microchip having an on-chip Ethernet debugging and tracing engine is shown according to an embodiment;

[0030] Figure 2 A schematic diagram of a microchip with multiple CPUs is shown, which, according to an embodiment, can perform debugging and tracing operations simultaneously using an on-chip Ethernet debugging and tracing engine.

[0031] Figure 3a A schematic diagram of the software / hardware stack of a typical debugging system is shown; and

[0032] Figure 3b A schematic diagram of the software / hardware stack of a debugging system including a microchip with an on-chip Ethernet debugging and tracing engine, according to an embodiment, is shown.

[0033] In the following figures, the same reference numerals denote the same or at least functionally equivalent features. Detailed Implementation

[0034] In the following description, reference is made to the accompanying drawings, which form part of this invention, which illustrate by way of description specific aspects of embodiments of the invention or aspects in which embodiments of the invention may be used. It should be understood that embodiments of the invention may be used in other aspects and may include structural or logical variations not depicted in the drawings. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of the invention is defined by the appended claims.

[0035] For example, it should be understood that the disclosure relating to the described method can also apply to the corresponding device or system for performing the method, and vice versa. For example, if one or more specific method steps are described, the corresponding device may include one or more units (e.g., functional units) to perform the described one or more method steps (e.g., one unit performs one or more steps, or multiple units perform one or more of a plurality of steps respectively), even if such one or more units are not explicitly described or illustrated in the drawings. On the other hand, for example, if a particular apparatus is described according to one or more units (e.g., functional units), the corresponding method may include a step to perform the function of one or more units (e.g., a step that performs the function of the one or more units, or multiple steps that perform the function of one or more of the plurality of units respectively), even if such one or more steps are not explicitly described or illustrated in the drawings. Furthermore, it should be understood that, unless otherwise expressly stated, features of the various exemplary embodiments and / or aspects described herein can be combined with each other.

[0036] Figure 1 A schematic diagram of a microchip 100 according to an embodiment is shown. The microchip 100 may be a system-on-a-chip 100 or a component thereof. The microchip 100 includes a central processing unit (CPU) 101 for performing debugging and tracing of software applications. Furthermore, the microchip 100 includes a physical layer Ethernet interface 120 (in... Figure 1 This is referred to as the "Ethernet physical layer" in the code. This interface is addressed by the Ethernet controller 118 and is used to communicate with external debugging entities (e.g., Figure 1The microchip 100 (not shown) sends Ethernet packets and receives Ethernet packets from an external debugging entity. Furthermore, the microchip 100 includes an on-chip debug and trace module 110. As detailed below, the on-chip debug and trace module 110 can be implemented using an embedded kernel with associated firmware, or by creating a specific state machine directly in hardware that interacts with external pins used for debugging.

[0037] In the following embodiments of microchip 100, an on-chip debug and trace module 110 will be described, wherein the on-chip debug and trace module 110 is implemented as an on-chip Ethernet JTAG / ETM debug and trace module or an on-chip Ethernet JTAG / ETM engine that utilizes Joint Test Action Group (JTAG) and / or Embedded Trace Macrocell (ETM) technologies. However, it should be understood that the on-chip debug and trace module 110 can be implemented using debugging techniques other than JTAG and / or ETM.

[0038] JTAG is a widely used technology in two main areas: (i) for boundary scan and chip debugging (for debugging internal chip implementations) and (ii) for debugging software applications running on the chip (e.g., for starting / stopping / programming the CPU; reading internal registers / memory; and / or configuring breakpoints, stepping through execution, etc.). Furthermore, using JTAG and the ETM trace port enables good observability, traceability, and controllability of software applications running on the CPU 101. Some features of JTAG and ETM technologies can be found in… Figure 1 The implementation of the microchip 100 shown in the embodiment is summarized below. JTAG (standardized by IEEE 1149.1) technology allows for stopping, starting, and controlling the CPU, for example... Figure 1 The CPU 101 shown reads the device's memory and communicates using a serial device (commonly known as JTAG UART). ETM technology allows for fast data streaming, i.e., from the CPU, for example... Figure 1 The CPU 101 shown is traced to an external debug entity. The trace may include one or more of the following data: program trace (tracing all conditional jumps executed by the processor); data trace (tracing the addresses and values ​​of read / write data); additional "tokens" (typically used to rebuild operating system context changes in resource-constrained systems); and / or the time when the given information was generated, i.e., a timestamp.

[0039] The on-chip debug and trace module 110 is used to convert debug data, specifically JTAG debug data from the CPU 101 executing the software application and trace data, particularly ETM trace data entering the Ethernet packet stream from the CPU 101, and providing the Ethernet packet stream to the Ethernet interface 120 for transmission to an external debug entity. In one embodiment, the on-chip debug and trace module 110 is also used to receive debug commands from an external debug entity in the form of one or more Ethernet packets for debugging the software application running on the CPU 101. Thus, in one embodiment, there can essentially be two data streams through the Ethernet interface 120: (i) a bidirectional and full-duplex data stream associated with JTAG commands and (ii) a unidirectional data stream associated with the ETM data stream (from the CPU 101 to and through the Ethernet interface 120).

[0040] exist Figure 1 In the illustrated embodiment, the on-chip debug and trace module 110 includes the following components for its JTAG portion: a JTAG decoder 111a, a JTAG protocol engine 113a, and a JTAG packet forwarder 115a. The JTAG decoder 111a is used to decode debug data from the CPU 101. Furthermore, the JTAG decoder 111a can be used to control the JTAG clock signal and the JTAG data signal 103a to execute debug commands addressed to the CPU 101, such as debug commands issued by an external debug entity (forwarded by the JTAG protocol engine 113a). The JTAG packet forwarder 115a is linked to the Ethernet controller 118.

[0041] In one embodiment, the JTAG protocol engine 113a of the on-chip debug and trace module 110 is used to convert debug commands from an external debug entity into a JTAG command sequence and provide the JTAG command sequence to the JTAG decoder 111a. In another embodiment, the JTAG packet forwarder 115a of the on-chip debug and trace module 110 is used to receive one or more Ethernet packets containing debug commands from an external debug entity via the Ethernet interface 120 and forward the debug commands to the JTAG protocol engine 113a. In one embodiment, the Ethernet packets can be raw MAC packets, or UDP, TCP, or IP packets. The JTAG packet forwarder 115a is used to parse these types of packets and forward their information content to the JTAG protocol engine 113a.

[0042] exist Figure 1In the illustrated embodiment, the on-chip debug and trace module 110 includes the following components for its ETM portion: an ETM decoder 111b, an ETM protocol engine 113b, and an ETM packet forwarder 115b. The ETM decoder 111b is used to decode trace data from the CPU 101, i.e., to receive and decode ETM signals 105a from the CPU 101. In one embodiment, the ETM decoder 111b is also used to control one or more ETM clock signals and extract trace data from one or more ETM data signals 105a received from the CPU 101.

[0043] like Figure 1 As shown, the on-chip debug and trace module 110 may further include a RAM buffer 119 for storing, for example, trace data of the CPU 101 provided by the ETM decoder 111b. In one embodiment, the RAM buffer 119 may be implemented as a FIFO queue for storing trace data.

[0044] In one embodiment, the ETM protocol engine 113b of the on-chip debug and trace module 110 is used to distribute trace data stored in a RAM buffer 119 (typically large) to multiple Ethernet packets. In other words, the ETM protocol engine 113b is used to control the refreshing of the RAM buffer 119. In one embodiment, the ETM protocol engine 113b can also be used to determine the sequence of multiple Ethernet packets. In one embodiment, the ETM packet forwarder 115b of the on-chip debug and trace module 110 can be used to send multiple Ethernet packets created based on the trace data in the RAM buffer 119 to an external debug entity via the Ethernet interface 120 according to the sequence of multiple Ethernet packets determined by the ETM protocol engine 113b, thereby allowing the external debug entity to efficiently reconstruct the trace data.

[0045] To enable the transmission of large amounts of data, data transfer from the ETM decoder 111b to the Ethernet interface 120 can be completed without data duplication or copying. In one embodiment, the ETM packet forwarder 115b is used to prioritize large packets. In another embodiment, the size of the RAM buffer 119 can be selected such that it can store, i.e., buffer a sufficient number of packets to allow the ETM decoder 111b to stream all data from the trace buffer of the CPU 101, while allowing the ETM protocol engine 113b to prepare packets to be sent. To ensure no packet loss, the storage capacity of the RAM buffer 119 can be determined based on the speed of the Ethernet medium through which packets are transmitted from the Ethernet interface 120. In another embodiment, data transfer to Ethernet can be handled by using a feature that allows trace data to be written to external DRAM memory.

[0046] like Figure 1 As shown, the on-chip debug and trace module 110 may further include a MAC / IP configuration module 117 for allowing the setting or adjustment of MAC / IP configuration parameters of the on-chip debug and trace module 110. In one embodiment, MAC / IP layer configuration can be specified to set the MAC / IP configuration, as well as (in the case of using UDP or TCP / IP) the IP address and port on which data packets should be sent / received.

[0047] In addition, the microchip 100 may also include a physical JTAG interface, specifically involving multiple JTAG pins 103 for connecting the CPU 101 to a JTAG debugging entity and / or a physical ETM interface in a conventional manner, and in particular multiple ETM pins 105 for connecting the CPU 101 to an external ETM debugging entity in a conventional manner.

[0048] Another implementation of microchip 100 is, for example Figure 2 As shown. In Figure 2 In the illustrated embodiment, the microchip 100 is a multi-core microchip 100 and includes multiple on-chip debug and trace modules 110. In one embodiment, Figure 2 The multi-core microchip 100 has multiple on-chip debug and trace modules 110 that can have the same functionality as... Figure 1 The microchip 110 has the same or similar components as the on-chip debug and trace module 110. For example... Figure 2 As shown in the embodiment, multiple on-chip debug and trace modules 110 can be used to communicate with one or more Ethernet interfaces 120 via a communication bus 130, such as Figure 1 The Ethernet interface 120 of the microchip 100 shown is illustrated. Figure 2 In the illustrated embodiment, the multi-core microchip 100 includes multiple Ethernet interfaces 120 and a switch 121 for controlling the multiple Ethernet interfaces 120. Figure 2 As shown, multiple Ethernet interfaces 120 and switches 121 define the Ethernet subsystem 122 of the multi-core microchip 100.

[0049] Therefore, in one embodiment, the microchip 100 includes at least one additional CPU 101 for executing another debuggable software application and at least one other on-chip debug and trace module 110. As described above, in one embodiment, at least two on-chip debug and trace modules 110 can be used to communicate via a communication bus 130. The other on-chip debug and trace module 110 is used to convert additional debug data from the other CPU 101 executing the other software application and additional trace data from the other CPU 101 into additional Ethernet packet streams, and to provide the additional Ethernet packet streams to the Ethernet subsystem 122, and ultimately transmit them to at least one of a plurality of Ethernet interfaces 120 for transmitting the additional Ethernet packet streams to an external debug entity. The Ethernet interface 120 is used to transmit the Ethernet packet streams provided by the on-chip debug and trace module 110 and / or the additional Ethernet packet streams provided by the other on-chip debug and trace module 110 to the external debug entity. In one implementation, the other on-chip debug and trace module 110 is also used to receive debug commands from the external debug entity in the form of one or more Ethernet packets for debugging the other software application running on the other CPU.

[0050] In another embodiment, microchip 100 may include multiple CPUs 101 connected to a single on-chip Ethernet JTAG / ETM debug and trace module, such as... Figure 1 The on-chip debug and trace module 110 is shown. Therefore, in one embodiment, the microchip 100 includes at least one additional CPU for executing another debuggable software application. CPU 101 and the other CPU 101 can be used via a communication bus, for example... Figure 2 The communication bus 130 shown communicates with a single on-chip debug and trace module 110. In this embodiment, the single on-chip debug and trace module 110 is used to convert additional debug data from another CPU 101 executing another software application and additional trace data from the other CPU 101 into additional Ethernet packet streams, and to provide the additional Ethernet packet streams to the Ethernet subsystem 122, and ultimately transmit them to multiple Ethernet interfaces 120 for transmitting the additional Ethernet packet streams to an external debug entity. As described above, the Ethernet subsystem 122 may include one or more Ethernet interfaces 120 and an internal Ethernet switch 121 for routing packets to the appropriate Ethernet interface 120. In one embodiment, the on-chip debug and trace module 110 is also used to receive debug commands from an external debug entity in the form of one or more Ethernet packets for debugging the other software application running on the other CPU 101.

[0051] Figure 3a A schematic diagram of the software / hardware stack of a typical debugging system is shown, while Figure 3b A schematic diagram of the software / hardware stack of a debugging system provided in an embodiment, including the microchip 100 provided in the embodiment, is shown. Figure 3a The typical stack shown includes a chip 300 with a CPU 301 and a standard JTAG / ETM interface 303. The JTAG / ETM interface 303 is then connected to an external device via a JTAG / ETM connector 305. A short cable 309 is typically used to connect to the JTAG / ETM connector 305 for communication with an external box 311. The box 311 may typically contain reconfigurable hardware, such as an FPGA 313 and additional RAM 315, to store collected debug and trace information. In some cases, the in-circuit debugger 311 and cable 309 may be integrated on the same PCB board 307 on which the microchip 300 is soldered. The box 311 is then connected to a personal computer 319 running debug software via a connection cable 317 (typically Ethernet or USB). Figure 3a This illustrates a typical separation from the PCB board 307, which includes chip 300, provided by the manufacturer and typically provided by an "external" debugging tool 320.

[0052] The software / hardware stack of the debugging system included in the embodiment of microchip 100. As described above, microchip 100 includes a CPU 101 and optional conventional JTAG interfaces, i.e., multiple JTAG pins 103 and / or conventional ETM interfaces, i.e., multiple ETM pins 105. Furthermore, Figure 3b A possible stack is shown, which includes a protocol converter layer 181 (provided by decoders 111a and 111b), a protocol management layer 183 (provided by protocol engines 113a and 113b) with optional RAM buffers 119, a standard communication protocol layer 185 (provided by JTAG packet forwarder 115a, packet forwarder 115b and MAC / IP configuration unit 117), and an Ethernet NIC layer 187 (in... Figure 1 (Provided by Ethernet interface 120). All the above components are included in microchip 100, which connects board 193 to debugger software on PC 191 via Ethernet connector 189 integrated in board 193. It should be understood that... Figure 3b The debugger software on the PC 191 shown in the stack corresponds to Figure 3a The stack shown is the debugger software on a personal computer 319.

[0053] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the described apparatus embodiments are merely exemplary. For example, the unit division is merely a logical functional division, and in actual implementation, it can be other divisions. For example, multiple units or components can be merged or integrated into another system, or some features can be ignored or not performed. In addition, the mutual coupling or direct coupling or communication connection shown or described can be implemented through some interface. Direct coupling or communication connection between apparatuses or units can be implemented electronically, mechanically, or otherwise.

[0054] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiment solution according to actual needs.

[0055] In addition, the functional units in the embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

Claims

1. A microchip (100), characterized in that, include: The central processing unit (CPU) (101) is used to execute software applications; Ethernet interface (120) is used to send Ethernet packets to and receive Ethernet packets from external debugging entities; The on-chip debug and trace module (110) is used to convert debug data from the CPU (101) and trace data from the CPU (101) into Ethernet packet streams and provide the Ethernet packet streams to the Ethernet interface (120). Another CPU is used to execute another software application; Another on-chip debug and trace module is used to convert more debug data from the other CPU and more trace data from the other CPU into more Ethernet packet streams and provide the more Ethernet packet streams to the Ethernet interface (120). The Ethernet interface (120) is configured to transmit the Ethernet packet stream and the additional Ethernet packet stream to the external debugging entity.

2. The microchip (100) according to claim 1, characterized in that, The on-chip debug and trace module (110) includes a JTAG decoder (111a) for decoding the debug data from the CPU (101).

3. The microchip (100) according to claim 2, characterized in that, The JTAG decoder (111a) is also used to control one or more JTAG clock signals and one or more JTAG data signals to execute debug commands addressed to the CPU (101).

4. The microchip (100) according to claim 2, characterized in that, The on-chip debug and trace module (110) includes a JTAG protocol engine (113a) for converting one or more debug commands from the external debug entity into a JTAG command sequence and providing the JTAG command sequence to the JTAG decoder (111a).

5. The microchip (100) according to claim 4, characterized in that, The on-chip debug and trace module (110) includes a JTAG packet forwarder (115a) for receiving one or more Ethernet packets including debug commands from the external debug entity and forwarding the debug commands to the JTAG protocol engine (113a).

6. The microchip (100) according to claim 4 or 5, characterized in that, The on-chip debug and trace module (110) includes an ETM decoder (111b) for decoding the trace data from the CPU (101).

7. The microchip (100) according to claim 6, characterized in that, The ETM decoder (111b) is also used to control one or more ETM clock signals and extract the tracking data from one or more ETM data signals received from the CPU (101).

8. The microchip (100) according to claim 6, characterized in that, The on-chip debug and trace module (110) also includes a RAM buffer (119) for storing the trace data.

9. The microchip (100) according to claim 8, characterized in that, The on-chip debug and trace module also includes an ETM protocol engine (113b) for distributing the trace data stored in the RAM buffer (119) to multiple Ethernet packets.

10. The microchip (100) according to claim 9, characterized in that, The ETM protocol engine (113b) is also used to determine the sequence of the plurality of Ethernet packets.

11. The microchip (100) according to claim 10, characterized in that, The on-chip debug and trace module (110) also includes an ETM packet forwarder (115b) for transmitting the plurality of Ethernet packets from the RAM buffer (119) to the external debug entity via the Ethernet interface (120) according to the sequence of the plurality of Ethernet packets determined by the ETM protocol engine (113b).

12. The microchip (100) according to claim 1, characterized in that, The microchip (100) also includes: A communication bus (170) is used to communicate between the CPU (101) and the other CPU and the on-chip debug and trace module (110); The on-chip debug and trace module (110) is used to convert more debug data from the other CPU executing the other software application and more trace data from the other CPU into more Ethernet packet streams, and provide the more Ethernet packet streams to the Ethernet interface (120) for transmitting the more Ethernet packet streams to the external debug entity.

13. The microchip (100) according to claim 1, characterized in that, It also includes the JTAG interface (103).

14. A debugging system, characterized in that, include: Microchip (100) according to any one of claims 1 to 13; A debugging entity, wherein the debugging entity is configured to send and receive Ethernet packets from the Ethernet interface (120) of the microchip (100) via an Ethernet connection.

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