Display panel and display device

Abstract

A display panel and a display device are provided. The display panel comprises: a pixel unit comprising a pixel circuit and a light emitting element, the pixel circuit comprising a driving transistor, a first reset transistor and a second reset transistor; the pixel unit comprises a first pixel unit and a second pixel unit, a first initialization signal line is connected with a first electrode of the first reset transistor in the first pixel unit; a second initialization signal line is connected with a first electrode of the second reset transistor in the first pixel unit; a third initialization signal line is connected with a first electrode of the first reset transistor in the second pixel unit; a fourth initialization signal line is connected with a first electrode of the second reset transistor in the second pixel unit; the first to third initialization signal lines are connected with a first signal bus respectively; the second signal bus is connected with the fourth initialization signal line; and the first signal bus and the second signal bus are insulated from each other.

Description

Technical Field

[0001] At least one embodiment of this disclosure relates to a display panel and a display device. Background Technology

[0002] With the continuous development of display technology, active-matrix organic light-emitting diode (AMOLED) display technology has been increasingly used in display devices such as mobile phones, tablets, and digital cameras due to its advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and high response speed.

[0003] Under-display camera technology is a new technology proposed to improve the screen-to-body ratio of display devices. Summary of the Invention

[0004] At least one embodiment of this disclosure relates to a display panel and a display device.

[0005] At least one embodiment of this disclosure provides a display panel, comprising: a substrate including a display area, the display area including a first display area and a second display area, the first display area being located on at least one side of the second display area; a pixel unit located on the substrate, including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the pixel circuit including a driving transistor, a first reset transistor and a second reset transistor, the first reset transistor being connected to the gate of the driving transistor and configured to reset the gate of the driving transistor, the second reset transistor being connected to a first electrode of the light-emitting element and configured to reset the first electrode of the light-emitting element; the pixel unit including a first pixel unit and a second pixel unit, the pixel circuit of the first pixel unit being located in the first display area and at least partially overlapping with the light-emitting element of the first pixel unit, the light-emitting element of the second pixel unit being located in the second display area, and the second pixel unit... The pixel circuit of the second pixel unit is located outside the second display area, and the pixel circuit of the second pixel unit is connected to the light-emitting element of the second pixel unit through a conductive line; a first initialization signal line is connected to the first terminal of the first reset transistor in the first pixel unit; a second initialization signal line is connected to the first terminal of the second reset transistor in the first pixel unit; a third initialization signal line is connected to the first terminal of the first reset transistor in the second pixel unit; a fourth initialization signal line is connected to the first terminal of the second reset transistor in the second pixel unit; a first signal bus is configured to provide a first initialization signal, and the first initialization signal line, the second initialization signal line, and the third initialization signal line are respectively connected to the first signal bus; a second signal bus is configured to provide a second initialization signal and is connected to the fourth initialization signal line; the first signal bus and the second signal bus are insulated from each other and are configured to input different initialization signals.

[0006] For example, the orthographic projection of the pixel circuit of the second pixel unit onto the substrate does not overlap with the orthographic projection of the light-emitting element of the second pixel unit onto the substrate.

[0007] For example, the substrate further includes a peripheral region located on at least one side of the display area, the peripheral region being a non-display area, and the pixel circuit of the second pixel unit being located in the peripheral region.

[0008] For example, at least a portion of the first signal bus and at least a portion of the second signal bus are both located in the peripheral area.

[0009] For example, the second initialization signal is greater than the first initialization signal.

[0010] For example, the display panel also includes an integrated circuit, with the first signal bus and the second signal bus respectively connected to different pins of the integrated circuit.

[0011] For example, the first signal bus is closer to the display area than the second signal bus.

[0012] For example, the display panel also includes a power line configured to provide a constant voltage signal to the pixel circuitry, the power line being connected to a second pole of the light-emitting element, and at least a portion of the second signal bus being located between the power line and the display area.

[0013] For example, at least a portion of the first signal bus is located between the power line and the display area.

[0014] For example, the display panel also includes a control circuit located between the power line and the display area, and the first signal bus and the second signal bus located between the control circuit and the display area.

[0015] For example, the display panel also includes a control circuit, wherein the control circuit is located between the power line and the display area, the first signal bus is located between the control circuit and the display area, and the second signal bus is located between the control circuit and the power line.

[0016] For example, the orthographic projection of the second signal bus on the substrate overlaps at least partially with the orthographic projection of the control circuit on the substrate.

[0017] For example, the orthographic projection of the second signal bus on the substrate overlaps at least partially with the orthographic projection of the power line on the substrate.

[0018] For example, the second signal bus includes two sub-lines located in the first conductive layer and the second conductive layer, respectively, connected by vias.

[0019] For example, the first signal bus includes two sub-lines located on the third conductive layer and the fourth conductive layer, respectively, connected by vias.

[0020] For example, the width of the first signal bus is greater than the width of the second signal bus.

[0021] For example, the second signal bus is configured to provide the second initialization signal, which includes at least two voltage signals with different values.

[0022] At least one embodiment of this disclosure also provides a display device including any of the above-described display panels.

[0023] For example, the display device also includes a light sensor located on one side of the display panel. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0025] Figure 1 This is a schematic diagram of a display panel.

[0026] Figure 2 This is a schematic diagram of a pixel unit in a display panel.

[0027] Figure 3 This is a schematic diagram of a display panel with external pixel circuitry.

[0028] Figure 4 This is a schematic diagram showing the connection between the pixel circuit and the light-emitting element of a second pixel unit in a display panel according to an embodiment of the present disclosure.

[0029] Figure 5 This is a schematic diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure.

[0030] Figure 6 This is a layout diagram of pixel circuits in a display panel according to an embodiment of the present disclosure.

[0031] Figure 7 This is a schematic diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure.

[0032] Figure 8 This is a layout diagram of pixel circuits in a display panel according to an embodiment of the present disclosure.

[0033] Figure 9 for Figure 6 A cross-sectional view along line AB or along Figure 8 A sectional view along line CD.

[0034] Figure 10 This is a schematic diagram of a second pixel unit in a display panel according to an embodiment of the present disclosure.

[0035] Figure 11 This is a schematic diagram of a display panel provided in one embodiment of the present disclosure.

[0036] Figure 12 for Figure 11 The diagram is shown in box B1.

[0037] Figure 13This is a schematic diagram of a display panel provided in one embodiment of the present disclosure.

[0038] Figure 14 for Figure 13 The diagram is shown in box B2.

[0039] Figure 15 This is a partial schematic diagram of a display panel provided in an embodiment of the present disclosure.

[0040] Figure 16 This is a partial schematic diagram of a display panel provided in an embodiment of the present disclosure.

[0041] Figure 17 This is a schematic diagram of a first signal bus in a display panel provided according to an embodiment of the present disclosure.

[0042] Figure 18 This is a schematic diagram of a second signal bus in a display panel provided according to an embodiment of the present disclosure.

[0043] Figure 19 This is a timing signal diagram of a pixel unit in a display panel provided in an embodiment of the present disclosure.

[0044] Figure 20 This is a schematic diagram of a second initialization signal in a display panel provided according to an embodiment of the present disclosure.

[0045] Figure 21 This is a schematic diagram of a second initialization signal in a display panel provided according to an embodiment of the present disclosure.

[0046] Figure 22 and Figure 23 This is a schematic diagram of a display device provided according to an embodiment of the present disclosure. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0048] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0049] With the continuous development of mobile phone screens, full-screen phones and under-display camera technology have become hot topics. In order to improve the PPI (Pixel Per Inch) and transmittance of the camera area, the under-display camera area usually retains the light-emitting element, while placing the pixel circuit (driving circuit) of the light-emitting element in other locations. For example, the pixel circuit can adopt an external or compressed solution, and transparent conductive lines are usually used to connect the light-emitting element and the pixel circuit to complete its driving light emission.

[0050] Figure 1 This is a schematic diagram of a display panel. (Example) Figure 1 As shown, the display panel includes a display area R0 and a peripheral area R3. The peripheral area R3 is a non-display area. The display area R0 includes a first display area R1 and a second display area R2. For example, hardware such as a light sensor (e.g., a camera) is disposed on one side of the display panel at a position corresponding to the second display area R2. For example, the second display area R2 is a light-transmitting display area, and the first display area R1 is a display area. For example, the first display area R1 is opaque and used only for display. The first display area R1 and the second display area R2 together constitute the display area of ​​the display panel. Figure 1 The substrate BS and the integrated circuit CC are also shown.

[0051] Figure 2 This is a schematic diagram of pixel units in a display panel. (Example) Figure 2 As shown, pixel unit 100 includes pixel circuit 100a and light-emitting element 100b, wherein pixel circuit 100a is configured to drive light-emitting element 100b. For example, pixel circuit 100a is configured to provide driving current to drive light-emitting element 100b to emit light. For example, light-emitting element 100b includes organic light-emitting diode (OLED), and light-emitting element 100b emits red light, green light, blue light, or white light, etc., under the drive of its corresponding pixel circuit 100a. The color emitted by light-emitting element 100b can be determined as needed. Figure 2 As shown, the light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer located between the first electrode E1 and the second electrode E2. For example, the first electrode E1 is an anode and the second electrode E2 is a cathode, but it is not limited thereto. For example, the first electrode E1 may be a pixel electrode and the second electrode E2 may be a common electrode.

[0052] To improve the light transmittance of the second display area R2, only a light-emitting element can be provided in the second display area R2, while the pixel circuit that drives the light-emitting element of the second display area R2 is located outside the second display area R2. For example, the pixel circuit that drives the light-emitting element of the second display area R2 can be located in the first display area R1 or the peripheral area R3. That is, the light transmittance of the second display area R2 is improved by separating the light-emitting element and the pixel circuit. In other words, no pixel circuit is provided in the second display area R2.

[0053] Figure 3 This is a schematic diagram of a display panel with externally mounted pixel circuitry. Figure 3 As shown, the display panel includes a substrate BS and pixel units 100 located on the substrate BS. Figure 3 As shown, pixel unit 100 includes a first pixel unit 101 and a second pixel unit 102. The first pixel unit 101 includes a first pixel circuit 10 and a first light-emitting element 30, and the second pixel unit 102 includes a second pixel circuit 20 and a second light-emitting element 40. Figure 3 As shown, the first pixel circuit 10 and the first light-emitting element 30 of the first pixel unit 101 are both located in the first display area R1, the second pixel circuit 20 of the second pixel unit 101 is located in the peripheral area R3, and the second light-emitting element 40 of the second pixel unit 102 is located in the second display area R2. For example, the first pixel circuit 10 can be called an in-situ pixel circuit, and the second pixel circuit 20 can be called a non-in-situ pixel circuit. Both the first pixel circuit 10 and the second pixel circuit 20 are driving circuits. Figure 1 As shown, in the second display area R2, the area between adjacent second light-emitting elements 40 is a light-transmitting sub-area, and the area where the second light-emitting elements 40 are located is a display sub-area. Figure 1 and Figure 3 The external circuitry area R3a is shown. For example, as... Figure 3 As shown, the second pixel circuit 20 is located in the external circuit area R3a.

[0054] For example, such as Figure 3 As shown, the display panel includes: a plurality of first pixel circuits 10 and a plurality of first light-emitting elements 30 located in the first display area R1, a plurality of second pixel circuits 20 located in the peripheral area R3, and a plurality of second light-emitting elements 40 located in the second display area R2. For example, as Figure 3As shown, multiple second pixel circuits 20 can be arranged in an array in the peripheral area R3.

[0055] For example, such as Figure 3 As shown, at least one of the plurality of first pixel circuits 10 can be connected to at least one of the plurality of first light-emitting elements 30, and the orthographic projection of at least one first pixel circuit 10 on the substrate BS and the orthographic projection of at least one first light-emitting element 30 on the substrate BS can at least partially overlap. The at least one first pixel circuit 10 can be used to provide a driving signal to the first light-emitting element 30 connected thereto, so as to drive the first light-emitting element 30 to emit light.

[0056] Figure 3 Taking the second pixel circuit 20, which drives the second light-emitting element 40 to emit light, located in the peripheral area R3 as an example, the second pixel circuit 20 is disposed outside the display area R0. In this case, the display panel adopts an external pixel circuit scheme. Of course, in other embodiments, the second pixel circuit 20 can also be located in the first display area R1, thereby forming a pixel circuit compression scheme. In the pixel circuit compression scheme, the size of the pixel circuit in the first direction X is reduced, so that the first pixel circuit 10 and the second pixel circuit 20 can be placed in the first direction X, and the second pixel circuit 20 can be distributed in the first pixel circuit 10. For example, if the first direction X is the row direction, the second pixel circuit 20 is arranged at intervals in the first pixel circuit 10 in the same row of pixel circuits.

[0057] For example, such as Figure 1 and Figure 3 As shown, the first display area R1 can be located on at least one side of the second display area R2. For example, in some embodiments, the first display area R1 surrounds the second display area R2. That is, the second display area R2 can be surrounded by the first display area R1. The second display area R2 can also be located at other positions, and the location of the second display area R2 can be determined as needed. For example, the second display area R2 can be located at the top center of the substrate BS, or at the upper left corner or upper right corner of the substrate BS.

[0058] Figure 4 This is a schematic diagram illustrating the connection between a second pixel circuit and a second light-emitting element in a display panel according to an embodiment of this disclosure. For example, as... Figure 3 and Figure 4As shown, at least one of the plurality of second pixel circuits 20 can be connected to at least one of the plurality of second light-emitting elements 40 via a conductive line L1. The at least one second pixel circuit 20 can be used to provide a driving signal to the connected second light-emitting element 40 to drive it to emit light. The second pixel circuit 20 controls the second light-emitting element 40 to emit light via the conductive line L1.

[0059] like Figure 3 and Figure 4 As shown, the second light-emitting element 40 is located in the second display area R2, and the second pixel circuit 20 is located in the peripheral area R3. Since the second light-emitting element 40 and the second pixel circuit 20 are located in different areas, there is no overlap between the orthographic projection of at least one second pixel circuit 20 on the substrate BS and the orthographic projection of at least one second light-emitting element 40 on the substrate BS.

[0060] For example, in the embodiments of this disclosure, the first display area R1 can be set as a non-transparent display area, and the second display area R2 can be set as a transparent display area. For example, the first display area R1 is opaque, and the second display area R2 is transparent. Thus, the display panel provided by the embodiments of this disclosure does not require perforation on the display panel; the necessary hardware structures, such as the photosensor, can be directly placed on one side of the display panel at the position corresponding to the second display area R2, laying a solid foundation for the realization of a true full-screen display. Furthermore, since the second display area R2 only includes light-emitting elements and not pixel circuits, the light transmittance of the second display area R2 is improved, resulting in a better display effect for the display panel.

[0061] For example, such as Figure 3 and Figure 4 As shown, the second pixel circuit 20 and the second light-emitting element 40 of the second pixel unit 102 are separately arranged, and the conductive line L1 is arranged as follows. Figure 4 As shown, Figure 4 The following explanation uses the example of a second pixel circuit 20 connected to a second light-emitting element 40. Figure 4 As shown, multiple second pixel circuits 20 are arranged in an array. Figure 4 The following explanation will be based on the example of one column of second light-emitting elements 40 corresponding to two columns of second pixel circuits 20. Figure 4 The data line DT is also shown.

[0062] like Figure 3 and Figure 4As shown, the pixel circuit (second pixel circuit 20) of the second pixel unit 102 is connected to the light-emitting element (second light-emitting element 40) of the second pixel unit 102 via a conductive line L1. For example, the conductive line L1 is made of a transparent conductive material. For example, the conductive line L1 is made of a conductive oxide material. For example, the conductive oxide material includes indium tin oxide (ITO), but is not limited to this.

[0063] like Figure 3 and Figure 4 As shown, one end of the conductive line L1 is connected to the second pixel circuit 20, and the other end of the conductive line L1 is connected to the second light-emitting element 40. Figure 3 and Figure 4 As shown, the conductive line L1 extends from the first display area R1 to the second display area R2.

[0064] Figure 5 This is a schematic diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure. Figure 6 This is a layout diagram of pixel circuits in a display panel according to an embodiment of the present disclosure. Figure 7 This is a schematic diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure. Figure 8 This is a layout diagram of pixel circuits in a display panel according to an embodiment of the present disclosure. Figure 9 for Figure 6 A cross-sectional view along line AB or along Figure 8 A sectional view along line CD. Figure 10 This is a schematic diagram of a second pixel unit in a display panel according to an embodiment of the present disclosure. Figure 5 and Figure 7 Nodes N1 to N4 are shown. Figure 10 Node N5 is shown. For example, in some embodiments, reference is made to... Figure 5 A capacitor is formed between the first node N1 and the conductive line L1, and a capacitor is formed between the conductive line L1 and the fourth node N4. The conductive line L1 is coupled to the first node N1 and the fourth node N4 respectively, which causes brightness differences and creates display defects such as mura, affecting display quality.

[0065] Figure 5 and Figure 7The pixel circuit shown can be a pixel circuit of a Low Temperature Poly-silicon (LTPS) AMOLED, but is not limited thereto. The pixel circuit can also be a Low Temperature Poly-Oxide (LTPO) pixel circuit, achieving low leakage current and improving the stability of the gate voltage of the driving transistor. The embodiments of this disclosure are illustrated using a pixel circuit of a Low Temperature Poly-silicon (LTPS) AMOLED as an example.

[0066] Figure 5 A pixel circuit for a first pixel unit 101 of a display panel is provided in one embodiment of the present disclosure. Figure 6 This is a layout diagram of a first pixel circuit 10 of a display panel provided in an embodiment of the present disclosure. Figure 7 A pixel circuit for a second pixel unit 102 of a display panel is provided in one embodiment of the present disclosure. Figure 8 This is a layout diagram of a second pixel circuit 20 of a display panel provided in an embodiment of the present disclosure. Figure 10 The capacitance C1 formed by the conductive line L1 and other components overlapping it is shown. Capacitance C1 is a parasitic capacitance. (Reference) Figure 4 Because the lengths of the conductive lines are different, their capacitances are also different. Therefore, due to the presence of capacitor C1, the screen-on time of the second display area will be delayed to varying degrees. That is, within one frame, the second light-emitting element will emit light after a delay of several milliseconds, which poses a higher risk of screen flickering and affects the uniformity of the image.

[0067] like Figures 5 to 8 As shown, pixel circuit 100a includes six switching transistors (T2-T7), one driving transistor T1, and one storage capacitor Cst. The six switching transistors are a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, and a second reset transistor T7. Light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer located between the first electrode E1 and the second electrode E2. For example, the first electrode E1 is the anode, and the second electrode E2 is the cathode. For example, the threshold compensation transistor T3 and the first reset transistor T6 employ a dual-gate thin-film transistor (TFT) to reduce leakage current.

[0068] like Figures 5 to 8As shown, in some embodiments, the pixel unit 100 is located on the substrate BS. The pixel unit 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a is configured to drive the light-emitting element 100b. The pixel circuit 100a includes a driving transistor T1, a first reset transistor T6, and a second reset transistor T7. The first reset transistor T6 is connected to the gate T10 of the driving transistor T1 and is configured to reset the gate T10 of the driving transistor T1. The second reset transistor T7 is connected to the first electrode E1 of the light-emitting element 100b and is configured to reset the first electrode E1 of the light-emitting element 100b. The pixel unit 100 includes a first pixel unit. The first pixel unit 101 has a pixel circuit 100a (first pixel circuit 10) located in the first display area R1 and at least partially overlapping with the light-emitting element 100b (first light-emitting element 30) of the first pixel unit 101. The second pixel unit 102 has a light-emitting element 100b (second light-emitting element 40) located in the second display area R2, and its pixel circuit 100a (second pixel circuit 20) located outside the second display area R2. The pixel circuit 100a (second pixel circuit 20) and the light-emitting element 100b (second light-emitting element 40) of the second pixel unit 102 are connected by a conductive line L1. Although the embodiments of this disclosure are described using a 7T1C pixel circuit as an example, the pixel circuits of the embodiments of this disclosure are not limited to the 7T1C pixel circuit, and can be any pixel circuit including a driving transistor T1, a first reset transistor T6, and a second reset transistor T7.

[0069] like Figures 5 to 8As shown, the display panel includes a gate line GT, a data line DT, a first power line PL1, a second power line PL2, a light emission control signal line EML, an initialization signal line INT, and a reset control signal line RST. For example, the reset control signal line RST includes a first reset control signal line RST1 and a second reset control signal line RST2. The first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel unit 100, and the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel unit 100, wherein the first voltage signal VDD is greater than the second voltage signal VSS. The gate line GT is configured to provide a scan signal SCAN to the pixel unit 100, the data line DT is configured to provide a data signal DATA (data voltage VDATA) to the pixel unit 100, the light emission control signal line EML is configured to provide a light emission control signal EM to the pixel unit 100, the first reset control signal line RST1 is configured to provide a first reset control signal RESET1 to the pixel unit 100, and the second reset control signal line RST2 is configured to provide a scan signal SCAN to the pixel unit 100. For example, in a row of pixel units, the second reset control signal line RST2 can be connected to the gate line GT to be input to the scan signal SCAN. Of course, the second reset control signal line RST2 can also be input to the second reset control signal RESET2.

[0070] Figure 10 The circuit diagram illustrates the conductive line and its load. The activation time of the second light-emitting element 40 is related to the voltage difference between node N5 and the second voltage signal VSS on the second power line PL2. When the voltage difference reaches the activation voltage of the second light-emitting element 40, the second light-emitting element 40 begins to emit light. The voltage change at node N5 begins with the voltage at node N4 after being reset by the second reset transistor. During the light-emitting phase, the voltage continuously increases until the voltage difference between node N5 and the second voltage signal VSS reaches the activation voltage of the second light-emitting element 40.

[0071] For example, such as Figures 5 to 8 As shown, the first initialization signal line INT1 is configured to provide the first initialization signal Vinit1 to the pixel unit 100. The second initialization signal line INT2 is configured to provide the first initialization signal Vinit1 to the pixel unit 100.

[0072] For example, such as Figure 7 and Figure 8 As shown, the third initialization signal line INT3 is configured to provide the first initialization signal Vinit1 to the pixel unit 100. The fourth initialization signal line INT4 is configured to provide the second initialization signal Vinit2 to the pixel unit 100.

[0073] For example, both the first initialization signal Vinit1 and the second initialization signal Vinit2 are constant voltage signals, whose magnitudes can be, for example, between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto. For example, both the first initialization signal Vinit1 and the second initialization signal Vinit2 can be less than or equal to the second voltage signal VSS. For example, the second initialization signal Vinit2 is greater than the first initialization signal Vinit1. An embodiment of this disclosure provides a display panel that, by increasing the second initialization signal Vinit2 to be greater than the first initialization signal Vinit1, charges the voltage at node N5 to a higher position during the reset phase, and then shortens the voltage rise time at node N5 during the light-emitting phase, thus advancing the turn-on time of the second light-emitting element 40. In this way, all the second light-emitting elements 40 in the second display area light up simultaneously, improving the uniformity of the displayed image. Furthermore, compared to the first display area, the second display area does not experience delayed light emission due to a large load on the conductive line L1. In some embodiments, the second initialization signal Vinit2 can be set with different voltage values ​​for high grayscale, low grayscale, and black screen conditions. That is, the second initialization signal Vinit2 is not a constant voltage signal, in order to eliminate the current difference between the second display area and the first display area and improve the uniformity of the image. For example, the second initialization signal Vinit2 can use different voltage signals for the three conditions of high grayscale, low grayscale, and black screen. For example, the second initialization signal Vinit2 includes three voltage signals with different values.

[0074] like Figures 5 to 8 As shown, the driving transistor T1 is electrically connected to the light-emitting element 100b, and outputs a driving current to drive the light-emitting element 100b to emit light under the control of signals such as the scan signal SCAN, the data signal DATA, the first voltage signal VDD, and the second voltage signal VSS.

[0075] For example, the light-emitting element 100b includes an organic light-emitting diode (OLED), which emits red, green, blue, or white light under the drive of its corresponding pixel circuit 100a. For example, a pixel includes multiple pixel units. A pixel may include multiple pixel units that emit different colors of light. For example, a pixel may include pixel units that emit red light, pixel units that emit green light, and pixel units that emit blue light, but is not limited to these. The number of pixel units included in a pixel and the light emission characteristics of each pixel unit can be determined as needed.

[0076] like Figures 5 to 8As shown, the first reset transistor T6 is connected to the gate T10 of the driving transistor T1 and is configured to reset the gate of the driving transistor T1. The second reset transistor T7 is connected to the first electrode E1 of the light-emitting element 100b and is configured to reset the first electrode E1 of the light-emitting element 100b.

[0077] like Figure 5 and Figure 6 As shown, the first initialization signal line INT1 is connected to the gate of the driving transistor T1 through the first reset transistor T6. The second initialization signal line INT2 is connected to the first terminal E1 of the light-emitting element 100b (the first light-emitting element 30) through the second reset transistor T7.

[0078] like Figure 7 and Figure 8 As shown, the third initialization signal line INT3 is connected to the gate of the driving transistor T1 through the first reset transistor T6. The fourth initialization signal line INT4 is connected to the first terminal E1 of the light-emitting element 100b (second light-emitting element 40) through the second reset transistor T7.

[0079] For example, such as Figures 5 to 8 As shown, the gate T60 of the first reset transistor T6 is connected to the first reset control signal line RST1, and the gate T70 of the second reset transistor T7 is connected to the second reset control signal line RST2.

[0080] For example, such as Figures 5 to 8 As shown, the second terminal T62 of the first reset transistor T6 is connected to the gate T10 of the driving transistor T1, and the second terminal T72 of the second reset transistor T7 is connected to the first terminal E1 of the light-emitting element 100b.

[0081] For example, such as Figure 5 and Figure 6 As shown, the first terminal T61 of the first reset transistor T6 is connected to the first initialization signal line INT1, and the first terminal T71 of the second reset transistor T7 is connected to the second initialization signal line INT2. That is, the first initialization signal line INT1 is connected to the first terminal T61 of the first reset transistor T6 in the first pixel unit 101, and the second initialization signal line INT2 is connected to the first terminal T71 of the second reset transistor T7 in the first pixel unit 101.

[0082] For example, such as Figure 7 and Figure 8As shown, the first terminal T61 of the first reset transistor T6 is connected to the third initialization signal line INT3, and the first terminal T71 of the second reset transistor T7 is connected to the fourth initialization signal line INT4. That is, the third initialization signal line INT3 is connected to the first terminal T61 of the first reset transistor T6 in the second pixel unit 102, and the fourth initialization signal line INT4 is connected to the first terminal T71 of the second reset transistor T7 in the second pixel unit 102.

[0083] For example, such as Figures 5 to 8 As shown, the gate T20 of the data writing transistor T2 is connected to the gate line GT, the first terminal T21 of the data writing transistor T2 is connected to the data line DT, and the second terminal T22 of the data writing transistor T2 is connected to the first terminal T11 of the driving transistor T1.

[0084] For example, such as Figures 5 to 8 As shown, the gate T30 of the threshold compensation transistor T3 is connected to the gate line GT, the first terminal T31 of the threshold compensation transistor T3 is connected to the second terminal T12 of the driving transistor T1, and the second terminal T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1.

[0085] For example, such as Figures 5 to 8 As shown, the gate T40 of the first light-emitting control transistor T4 is connected to the light-emitting control signal line EML, the first terminal T41 of the first light-emitting control transistor T4 is connected to the first power supply line PL1, and the second terminal T42 of the first light-emitting control transistor T4 is connected to the first terminal T11 of the driving transistor T1; the gate T50 of the second light-emitting control transistor T5 is connected to the light-emitting control signal line EML, the first terminal T51 of the second light-emitting control transistor T5 is connected to the second terminal T12 of the driving transistor T1, and the second terminal T52 of the second light-emitting control transistor T5 is connected to the first terminal E1 of the light-emitting element 100b.

[0086] like Figure 5 and Figure 7 As shown, the pixel circuit also includes a storage capacitor Cst. The first terminal Ca of the storage capacitor Cst is connected to the gate T10 of the driving transistor T1, and the second terminal Cb of the storage capacitor Cst is connected to the first power supply line PL1.

[0087] For example, such as Figure 5 As shown, the second power line PL2 is connected to the second electrode E2 of the light-emitting element 100b.

[0088] like Figure 6 As shown, the driving transistor T1 includes a gate T10. (Reference) Figure 6 and Figure 8The second electrode Cb of the storage capacitor Cst has an opening OPN1, and one end of the connecting electrode CE1 is connected to the gate T10 of the driving transistor T1 through the opening OPN1.

[0089] For example, refer to Figure 3 At least one of the multiple conductive lines L1 has its orthographic projection on the substrate BS overlapping with the orthographic projection of the pixel circuit (first pixel circuit 10) of the first pixel unit 101 on the substrate BS.

[0090] refer to Figure 6 and Figure 9 A buffer layer BL is disposed on the substrate BS, an isolation layer BR is disposed on the buffer layer BL, an active layer LY0 is disposed on the isolation layer BR, a first insulating layer ISL1 is disposed on the active layer LY0, a first conductive layer LY1 is disposed on the first insulating layer ISL1, a second insulating layer ISL2 is disposed on the first conductive layer LY1, a second conductive layer LY2 is disposed on the second insulating layer ISL2, a third insulating layer ISL3 is disposed on the second conductive layer LY2, and a third conductive layer LY3 is disposed on the third insulating layer ISL3. The third conductive layer LY3 includes a connection electrode CE0, which is connected to the second electrode T52 of the second light-emitting control transistor T5 through a via H3 penetrating the first insulating layer ISL1, the second insulating layer ISL2, and the third insulating layer ISL3.

[0091] like Figure 6 and Figure 8 As shown, one end of the connecting electrode CE1 is connected to the gate T10 of the driving transistor T1 through the via H1, and the other end of the connecting electrode CE1 is connected to the second electrode T62 of the first reset transistor T6 through the via H2.

[0092] like Figure 6 As shown, one end of the connecting electrode CE2 is connected to the first initialization signal line INT1 through via H4, and the other end of the connecting electrode CE2 is connected to the first terminal T61 of the first reset transistor T6 through via H5. One end of the connecting electrode CE3 is connected to the second initialization signal line INT2 through via H6, and the other end of the connecting electrode CE3 is connected to the first terminal T71 of the second reset transistor T7 through via H7.

[0093] like Figure 8 As shown, one end of the connecting electrode CE2 is connected to the third initialization signal line INT3 through via H4, and the other end of the connecting electrode CE2 is connected to the first terminal T61 of the first reset transistor T6 through via H5. One end of the connecting electrode CE3 is connected to the fourth initialization signal line INT4 through via H6, and the other end of the connecting electrode CE3 is connected to the first terminal T71 of the second reset transistor T7 through via H7.

[0094] like Figure 6 and Figure 8 As shown, the first power line PL1 is connected to the first terminal T41 of the first light-emitting control transistor T4 through via H8. The first power line PL1 is connected to the second terminal Cb of the storage capacitor Cst through via H9. The first power line PL1 is connected to the stop block BK through via Hk. The data line DT is connected to the first terminal T21 of the data writing transistor T2 through via H0.

[0095] like Figure 6 and Figure 8 As shown, the channels of each transistor and the first and second electrodes located on both sides of the channel are located in the active layer LY0; the first reset control signal line RST1, the gate line GT, the gate T10 of the driving transistor (the first electrode Ca of the storage capacitor Cst), the light emission control signal line EML, and the second reset control signal line RST2 are located in the first conductive layer LY1; the first initialization signal line INT1, the second electrode Cb of the storage capacitor Cst, the second initialization signal line INT2, the third initialization signal line INT3, and the fourth initialization signal line INT4 are located in the second conductive layer LY2; the data line DT, the first power supply line PL1, the connection electrode CE1, the connection electrode CE2, the connection electrode CE3, and the connection electrode CE0 are located in the third conductive layer LY3.

[0096] like Figure 6 and Figure 8 As shown, the first initialization signal line INT1, the first reset control signal line RST1, the gate line GT, the light emission control signal line EML, the second initialization signal line INT2, the third initialization signal line INT3, the fourth initialization signal line INT4, and the second reset control signal line RST2 all extend along the first direction X, as shown. Figure 6 and Figure 8 As shown, both the data line DT and the first power line PL1 extend along the second direction Y.

[0097] For example, in the manufacturing process of a display panel, a self-aligned process is used to conduct the semiconductor pattern layer using the first conductive layer LY1 as a mask. The semiconductor pattern layer can be formed by patterning a semiconductor thin film. For example, ion implantation is used to heavily dope the semiconductor pattern layer, thereby making the portion of the semiconductor pattern layer not covered by the first conductive layer LY1 conductive, forming the source region (first pole T11) and drain region (second pole T12) of the driving transistor T1, the source region (first pole T21) and drain region (second pole T22) of the data writing transistor T2, the source region (first pole T31) and drain region (second pole T32) of the threshold compensation transistor T3, the source region (first pole T41) and drain region (second pole T42) of the first light-emitting control transistor T4, the source region (first pole T51) and drain region (second pole T52) of the second light-emitting control transistor T5, the source region (first pole T61) and drain region (second pole T62) of the first reset transistor T6, and the source region (first pole T71) and drain region (second pole T72) of the second reset transistor T7. The portion of the semiconductor patterned layer covered by the first conductive layer LY1 retains semiconductor properties, forming the channel region of the driving transistor T1, the channel region of the data writing transistor T2, the channel region of the threshold compensation transistor T3, the channel region of the first light-emitting control transistor T4, the channel region of the second light-emitting control transistor T5, the channel region of the first reset transistor T6, and the channel region of the second reset transistor T7. For example, as... Figure 6 As shown, the second terminal T72 of the second reset transistor T7 and the second terminal T52 of the second light-emitting control transistor T5 are integrally formed; the first terminal T51 of the second light-emitting control transistor T5, the second terminal T12 of the driving transistor T1, and the first terminal T31 of the threshold compensation transistor T3 are integrally formed; the first terminal T11 of the driving transistor T1, the second terminal T22 of the data writing transistor T2, and the second terminal T42 of the first light-emitting control transistor T4 are integrally formed; the second terminal T32 of the threshold compensation transistor T3 and the second terminal T62 of the first reset transistor T6 are integrally formed. In some embodiments, such as Figure 6 As shown, the first electrode T71 of the second reset transistor T7 and the first electrode T61 of the first reset transistor T6 can be integrally formed.

[0098] For example, the channel region of the transistor used in this embodiment can be monocrystalline silicon, polycrystalline silicon (e.g., low-temperature polycrystalline silicon), or metal-oxide-semiconductor (MODS) materials (e.g., IGZO, AZO, etc.). In one embodiment, the transistor is a P-type low-temperature polycrystalline silicon (LTPS) thin-film transistor. In another embodiment, the threshold compensation transistor T3 and the first reset transistor T6, which are directly connected to the gate of the driving transistor T1, are MODS thin-film transistors, that is, the channel material of the transistor is a MODS material (e.g., IGZO, AZO, etc.). MODS thin-film transistors have lower leakage current, which can help reduce the gate leakage current of the driving transistor T1.

[0099] For example, the transistors used in the embodiments of this disclosure may include various structures, such as top-gate, bottom-gate, or dual-gate structures. In one embodiment, the threshold compensation transistor T3 and the first reset transistor T6, which are directly connected to the gate of the driving transistor T1, are dual-gate thin-film transistors, which can help reduce the gate leakage current of the driving transistor T1.

[0100] For example, the display panel also includes a pixel definition layer and spacers. The pixel definition layer has openings configured to define the light-emitting area (light-emitting region, effective light-emitting area) of the pixel unit. The spacers are configured to support a fine metal mask during the formation of the light-emitting functional layer.

[0101] For example, the opening in the pixel definition layer is the light-emitting area of ​​the pixel unit. The light-emitting functional layer is located above the first electrode E1 of the light-emitting element 100b, and the second electrode E2 of the light-emitting element 100b is located on the light-emitting functional layer. For example, an encapsulation layer is disposed on the light-emitting element 100b. The encapsulation layer includes a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. For example, the first and third encapsulation layers are inorganic material layers, and the second encapsulation layer is an organic material layer. For example, the first electrode E1 is the anode of the light-emitting element 100b, and the second electrode E2 is the cathode of the light-emitting element 100b, but this is not limited to these examples.

[0102] Figure 11 This is a schematic diagram of a display panel provided in one embodiment of the present disclosure. Figure 12 for Figure 11 The diagram is shown in box B1. Figure 13 This is a schematic diagram of a display panel provided in one embodiment of the present disclosure. Figure 14 for Figure 13 The diagram is shown in box B2. Figure 15 This is a partial schematic diagram of a display panel provided in an embodiment of the present disclosure. Figure 16 This is a partial schematic diagram of a display panel provided in an embodiment of the present disclosure.

[0103] like Figures 11 to 16As shown, the display panel also includes a first signal bus 81 and a second signal bus 82. The first signal bus 81 is configured to provide a first initialization signal Vinit1, and the second signal bus 82 is configured to provide a second initialization signal Vinit2. The first signal bus 81 and the second signal bus 82 are insulated from each other and are configured to input different initialization signals. The first signal bus 81 and the second signal bus 82 are insulated from each other to provide signals separately. The first signal bus 81 and the second signal bus 82 are configured to provide different signals. The second initialization signal Vinit2 is greater than the first initialization signal Vinit1, which helps to shorten the turn-on time of the second light-emitting element 40 and improve display uniformity.

[0104] For example, the width of the first signal bus 81 is greater than the width of the second signal bus 82. In some embodiments, the width of the first signal bus 81 is 20 μm, and the width of the second signal bus 82 is 10 μm. For example, in embodiments of this disclosure, the width of the trace is the dimension in the direction perpendicular to the extension direction of the trace.

[0105] For example, such as Figure 11 As shown, the distance between the second signal bus 82 and the display area R1 of the display panel is D1. For example, in some embodiments, the distance D1 is 500-600 μm, but it is not limited to this.

[0106] For example, such as Figure 11 As shown, the distance between the first signal bus 81 and the display area R1 of the display panel is D2. The distance D2 is less than the distance D1.

[0107] like Figure 11 , Figure 13 , Figure 15 and Figure 16 As shown, the first initialization signal line INT1, the second initialization signal line INT2, and the third initialization signal line INT3 are respectively connected to the first signal bus 81. Figure 11 , Figure 13 and Figure 15 As shown, the second signal bus 82 is connected to the fourth initialization signal line INT4.

[0108] For example, refer to Figure 3 and Figure 4 The orthographic projection of the pixel circuit of the second pixel unit 102 on the substrate BS does not overlap with the orthographic projection of the light-emitting element of the second pixel unit 102 on the substrate BS. That is, the orthographic projection of the second pixel circuit 20 on the substrate BS does not overlap with the orthographic projection of the second light-emitting element 40 on the substrate BS.

[0109] For example, refer to Figure 3 and Figure 4The substrate BS also includes a peripheral region R3, which is located on at least one side of the display region R0, and the pixel circuit of the second pixel unit 102 is located in the peripheral region R3. That is, the second pixel circuit 20 is located in the peripheral region R3.

[0110] For example, such as Figure 11 and Figure 13 As shown, at least a portion of the first signal bus 81 and at least a portion of the second signal bus 82 are both located in the peripheral region R3.

[0111] For example, such as Figure 11 and Figure 13 As shown, the first signal bus 81 and the second signal bus 82 are respectively connected to different pins of the integrated circuit CC. Figure 11 and Figure 13 The first pin P1 and the second pin P2 are shown. (See diagram.) Figure 11 and Figure 13 As shown, the first signal bus 81 is connected to the first pin P1 of integrated circuit CC, and the second signal bus 82 is connected to the second pin P2 of integrated circuit CC. The first pin P1 and the second pin P2 are two different pins. The first pin P1 and the second pin P2 are not connected. The first initialization signal Vinit1 and the second initialization signal Vinit2 originate from integrated circuit CC.

[0112] For example, the first signal bus 81 is closer to the display area R0 than the second signal bus 82.

[0113] For example, such as Figure 5 , Figure 7 , Figure 12 and Figure 14 As shown, the display panel also includes a second power line PL2, which is configured to provide a constant second voltage signal to the pixel circuitry. The second power line PL2 is connected to the second electrode of the light-emitting element, and at least a portion of the second signal bus 82 is located between the second power line PL2 and the display area R0. For example, the second power line PL2 is located in the peripheral area R3.

[0114] For example, such as Figure 12 and Figure 14 As shown, the first signal bus 81 is located between the second power line PL2 and the display area R0.

[0115] For example, such as Figure 12As shown, the display panel also includes a control circuit 90 located between the second power line PL2 and the display area R0. At least a portion of the first signal bus 81 is located between the control circuit 90 and the display area R0, and at least a portion of the second signal bus 82 is located between the control circuit 90 and the second power line PL2. For example, in some embodiments, to facilitate a narrow bezel, the orthographic projection of the second signal bus 82 on the substrate BS at least partially overlaps with the orthographic projection of the control circuit 90 on the substrate BS. For example, in some embodiments, to facilitate a narrow bezel, the orthographic projection of the second signal bus 82 on the substrate BS at least partially overlaps with the orthographic projection of the second power line PL2 on the substrate BS. Figure 12 As shown, in order to achieve a narrow bezel, the second signal bus 82 and the second power line PL2 overlap at least partially, and the second signal bus 82 and the control circuit 90 overlap at least partially.

[0116] For example, control circuit 90 includes circuitry with gate drive on the array (GOA circuitry).

[0117] In other embodiments, the second signal bus 82 may not overlap with the second power supply line PL2, nor with the control circuit 90.

[0118] For example, such as Figure 14 As shown, the display panel also includes a control circuit 90, which is located between the second power line PL2 and the display area R0. At least a portion of the first signal bus 81 and at least a portion of the second signal bus 82 are located between the control circuit 90 and the display area R0.

[0119] For example, such as Figure 13 As shown, the space between the second signal bus 82 and the first signal bus 81 is approximately 5-8 μm, and the distance D3 between the first signal bus 81 and the display area R0 is 30-35 μm, but not limited to this.

[0120] Figure 17 This is a schematic diagram of a first signal bus in a display panel provided according to an embodiment of the present disclosure. For example, such as... Figure 17 As shown, in order to reduce resistance and lower the load, the first signal bus 81 includes two sub-lines connected through via V01 located in the third conductive layer LY3 and the fourth conductive layer LY4, respectively. Figure 17 The first sub-line 81a located in the third conductive layer LY3 and the second sub-line 81b located in the fourth conductive layer LY4 are shown. The via V01 penetrates the fourth insulating layer ISL4.

[0121] Figure 18 This is a schematic diagram of a second signal bus 82 in a display panel provided according to an embodiment of the present disclosure. For example, as... Figure 18As shown, in order to reduce resistance and lower the load, the second signal bus 82 includes two sub-lines located in the first conductive layer LY1 and the second conductive layer LY2 respectively, connected through via V02. Figure 18 The first sub-line 82a located in the first conductive layer LY1 and the second sub-line 82b located in the second conductive layer LY2 are shown.

[0122] Of course, in some embodiments, the first signal bus 81 may also include two sub-lines connected by vias located in the first conductive layer LY1 and the second conductive layer LY2, respectively. In some embodiments, the second signal bus 82 may also include two sub-lines connected by vias located in the third conductive layer LY3 and the fourth conductive layer LY4, respectively. Of course, the layers in which the two sub-lines in the display panel provided in the embodiments of this disclosure are located are not limited to those described above, as long as the two sub-lines are located in two different conductive layers and the two sub-lines are connected by vias penetrating the two different conductive layers.

[0123] For example, the transistors in the pixel circuits of the embodiments of this disclosure are all thin-film transistors. For example, the first conductive layer LY1, the second conductive layer LY2, and the third conductive layer LY3 are all made of metallic materials. For example, the first conductive layer LY1 and the second conductive layer LY2 are formed of metallic materials such as nickel and aluminum, but are not limited thereto. For example, the third conductive layer LY3 or the fourth conductive layer LY4 is formed of materials such as titanium, molybdenum, and aluminum, but are not limited thereto. For example, the third conductive layer LY3 or the fourth conductive layer LY4 has a structure formed of three sub-layers of Ti / Al / Ti, but is not limited thereto. For example, the substrate can be a glass substrate or a polyimide substrate, but is not limited thereto, and can be selected as needed. For example, the buffer layer BL, the isolation layer BR, the first insulating layer ISL1, the second insulating layer ISL2, the third insulating layer ISL3, and the fourth insulating layer ISL4 are all made of insulating materials. At least one of the materials of the buffer layer BL, the isolation layer BR, the first insulating layer ISL1, the second insulating layer ISL2, the third insulating layer ISL3, and the fourth insulating layer ISL4 is made of an inorganic insulating material. The materials of the first electrode E1 and the second electrode E2 of the light-emitting element can be selected as needed. In some embodiments, the first electrode E1 may be at least one of a transparent conductive metal oxide and silver, but is not limited thereto. For example, the transparent conductive metal oxide includes indium tin oxide (ITO), but is not limited thereto. For example, the first electrode E1 may have a structure in which three sublayers of ITO-Ag-ITO are stacked. In some embodiments, the second electrode E2 may be a metal with low work function, and may be at least one of magnesium and silver, but is not limited thereto.

[0124] For example, in embodiments of this disclosure, the first direction X and the second direction Y are directions parallel to the main surface of the substrate, and the third direction Z is a direction perpendicular to the main surface of the substrate. The main surface of the substrate is the surface on which various components are fabricated. Figure 22 The upper surface of the substrate is its main surface. For example, the first direction X and the second direction Y intersect. Further, for example, the first direction X is perpendicular to the second direction Y. For example, the first direction X is a row direction, and the second direction Y is a column direction.

[0125] Figure 19 This is a timing signal diagram of a pixel unit in a display panel provided in an embodiment of this disclosure. The following will be combined with... Figure 5 , Figure 7 and Figure 19 The driving method for a pixel unit in a display panel provided in the embodiments of this disclosure will be described.

[0126] like Figure 19 As shown, within a frame display time period, the driving method of the pixel unit includes a first reset phase t1, data writing and threshold compensation, a second reset phase t2, and a light emission phase t3.

[0127] In the first reset phase t1, the light emission control signal EM is set to the off voltage, the reset control signal RESET is set to the on voltage, and the scan signal SCAN is set to the off voltage.

[0128] During the data writing and threshold compensation and second reset phase t2, the light emission control signal EM is set to the off voltage, the reset control signal RESET is set to the off voltage, and the scan signal SCAN is set to the on voltage.

[0129] During the light emission stage t3, the light emission control signal EM is set to the turn-on voltage, the reset control signal RESET is set to the turn-off voltage, and the scan signal SCAN is set to the turn-off voltage.

[0130] like Figure 19 As shown, the first voltage signal ELVDD, the second voltage signal ELVSS, the first initialization signal Vinit1, and the second initialization signal Vinit2 are all constant voltage signals. The first initialization signal Vinit1 is between the first voltage signal ELVDD and the second voltage signal ELVSS, and the second initialization signal Vinit2 is between the first voltage signal ELVDD and the second voltage signal ELVSS. The second initialization signal Vinit2 is greater than the first initialization signal Vinit1. It should be noted that... Figure 19 The following explanation uses the example of a constant voltage as the second initialization signal Vinit2.

[0131] For example, in some embodiments, the first initialization signal Vinit1 is a negative voltage, and the second initialization signal Vinit2 is also a negative voltage. Further, for example, the range of the first initialization signal Vinit1 is -3V to -2.5V, and the range of the second initialization signal Vinit2 is -2.5V to -2V. In one embodiment, the first initialization signal Vinit1 is -3V, and the range of the second initialization signal Vinit2 is -2.5V.

[0132] In other embodiments, the second initialization signal Vinit2 may not be a constant voltage. For example, the second initialization signal Vinit2 may include at least two voltage signals with different values ​​to eliminate the current difference between the second display area and the first display area and improve the uniformity of the image.

[0133] Figure 20 This is a schematic diagram of a second initialization signal in a display panel provided according to an embodiment of the present disclosure. For example, the second initialization signal Vinit2 can employ different voltage signals depending on whether the screen displays high grayscale, low grayscale, or a black screen. In some embodiments, the second initialization signal Vinit2 includes three voltage signals with different values. For example, as... Figure 20 As shown, the first voltage signal V1 corresponds to a high grayscale, the second voltage signal V2 corresponds to a low grayscale, and the third voltage signal V3 corresponds to a black screen. For example, the first voltage signal V1 is greater than the second voltage signal V2, and the second voltage signal V2 is greater than the third voltage signal V3. For example, in grayscale L0-L255, L0 is zero grayscale, corresponding to a black screen. In some embodiments, the boundary value between low and high grayscale can be L60, but it is not limited to this. In the embodiments of this disclosure, the boundary value between low and high grayscale can be determined as needed.

[0134] For example, in some embodiments, the range of the first voltage signal V1 is -2.3V to -2V, the range of the second voltage signal V2 is -2.5V to -2.3V, and the range of the third voltage signal V3 is -3V to -2.5V. For example, in some embodiments, the first voltage signal V1 is -2.2V, the second voltage signal V2 is -2.4V, and the third voltage signal V3 is -2.8V. Of course, the second initialization signal Vinit2 can also be divided according to other circumstances. In some embodiments, depending on whether the screen is black or not, the second initialization signal Vinit2 includes at least two voltage signals with different values.

[0135] Figure 21 This is a schematic diagram of a second initialization signal in a display panel provided according to an embodiment of the present disclosure. For example, such as... Figure 21 As shown, the fourth voltage signal V4 corresponds to a non-black screen, and the fifth voltage signal V5 corresponds to a black screen. For example, the fourth voltage signal V4 is greater than the fifth voltage signal V5. In some embodiments, the fourth voltage signal V4 ranges from -2.5V to -2V, and the fifth voltage signal V5 ranges from -3V to -2.5V. For example, in some embodiments, the fourth voltage signal V4 is -2.4V, and the fifth voltage signal V5 is -2.8V.

[0136] For example, the driving method for the display panel provided in the embodiments of this disclosure includes: providing a first initialization signal Vinit1 to the pixel circuit via a first signal bus; and providing a second initialization signal Vinit2 to the pixel circuit via a second signal bus, wherein the second initialization signal Vinit2 is greater than the first initialization signal Vinit1, so as to improve the uniformity of the display screen.

[0137] For example, in the driving method described above, the second initialization signal Vinit2 can be divided according to the screen display. The specific division method can be found in the previous description and will not be repeated here.

[0138] For example, in the embodiments of this disclosure, the turn-on voltage refers to the voltage that enables the first and second terminals of the corresponding transistor to conduct, and the turn-off voltage refers to the voltage that enables the first and second terminals of the corresponding transistor to disconnect. When the transistor is a P-type transistor, the turn-on voltage is a low voltage (e.g., 0V) and the turn-off voltage is a high voltage (e.g., 5V); when the transistor is an N-type transistor, the turn-on voltage is a high voltage (e.g., 5V) and the turn-off voltage is a low voltage (e.g., 0V). Figure 19 The driving waveforms shown are all illustrated using a P-type transistor as an example, i.e., the turn-on voltage is low (e.g., 0V) and the turn-off voltage is high (e.g., 5V).

[0139] Please refer to the following: Figure 5 , Figure 7 and Figure 19 During the first reset phase t1, the light emission control signal EM is at the off voltage, the reset control signal RESET is at the on voltage, and the scan signal SCAN is at the off voltage. At this time, the first reset transistor T6 is in the on state, while the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, and the second light emission control transistor T5 are in the off state. The first reset transistor T6 transmits the first initialization signal (initialization voltage) Vinit1 to the gate of the driving transistor T1 and stores it in the storage capacitor Cst, resetting the driving transistor T1 and erasing the data stored during the previous (previous frame) light emission.

[0140] During the data writing, threshold compensation, and second reset phase t2, the light emission control signal EM is at the off voltage, the reset control signal RESET is at the off voltage, and the scan signal SCAN is at the on voltage. At this time, the data writing transistor T2 and the threshold compensation transistor T3 are in the on state, and the second reset transistor T7 is in the on state. For the second pixel unit 102, the second reset transistor T7 of the second pixel unit 102 transmits the second initialization signal Vinit2 to the first electrode of the second light-emitting element 40 to reset the second light-emitting element 40; for the first pixel unit 101, the second reset transistor T7 of the first pixel unit 101 transmits the first initialization signal Vinit1 to the first electrode of the first light-emitting element 30 to reset the first light-emitting element 30; while the first light emission control transistor T4, the second light emission control transistor T5, and the first reset transistor T6 are in the off state. At this time, the data writing transistor T2 transmits the data signal voltage VDATA to the first electrode of the driving transistor T1, that is, the data writing transistor T2 receives the scan signal SCAN and the data signal DATA and writes the data signal DATA to the first electrode of the driving transistor T1 according to the scan signal SCAN. When threshold compensation transistor T3 is turned on, it connects driving transistor T1 into a diode structure, thereby charging the gate of driving transistor T1. After charging is complete, the gate voltage of driving transistor T1 is VDATA + Vth, where VDATA is the data signal voltage and Vth is the threshold voltage of driving transistor T1. That is, threshold compensation transistor T3 receives the scan signal SCAN and performs threshold voltage compensation on the gate voltage of driving transistor T1 according to the scan signal SCAN. During this stage, the voltage difference across the storage capacitor Cst is ELVDD - VDATA - Vth.

[0141] During the light-emitting stage t3, the light-emitting control signal EM is the turn-on voltage, the reset control signal RESET is the turn-off voltage, and the scan signal SCAN is the turn-off voltage. The first light-emitting control transistor T4 and the second light-emitting control transistor T5 are in the on state, while the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6, and the second reset transistor T7 are in the off state. The first voltage signal ELVDD is transmitted to the first terminal of the driving transistor T1 through the first light-emitting control transistor T4. The gate voltage of the driving transistor T1 remains at VDATA+Vth. The light-emitting current I flows into the light-emitting element 100b through the first light-emitting control transistor T4, the driving transistor T1, and the second light-emitting control transistor T5, causing the light-emitting element 100b to emit light. That is, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 receive the light-emitting control signal EM and control the light-emitting element 100b to emit light according to the light-emitting control signal EM. The light-emitting current I satisfies the following saturation current formula:

[0142] K(Vgs-Vth)2 =K(VDATA+Vth-ELVDD-Vth) 2 =K(VDATA-ELVDD) 2

[0143] in, μ n The channel mobility of the driving transistor is given by Cox, the channel capacitance per unit area of ​​the driving transistor T1 is given by W and L, respectively, and the channel width and channel length of the driving transistor T1 are given by Vgs, respectively. Vgs is the voltage difference between the gate and the source (i.e., the first terminal of the driving transistor T1 in this embodiment) of the driving transistor T1.

[0144] As can be seen from the above formula, the current flowing through the light-emitting element 100b is independent of the threshold voltage of the driving transistor T1. Therefore, this pixel circuit structure compensates for the threshold voltage of the driving transistor T1 very well.

[0145] For example, the proportion of the duration of the light-emitting phase t3 to the display time of one frame can be adjusted. Thus, the brightness can be controlled by adjusting the proportion of the duration of the light-emitting phase t3 to the display time of one frame. For example, the proportion of the duration of the light-emitting phase t3 to the display time of one frame can be adjusted by controlling the scan drive circuit 103 in the display panel or by an additional drive circuit.

[0146] At least one embodiment of this disclosure provides a display device including any of the above-described display panels.

[0147] Figure 22 and Figure 23 This is a schematic diagram of a display device provided according to an embodiment of the present disclosure. Figure 22 and Figure 23 As shown, the sensor SS is located on one side of the display panel DS and within the second display area R2. Ambient light can be transmitted through the second display area R2 and sensed by the sensor SS. Figure 23 As shown, the side of the display panel without the sensor SS is the display side, where images can be displayed. For example, the sensor SS includes a photosensor located on one side of the display panel. In this type of display device, hardware such as photosensors (e.g., cameras) can be placed in the light-transmitting display area, eliminating the need for punch holes and facilitating the realization of a true full-screen display.

[0148] For example, the second display area R2 can be rectangular, and the area of ​​the sensor SS projected onto the substrate BS can be less than or equal to the area of ​​the inscribed circle of the second display area R2. That is, the size of the area where the sensor SS is located can be less than or equal to the size of the inscribed circle of the second display area R2. For example, if the size of the area where the sensor SS is located is equal to the size of the inscribed circle of the second display area R2, then the shape of the area where the sensor SS is located can be circular. Of course, in some embodiments, the second display area R2 can also be other shapes besides rectangles, such as circles or ellipses.

[0149] For example, the display device is a full-screen display device with an under-display camera. For example, the display device includes OLED or products that include OLED. For example, the display device includes any product or component with display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigator, which contains the above-mentioned display panel.

[0150] For example, embodiments of this disclosure are not limited to Figure 5 and Figure 7 The specific pixel circuit shown can be replaced with other pixel circuits capable of compensating for the driving transistors. Based on the description and teachings of this disclosure, other configurations that can be readily conceived by those skilled in the art without inventive effort are all within the scope of this disclosure.

[0151] The above description uses a 7T1C pixel circuit as an example, and the embodiments of this disclosure include, but are not limited to, this. It should be noted that the embodiments of this disclosure do not limit the number of thin-film transistors or capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display panel may also be a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure; the embodiments of this disclosure do not limit this. Of course, the display panel may also include a pixel circuit with fewer than 7 transistors.

[0152] In embodiments of this disclosure, elements located in the same layer may be formed from the same film layer using the same patterning process. For example, elements located in the same layer may be located on the surface of the same element that is away from the substrate.

[0153] It should be noted that, for clarity, the thickness of layers or regions is magnified in the drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "below" another element, the element may be located "directly" on or "below" the other element, or there may be intermediate elements present.

[0154] In the embodiments of this disclosure, the patterning or patterning process may include only photolithography, or it may include both photolithography and etching steps, or it may include other processes such as printing or inkjet printing to form a predetermined pattern. Photolithography refers to processes including film formation, exposure, and development, using photoresist, photomasks, and exposure machines to form patterns. The appropriate patterning process can be selected based on the structure formed in the embodiments of this disclosure.

[0155] Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0156] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, comprising: a substrate substrate comprising a display area, the display area comprising a first display area and a second display area, the first display area being located at least one side of the second display area; a pixel unit located on the substrate substrate, comprising a pixel circuit and a light emitting element, the pixel circuit being configured to drive the light emitting element, the pixel circuit comprising a driving transistor, a first reset transistor and a second reset transistor, the first reset transistor being connected to a gate of the driving transistor and being configured to reset the gate of the driving transistor, the second reset transistor being connected to a first electrode of the light emitting element and being configured to reset the first electrode of the light emitting element; the pixel unit comprising a first pixel unit and a second pixel unit, the pixel circuit of the first pixel unit being located in the first display area and at least partially overlapping with the light emitting element of the first pixel unit, the light emitting element of the second pixel unit being located in the second display area, the pixel circuit of the second pixel unit being located outside the second display area, the pixel circuit of the second pixel unit being connected to the light emitting element of the second pixel unit through a conductive wire; a first initialization signal line connected to a first electrode of the first reset transistor in the first pixel unit; a second initialization signal line connected to a first electrode of the second reset transistor in the first pixel unit; a third initialization signal line connected to a first electrode of the first reset transistor in the second pixel unit; a fourth initialization signal line connected to a first electrode of the second reset transistor in the second pixel unit; a first signal bus configured to provide a first initialization signal, the first initialization signal line, the second initialization signal line and the third initialization signal line being connected to the first signal bus respectively; a second signal bus configured to provide a second initialization signal and connected to the fourth initialization signal line, wherein the first signal bus and the second signal bus are insulated from each other to be configured to input different initialization signals.

2. The display panel of claim 1, wherein, A normal projection of the pixel circuit of the second pixel unit on the substrate substrate does not overlap with a normal projection of the light emitting element of the second pixel unit on the substrate substrate.

3. The display panel of claim 1, wherein, The substrate substrate further comprises a peripheral area, the peripheral area being located at least one side of the display area, the peripheral area being a non-display area, the pixel circuit of the second pixel unit being located in the peripheral area.

4. The display panel of claim 3, wherein, At least a part of the first signal bus and at least a part of the second signal bus are both located in the peripheral area.

5. The display panel of claim 1, wherein, The second initialization signal is greater than the first initialization signal.

6. The display panel of claim 1, further comprising an integrated circuit, wherein, The first signal bus and the second signal bus are connected to different pins of the integrated circuit respectively.

7. The display panel of claim 1, wherein, The first signal bus is closer to the display area than the second signal bus.

8. The display panel of any of claims 1-7, further comprising a power line, wherein, The power line is configured to provide a constant voltage signal to the pixel circuit, the power line being connected to a second electrode of the light emitting element, at least a part of the second signal bus being located between the power line and the display area.

9. The display panel of claim 8, wherein, At least a portion of the first signal bus is located between the power line and the display area.

10. The display panel of claim 8, further comprising a control circuit, wherein, The control circuit is located between the power line and the display area, and the first signal bus and the second signal bus are located between the control circuit and the display area.

11. The display panel of claim 8, further comprising a control circuit, wherein, The control circuit is located between the power line and the display area, the first signal bus is located between the control circuit and the display area, and the second signal bus is located between the control circuit and the power line.

12. The display panel of claim 11, wherein, A projection of the second signal bus on the substrate substrate at least partially overlaps a projection of the control circuit on the substrate substrate.

13. The display panel of claim 11 or 12, wherein, A projection of the second signal bus on the substrate substrate at least partially overlaps a projection of the power line on the substrate substrate.

14. The display panel of any of claims 1-7, wherein, The second signal bus includes two sub-lines connected by a via between a first conductive layer and a second conductive layer, respectively.

15. The display panel of any of claims 1-7, wherein, The first signal bus includes two sub-lines connected by a via between a third conductive layer and a fourth conductive layer, respectively.

16. The display panel of any one of claims 1-7, wherein, The first signal bus has a width greater than a width of the second signal bus.

17. The display panel of any of claims 1-7, wherein, The second signal bus is configured to provide the second initialization signal, and the second initialization signal includes at least two voltage signals with different values.

18. A display device comprising the display panel according to any one of claims 1-17.

19. The display device of claim 18, further comprising a photosensor, wherein, The light sensor is located on a side of the display panel.

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