A high-precision trimming circuit applicable to a voltage reference circuit

Abstract

The present invention discloses a high-precision trimming circuit applicable to a voltage reference circuit. A control signal is input externally through a bias circuit. The output end of the locking circuit is connected to the input end of the fuse circuit array. The output end of the bias circuit is respectively connected to the input ends of the D flip-flop array, the locking circuit and the fuse circuit. The output end of the D flip-flop array is connected to the input ends of the fuse circuit and the locking circuit. The output end of the fuse circuit is connected to the input end of the output voltage voltage-dividing network. The feedback signal at the output end of the output voltage voltage-dividing network is connected to the input end of the output voltage voltage-dividing network. By controlling the D flip-flop array and the fuse circuit array through the bias circuit, the resistance connected in the output voltage voltage-dividing network is changed, so as to correct the output voltage value on the premise of retaining the temperature drift characteristic and noise characteristic of the output voltage.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuits, and particularly relates to a high-precision trimming circuit applicable to a voltage reference circuit. Background Art

[0002] The pre-stage circuit of a low-temperature-drift reference can generate an output voltage reference value with an error in the voltage fluctuation value within 1.5 mV in the full temperature range of -55°C to 125°C. However, due to reasons such as the temperature coefficient of the resistor, the offset and mismatch of the operational amplifier, the package stress, and the production error between batches, random errors will be introduced. The output accuracy and performance can be improved by trimming the absolute value of the output voltage.

[0003] Currently, the existing mainstream integrated circuit trimming technologies include laser trimming, fuse trimming, etc.

[0004] Among them, the basic principle of laser trimming is to focus the laser beam on the resistor film through a lens. Under the action of instantaneous high temperature, the resistor film is vaporized. Under the action of continuous laser pulses, as the beam moves, a cut is formed on the resistor film, thereby changing the conductive area of the resistor (i.e., the number of resistor squares), achieving the purpose of changing the resistor. This method has a high cost and complex operation, and is not suitable for use in large-scale production circuits.

[0005] When trimming by fusing a metal fuse, a large external current is used to fuse the fuse, and the operation needs to be carried out before the circuit packaging. Although this method has a simple operation, it is labor-consuming, occupies chip area, and has a high cost. Summary of the Invention

[0006] The purpose of the present invention is to provide a high-precision trimming circuit applicable to a voltage reference circuit to overcome the problems of high cost, complex operation, and occupation of chip area existing in the existing integrated circuit trimming technologies.

[0007] To solve the above problems, the present invention adopts the following technical solutions:

[0008] A high-precision trimming circuit applicable to a voltage reference circuit includes a bias circuit, a D flip-flop array, a fuse circuit array, and an output voltage voltage division network. The bias circuit is externally connected to a control signal input. The fuse circuit array includes a fuse circuit and a locking circuit. The output end of the locking circuit is connected to the input end of the fuse circuit. The output end of the bias circuit is respectively connected to the input end of the D flip-flop array, the input end of the locking circuit, and the input end of the fuse circuit. The output end of the D flip-flop array is connected to the input end of the fuse circuit and the input end of the locking circuit. The output end of the fuse circuit is connected to the input end of the output voltage voltage division network. The input end of the output voltage voltage division network is further connected to a reference circuit output voltage feedback signal L1, and the reference circuit output voltage feedback signal L1 is a voltage reference signal from the reference circuit.

[0009] Further, the fuse circuit array includes 5 fuse circuits and 1 locking circuit. The fuse circuit includes a first resistor R1, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, and a fourth PMOS transistor P4. The gate of the first PMOS transistor P1 is connected to the output terminal of a three-input NAND gate. The source of the first PMOS transistor P1 is connected to the sources of the second PMOS transistor P2, the third PMOS transistor P3, and the fourth PMOS transistor P4, and the source of the first PMOS transistor P1 is connected to the power supply VCC. The gates of the second PMOS transistor P2, the third PMOS transistor P3, and the fourth PMOS transistor P4 are connected to the output terminal of a bias circuit.

[0010] Further, the inputs of the three-input NAND gate are respectively the output control signal in1 of the bias circuit, the output control signal in2 of the corresponding D flip-flop, and the output L4 of the locking circuit.

[0011] Further, one end of the first resistor R1 is connected to the drain of the first PMOS transistor P1, the drain of the second PMOS transistor P2, and the gate of the first NMOS transistor N1. The drain of the first NMOS transistor N1 is connected to the drain of the third PMOS transistor P3 and the gate of the second NMOS transistor N2. The other end of the first resistor R1, the source of the first NMOS transistor N1, and the source of the second NMOS transistor N2 are grounded. The drain of the third PMOS transistor P3 is connected to the drain of the first NMOS transistor N1. The drain of the fourth PMOS transistor P4 is connected to the drain of the second NMOS transistor N2.

[0012] Further, the locking circuit includes a second resistor R2, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, and a third NMOS transistor N3. The gate of the fifth PMOS transistor P5 is connected to the output terminal of a two-input NAND gate, the output terminal of the bias circuit, and the output terminal of the D flip-flop array. The source of the fifth PMOS transistor P5 is connected to the sources of the sixth PMOS transistor P6, the seventh PMOS transistor P7, and the power supply VCC. The drain of the fifth PMOS transistor P5 is connected to the second resistor R2, the drain of the sixth PMOS transistor P6, and the gate of the third NMOS transistor N3. The other end of the second resistor R2 is grounded.

[0013] Further, the inputs of the two-input NAND gate are respectively the output control signal in1 of the bias circuit and the output control signal in2 of the corresponding D flip-flop.

[0014] Further, the gates of the sixth PMOS transistor P6 and the seventh PMOS transistor P7 are connected to the output terminal of the bias circuit. The drain of the seventh PMOS transistor P7 is connected to the drain of the third NMOS transistor N3.

[0015] Further, the output voltage dividing network includes a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, and a third resistor R3. One end of the third resistor R3 is connected to the output terminal of the entire trimming circuit. The output terminal of the entire trimming circuit is further connected to a sixteenth resistor R16, and the other end of the sixteenth resistor R16 is connected to a seventeenth resistor R17.

[0016] Further, the other end of the third resistor R3 is connected to a fourth resistor R4 and a fifth resistor R5. The other end of the fourth resistor R4 is connected to the drain of the fourth NMOS transistor N4. The source of the fourth NMOS transistor N4 is connected to a reference circuit output voltage feedback signal L1 and a seventh resistor R7. The other end of the seventh resistor R7 is connected to an eighth resistor R8, and the other end of the eighth resistor R8 is connected to the drain of the fifth NMOS transistor N5.

[0017] Further, the source of the fifth NMOS transistor N5 is connected to the drain of the sixth NMOS transistor N6 through a tenth resistor R10. The source of the sixth NMOS transistor N6 is connected to the drain of the seventh NMOS transistor N7 through a twelfth resistor R12. The source of the seventh NMOS transistor N7 is connected to the gate of the eighth NMOS transistor N8 through a fourteenth resistor R14. The source of the eighth NMOS transistor N8 is connected to the seventeenth resistor R17, and the other end of the seventeenth resistor R17 is grounded.

[0018] Compared with the prior art, the present invention has the following beneficial technical effects:

[0019] The present invention provides a high-precision trimming circuit applicable to a voltage reference circuit. By controlling a D flip-flop array and a fusing circuit array through a bias circuit, the resistors connected in the output voltage dividing network are changed, so as to correct the output voltage value on the premise of retaining the output voltage temperature drift characteristic and noise characteristic. The present invention can realize the trimming of the output voltage of the voltage reference circuit through a hardware trimming circuit. Compared with the traditional laser trimming and trimming by fusing a metal fuse, it has the advantages of low cost, no need for additional operations, and small chip space occupation.

[0020] Preferably, after the trimming circuit completes trimming, the locking circuit locks the fusing circuit connected thereto, so that the subsequent bias circuit will not continue to control the trimming circuit to work, and the output of the trimming circuit will no longer change, thereby ensuring that the trimmed output voltage remains stable and will not interfere with the performance of the entire reference circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic structural diagram of a high-precision trimming circuit applicable to a voltage reference circuit in an embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram of the fuse circuit array in the high-precision trimming circuit that can be used in the voltage reference circuit in the embodiment of the present invention.

[0023] Figure 3 This is a structural diagram of the fuse circuit in the fuse circuit array in the embodiment of the present invention.

[0024] Figure 4 This is a structural diagram of the locking circuit in the fuse circuit array in the embodiment of the present invention.

[0025] Figure 5 This is an equivalent circuit diagram of the output voltage divider network in the high-precision trimming circuit that can be used in the voltage reference circuit in the embodiment of the present invention. Detailed implementation manners

[0026] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0027] As Figure 1 、 Figure 2 shown, a high-precision trimming circuit that can be used in a voltage reference circuit includes a bias circuit, a D flip-flop array, a fuse circuit array, and an output voltage divider network. The bias circuit is externally connected to control signal inputs IC1, IC2, and IC3. The output of the bias circuit is connected to the fuse circuit array and the D flip-flop array. The fuse circuit array includes a fuse circuit and a locking circuit. The output signals of the bias circuit include L2 and L3. The output terminal of the bias circuit is respectively connected to the input terminal of the D flip-flop array, the input terminal of the fuse circuit, and the input terminal of the locking circuit. The output terminal of the D flip-flop array is respectively connected to the input terminals of the fuse circuit and the locking circuit. The output terminal of the locking circuit is connected to the input terminal of the fuse circuit. The output terminal of the fuse circuit is connected to the input terminal of the output voltage divider network. The output voltage feedback signal L1 of the reference circuit is a voltage reference value with low temperature drift characteristics from the reference circuit and is connected to the input terminal of the output voltage divider network.

[0028] Specifically, as Figures 2 - 4, the fuse circuit array includes 5 fuse circuits U1 and 1 lock circuit U2. The output signals of the fuse circuits are L5, L6, L7, L8, and L9, and the output signal of the lock circuit is L4. Among them, the gate of the first PMOS transistor P1 of the fuse circuit U1 is connected to the output of a three-input NAND gate with the output control signal in1 of the bias circuit, the output control signal in2 of the corresponding D flip-flop, and the output L4 of the lock circuit U2 as inputs. The source of the first PMOS transistor P1 is connected to the sources of the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, and the power supply VCC; the drain of the first PMOS transistor P1 is connected to the drain of the second PMOS transistor P2, the gate of the first NMOS transistor N1, and one end of the first resistor R1; the other end of the first resistor R1 is connected to the source of the first NMOS transistor N1, the source of the second NMOS transistor N2, and the ground; the gate of the second PMOS transistor P2 is connected to the output L2 of the bias circuit; the gates of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected to the output L3 of the bias circuit; the drain of the third PMOS transistor P3 is connected to the drain of the first NMOS transistor N1; the drains of the fourth PMOS transistor P4 and the second NMOS transistor N2 are connected to the output terminal of the fuse circuit U1.

[0029] As Figures 2 - 4 shown, the gate of the fifth PMOS transistor P5 of the lock circuit U2 is connected to the output of a two-input NAND gate with the output control signal in1 of the bias circuit and the output control signal in2 of the corresponding D flip-flop as inputs. The source of the fifth PMOS transistor P5 is connected to the sources of the sixth PMOS transistor P6 and the seventh PMOS transistor P7 and the power supply VCC; the drain of the fifth PMOS transistor P5, the drain of the sixth PMOS transistor P6, and the gate of the third NMOS transistor N3 are connected to one end of the second resistor R2, and the other end of R2 is grounded; the gate of the sixth PMOS transistor P6 is connected to the output L2 of the bias circuit; the gate of the seventh PMOS transistor P7 is connected to the output L3 of the bias circuit; the drain of the seventh PMOS transistor P7 is connected to the drain of the third NMOS transistor N3 and the output L4.

[0030] As Figure 1 , Figure 5As shown, one end of the third resistor R3 and one end of the sixteenth resistor R16 of the output voltage dividing network are connected to the output Vout of the entire trimming output network; the other end of the third resistor R3 is connected to one end of the fourth resistor R4 and the fifth resistor R5; the other end of the fourth resistor R4 is connected to the drain of the fourth NMOS transistor N4, and the gate of the fourth NMOS transistor N4 is connected to the output L5 of the fuse circuit array; the source of the fourth NMOS transistor N4 is connected to the output voltage reference signal L1 of the low-temperature drift reference circuit, one end of the seventh resistor R7, and the other end of the fifth resistor R5; the other end of the seventh resistor R7 is connected to one end of the eighth resistor R8 and one end of the ninth resistor R9; the other end of the eighth resistor R8 is connected to the drain of the fifth NMOS transistor N5; the gate of the fifth NMOS transistor N5 is connected to the output L6 of the fuse circuit array; the source of the fifth NMOS transistor N5 is connected to one end of the tenth resistor R10, the other end of the ninth resistor R9, and one end of the eleventh resistor R11; the other end of the tenth resistor R10 is connected to the drain of the sixth NMOS transistor N6; the gate of the sixth NMOS transistor N6 is connected to the output L7 of the fuse circuit array; the source of the sixth NMOS transistor N6 is connected to one end of the twelfth resistor R12, the other end of the eleventh resistor R11, and one end of the thirteenth resistor R13; the other end of the twelfth resistor R12 is connected to the drain of the seventh NMOS transistor N7; the gate of the seventh NMOS transistor N7 is connected to the output L8 of the fuse circuit array; the source of the seventh NMOS transistor N7 is connected to one end of the fourteenth resistor R14, the other end of the thirteenth resistor R13, and one end of the fifteenth resistor R15; the other end of the fourteenth resistor R14 is connected to the drain of the eighth NMOS transistor N8; the gate of the eighth NMOS transistor N8 is connected to the output L9 of the fuse circuit array; the source of the eighth NMOS transistor N8 is connected to the other end of the fifteenth resistor R15, the other end of the sixteenth resistor R16, and one end of the seventeenth resistor R17; the other end of the seventeenth resistor R17 is connected to the ground.

[0031] The working principles of each module are specifically analyzed below;

[0032] The reference circuit output voltage feedback signal L1 is a voltage signal with a voltage error within 1.5 mV within the temperature difference of -55°C to 125°C from other parts of the reference circuit. The circuit output Vout is the voltage signal obtained by L1 passing through the output voltage dividing resistor network. Due to errors introduced by reasons such as offset and package stress, there will be a deviation between Vout and the expected value, and trimming is required. The trimming method is to measure the circuit output voltage at the final test stage using a test bench, and according to the existing deviation value, edit three voltage signals and input them into three external trimming ports of the circuit. These three trimming signals, IC1, IC2, and IC3, can provide bias voltage and selection signals to the entire trimming network through the bias circuit. The selection signal can selectively fuse the resistors in the corresponding fuse circuits by enabling the D flip-flops, thereby turning on the NMOS transistors in the corresponding output voltage dividing network to change the voltage dividing resistors, and then correcting the value of the output voltage Vout.

[0033] After trimming is completed, the signal controls the last D flip-flop to enable the locking circuit, locking the outputs of the previous 5 fuse circuits. That is, the output of the circuit will no longer be affected by the signals input through the trimming signal ports; after trimming is completed, during the normal operation of the circuit, the electrical signals of the trimming network will no longer change.

[0034] The inputs of the bias circuit are IC1, IC2, and IC3, and the output of the bias circuit is connected to the fuse circuit array and the D flip-flop array. Configuring appropriate bias inputs can selectively turn on the fuse circuits by controlling the outputs of each D flip-flop. When the output of the D flip-flop is high, the resistor in the corresponding fuse circuit can be fused, that is, the output of the fuse circuit changes from low to high, and the gate voltage of the NMOS transistor in the corresponding output voltage dividing network changes from low to high and is turned on. At this time, the resistor in series with this NMOS transistor is connected.

[0035] in1, in2, and L4 are the inputs of a three-input NAND gate. When in1, in2, and L4 are not all high at the same time, the output of the three-input NAND gate is high, the first PMOS transistor P1 is turned off, and the output signal L2 of the bias circuit can make the second PMOS transistor P2 of the fuse circuit weakly conductive. Therefore, the pulling-down ability of the first resistor R1 on the gate potential of the first NMOS transistor N1 is greater than the pulling-up ability of the weakly conductive second PMOS transistor P2 on this potential, and the gate potential of the first NMOS transistor N1 is low and it is not conductive; the output signal L3 of the bias circuit turns on the third PMOS transistor P3 and the fourth PMOS transistor P4; since the gate potential of the second NMOS transistor N2 is high due to the third PMOS transistor P3 being on and the first NMOS transistor N1 being off, the second NMOS transistor N2 is turned on; the aspect ratio of the second NMOS transistor N2 is set to be greater than that of the fourth PMOS transistor P4 and the electron mobility is greater than the hole mobility. Therefore, the pulling-down ability of the second NMOS transistor N2 on the output potential of the fuse circuit is greater than the pulling-up ability of the fourth PMOS transistor P4 on this potential. At this time, although the second NMOS transistor N2 and the fourth PMOS transistor P4 are turned on at the same time, the potential at the output end of the fuse circuit is pulled to a low level, that is, when the first resistor R1 is not blown, the output of the fuse circuit U1 is low.

[0036] When the three inputs In1, in2, and L4 of the fuse circuit U1 are all high at the same time, the first PMOS transistor P1 is turned on, and the large current flowing through it after being turned on will permanently blow the first resistor R1. When the first resistor R1 is blown, the weakly conductive second PMOS transistor P2 pulls the gate voltage of the first NMOS transistor N1 to a high level, turning on the first NMOS transistor N1. Since the aspect ratio of the first NMOS transistor N1 is greater than that of the third PMOS transistor P3 and the electron mobility is greater than the hole mobility, when the two transistors are turned on at the same time, the first NMOS transistor N1 pulls the gate potential of the second NMOS transistor N2 to a low potential, turning off the second NMOS transistor N2. At this time, the fourth PMOS transistor P4 that is turned on will pull the output of the fuse circuit U1 to a high potential.

[0037] Before the trimming of the locking circuit U2 ends, its output signal L4 is constantly high. After its fuse resistor, that is, the second resistor R2, is open-circuited, the output L4 is locked to low. At the same time, L4 is connected to the three-input terminals of all the previous five fuse circuits, locking the outputs of all the fuse circuits. The subsequent levels connected to 1C1, 1C2, and 1C3 will not activate the trimming circuit, that is, the output voltage is fixed.

[0038] The control of the D flip-flop array and the fuse circuit array through the bias circuit can select five NMOS transistors in the output voltage voltage division network to change the resistance connected to the voltage division network, so as to correct the output voltage value on the premise of retaining the temperature drift characteristics and noise characteristics of the output voltage. That is, when the fusible resistor in the fuse circuit U1 is fused, the output of the fuse circuit changes from low to high, selects the corresponding NMOS transistor, and opens the resistor in series with it, thereby changing the absolute value of the output voltage Vout.

[0039] As mentioned above, only the preferred specific embodiments of the present invention are described, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A high-precision trimming circuit applicable to a voltage reference circuit, characterized in that It includes a bias circuit, a D flip-flop array, a fuse circuit array, and an output voltage divider network. The bias circuit is externally connected to a control signal input. The fuse circuit array includes a fuse circuit and a locking circuit. The output end of the locking circuit is connected to the input end of the fuse circuit. The output end of the bias circuit is respectively connected to the input end of the D flip-flop array, the input end of the locking circuit, and the input end of the fuse circuit. The output end of the D flip-flop array is connected to the input end of the fuse circuit and the input end of the locking circuit. The output end of the fuse circuit is connected to the input end of the output voltage divider network. The input end of the output voltage divider network is also connected to the output voltage feedback signal L1 of the reference circuit, and the output voltage feedback signal L1 of the reference circuit is a voltage reference signal from the reference circuit. The fuse circuit array includes 5 fuse circuits and 1 locking circuit. The fuse circuit includes a first resistor R1, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, and a fourth PMOS transistor P4. The gate of the first PMOS transistor P1 is connected to the output end of a three-input NAND gate. The source of the first PMOS transistor P1 is connected to the sources of the second PMOS transistor P2, the third PMOS transistor P3, and the fourth PMOS transistor P4. The source of the first PMOS transistor P1 is connected to the power supply VCC. The gates of the second PMOS transistor P2, the third PMOS transistor P3, and the fourth PMOS transistor P4 are connected to the output end of the bias circuit. The inputs of the three-input NAND gate are respectively the output control signal in1 of the bias circuit, the output control signal in2 of the corresponding D flip-flop, and the output L4 of the locking circuit. One end of the first resistor R1 is connected to the drain of the first PMOS transistor P1, the drain of the second PMOS transistor P2, and the gate of the first NMOS transistor N1. The drain of the first NMOS transistor N1 is connected to the drain of the third PMOS transistor P3 and the gate of the second NMOS transistor N2. The other end of the first resistor R1, the source of the first NMOS transistor N1, and the source of the second NMOS transistor N2 are grounded. The drain of the third PMOS transistor P3 is connected to the drain of the first NMOS transistor N1. The drain of the fourth PMOS transistor P4 is connected to the drain of the second NMOS transistor N2. The locking circuit includes a second resistor R2, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, and a third NMOS transistor N3. The gate of the fifth PMOS transistor P5 is connected to the output end of a two-input NAND gate, which is connected to the output end of the bias circuit and the output end of the D flip-flop array. The source of the fifth PMOS transistor P5 is connected to the sources of the sixth PMOS transistor P6, the seventh PMOS transistor P7, and the power supply VCC. The drain of the fifth PMOS transistor P5 is connected to the second resistor R2, the drain of the sixth PMOS transistor P6, and the gate of the third NMOS transistor N3. The other end of the second resistor R2 is grounded. The inputs of the two-input NAND gate are respectively the output control signal in1 of the bias circuit and the output control signal in2 of the corresponding D flip-flop. The gates of the sixth PMOS transistor P6 and the seventh PMOS transistor P7 are connected to the output terminal of the bias circuit, and the drain of the seventh PMOS transistor P7 is connected to the drain of the third NMOS transistor N3.

2. The high-precision trimming circuit applicable to a voltage reference circuit according to claim 1, wherein The output voltage dividing network includes a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, and a third resistor R3. One end of the third resistor R3 is connected to the output terminal of the entire trimming circuit. The output terminal of the entire trimming circuit is also connected to a sixteenth resistor R16, and the other end of the sixteenth resistor R16 is connected to a seventeenth resistor R17.

3. The high-precision trimming circuit applicable to a voltage reference circuit according to claim 2, wherein The other end of the third resistor R3 is connected to a fourth resistor R4 and a fifth resistor R5. The other end of the fourth resistor R4 is connected to the drain of the fourth NMOS transistor N4. The source of the fourth NMOS transistor N4 is connected to a reference circuit output voltage feedback signal L1 and a seventh resistor R7. The other end of the seventh resistor R7 is connected to an eighth resistor R8, and the other end of the eighth resistor R8 is connected to the drain of the fifth NMOS transistor N5.

4. A high-precision trimming circuit applicable to a voltage reference circuit according to claim 2, characterized in that, The source of the fifth NMOS transistor N5 is connected to the drain of the sixth NMOS transistor N6 through a tenth resistor R10. The source of the sixth NMOS transistor N6 is connected to the drain of the seventh NMOS transistor N7 through a twelfth resistor R12. The source of the seventh NMOS transistor N7 is connected to the gate of the eighth NMOS transistor N8 through a fourteenth resistor R14. The source of the eighth NMOS transistor N8 is connected to the seventeenth resistor R17, and the other end of the seventeenth resistor R17 is grounded.

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