Hierarchical layout method and device of directed graph, electronic equipment and storage medium

Abstract

The application relates to the field of artificial intelligence, and provides a directed graph hierarchical layout method and device, electronic equipment and a storage medium. After obtaining directed weight information of a directed graph, a first hierarchical graph is constructed according to the directed weight information, loop elimination is performed on a loop in the first hierarchical graph, a second hierarchical graph without a loop is obtained, then network breaking is performed on the second hierarchical graph, an initial hierarchical tree without a network structure is obtained, finally, the positions of nodes in the hierarchical tree and the branch widths of the nodes are determined, two nodes with a parent-child relationship in the initial hierarchical tree are connected according to the positions of the nodes and the branch widths of the nodes, a target hierarchical tree is obtained, and the hierarchical layout of the directed graph is completed. The application does not use a cross elimination algorithm, directly obtains the branch width when generating the hierarchical tree, and the lines shuttle in the branch gap, so that node crossing is not generated, the application is easy to implement, and the layout efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence technology, and specifically to a method, apparatus, electronic device, and storage medium for hierarchical layout of directed graphs. Background Technology

[0002] Graphs are a common data structure and representation, and they are frequently used in visualization to show related data. When visualizing graphs, it is often necessary to automatically lay them out.

[0003] However, in the process of realizing this invention, the inventors discovered that in the prior art, the layout efficiency for graphs is low, and most of them are only applicable to acyclic graphs, and cannot be applied to circular graphs. Summary of the Invention

[0004] In view of the above, it is necessary to propose a hierarchical layout method, device, electronic device and storage medium for directed graphs, which can not only reflect the hierarchical structure in a topology graph with a ring network structure, but also improve the layout efficiency.

[0005] A first aspect of the present invention provides a hierarchical layout method for a directed graph, the method comprising:

[0006] In response to an instruction to lay out a directed graph, the directed weight information of the directed graph is obtained;

[0007] Construct a first-level graph based on the directed weight information of the directed graph;

[0008] Eliminate the loops in the first-level graph to obtain the second-level graph;

[0009] Disconnect the network from the second-level graph to obtain the initial hierarchical tree;

[0010] Determine the position of the nodes and the branch width of the nodes in the hierarchical tree;

[0011] Based on the position and branch width of the node, connect two nodes with a parent-child relationship in the initial hierarchical tree to obtain the target hierarchical tree.

[0012] In an optional implementation, constructing the first-level graph based on the directed weight information of the directed graph includes:

[0013] The parent node and leaf node in the directed graph are determined based on the directed weight information of the directed graph;

[0014] A node array is generated based on the node identifier of the parent node and the node identifiers of the leaf nodes of the parent node, and the node array is stored in the parent node;

[0015] Construct a first-level graph based on the parent node, the leaf node, and the hierarchy of the leaf nodes.

[0016] In an optional implementation, constructing the first hierarchical graph based on the parent node, the leaf node, and the hierarchy of the leaf nodes includes:

[0017] Calculate the number of parent nodes;

[0018] Determine whether the quantity is 1;

[0019] When the quantity is 1, the parent node is determined as the root node in the first level graph;

[0020] When the number is greater than 1, a pseudo node is generated and the pseudo node is used as the root node of the multiple parent nodes in the first level graph.

[0021] In an optional implementation, the step of eliminating loops in the first-level graph to obtain the second-level graph includes:

[0022] Initialize the link path array;

[0023] Traverse the graph from the root node of the first level along the direction of the leaf nodes;

[0024] For each node visited, determine whether the visited node is in the link path array;

[0025] When it is determined that the traversed node is not in the link path array, the link path array is updated according to the traversed node, and the leaf nodes of the node are traversed again to determine whether the traversed leaf is in the updated link path array.

[0026] When it is determined that the traversed node is in the link path array, the link between the traversed node and its parent node is disconnected according to the node array, thus obtaining the second-level graph.

[0027] In an optional implementation, the step of disconnecting the network in the second hierarchical graph to obtain the initial hierarchical tree includes:

[0028] Traverse from the root node of the second-level graph;

[0029] For each node visited, obtain the link from the root node to that node;

[0030] When there are multiple links, calculate the link length of each link;

[0031] The link with the longest length among the multiple links is selected as the target link.

[0032] Each of the multiple links, except for the target link, is compared with the target link from the end to the beginning to obtain the different nodes in each link from the target link;

[0033] Based on the node array, the links between different nodes in each link and the leaf nodes of the different nodes are disconnected to obtain the initial hierarchical tree.

[0034] In an optional implementation, determining the position of a node and the branch width of the node in the hierarchical tree includes:

[0035] Starting from the root node, traverse to the target leaf node, which is the target leaf node;

[0036] Determine the first position of the target leaf node;

[0037] Based on the first position, the sibling nodes of the target leaf node are determined sequentially until the second position of the rightmost sibling node is reached;

[0038] The third position of the parent node of the target leaf node is determined based on the first position and the second position;

[0039] The branch width of the parent node is determined based on the first position, the second position, and the third position.

[0040] In an optional implementation, the step of connecting two nodes with a parent-child relationship in the initial hierarchical tree according to the position and branch width of the node to obtain the target hierarchical tree includes:

[0041] Generate a preset number of virtual nodes between two nodes that have a parent-child relationship;

[0042] The position of each virtual node is determined according to the preset coordinate calculation rules;

[0043] Connect any two adjacent virtual nodes to obtain the target hierarchical tree.

[0044] A second aspect of the present invention provides a hierarchical layout apparatus for directed graphs, the apparatus comprising:

[0045] The acquisition module is used to acquire the directed weight information of the directed graph in response to an instruction to lay out the directed graph;

[0046] A construction module is used to construct a first-level graph based on the directed weight information of the directed graph;

[0047] The loop elimination module is used to eliminate loops in the first-level graph to obtain the second-level graph.

[0048] The network disconnection module is used to disconnect the network of the second-level graph to obtain the initial level tree;

[0049] A calculation module is used to determine the position of nodes and the branch width of nodes in the hierarchical tree;

[0050] The connection module is used to connect two nodes with a parent-child relationship in the initial hierarchical tree according to the position and branch width of the node, so as to obtain the target hierarchical tree.

[0051] A third aspect of the present invention provides an electronic device including a processor and a memory, wherein the processor is configured to implement the directed graph hierarchical layout method when executing a computer program stored in the memory.

[0052] A fourth aspect of the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the hierarchical layout method for the directed graph.

[0053] After obtaining the directed weight information of a directed graph, this invention constructs a first-level graph based on this information. Since the first-level graph may contain loops (including self-loops) and mesh structures, loops in the first-level graph are eliminated to obtain a second-level graph. Then, the mesh in the second-level graph is broken to obtain an initial hierarchical tree. The obtained initial hierarchical tree contains neither loops nor mesh structures. Therefore, by determining the position and branch width of nodes in the hierarchical tree, lines can be connected between two nodes with a parent-child relationship in the initial hierarchical tree based on the node's position and branch width to obtain the target hierarchical tree, thus completing the hierarchical layout of the directed graph. This invention does not use a crossover exclusion algorithm; the branch width is obtained directly when generating the hierarchical tree. Lines pass through the gaps between branches, preventing node intersections, thus making it easy to implement and improving layout efficiency. Attached Figure Description

[0054] Figure 1 This is a flowchart of a hierarchical layout method for directed graphs provided in Embodiment 1 of the present invention.

[0055] Figure 2 This is a schematic diagram of a directed acyclic graph.

[0056] Figure 3 This is a schematic diagram of a directed cyclic graph.

[0057] Figure 4 This is a schematic diagram of generating a virtual node as the root node of a directed tree.

[0058] Figure 5 It is a schematic diagram of a hierarchical diagram with self-loops.

[0059] Figure 6 It is a schematic diagram of a hierarchical diagram with loops.

[0060] Figure 7 It is a schematic diagram of a hierarchical structure with a network structure.

[0061] Figure 8 This is a schematic diagram of a hierarchical tree.

[0062] Figure 9 This is a diagram illustrating the generation of multiple virtual nodes between two nodes that have a parent-child relationship.

[0063] Figure 10 This is a structural diagram of the directed graph hierarchical layout device provided in Embodiment 2 of the present invention.

[0064] Figure 11 This is a schematic diagram of the structure of the electronic device provided in Embodiment 3 of the present invention. Detailed Implementation

[0065] To better understand the above-mentioned objects, features, and advantages of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. Unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing an embodiment in one alternative implementation and is not intended to be limiting of the invention.

[0067] The directed graph hierarchical layout method provided in this embodiment of the invention is executed by an electronic device, and correspondingly, the directed graph hierarchical layout device runs in the electronic device.

[0068] This invention provides a standardized approach to symptom processing based on artificial intelligence (AI) technology. AI is the theory, method, technology, and application system that uses digital computers or computers-controlled machines to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to achieve optimal results.

[0069] Foundational technologies for artificial intelligence generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing, operating / interactive systems, and mechatronics. AI software technologies mainly encompass computer vision, robotics, biometrics, speech processing, natural language processing, and machine learning / deep learning.

[0070] Example 1

[0071] Graphs are a common data structure and representation, frequently used in visualization to show related data. When visualizing graphs, automatic layout is often required, and different layout methods are needed for different problems and scenarios. Hierarchical layout is often used when data has a certain hierarchical structure or sequential order; the corresponding data structure is generally a Directed Acyclic Graph (DAG). Common scenarios include flowcharts, organizational charts, and state transition diagrams. The hierarchical layout method is also known as the Sugiyama layout (S-layout). The S-layout considers layering, intersection, and balance, each of which is complex to implement. Regarding layering, if a layer is crossed, a pseudo-node is added to the corresponding layer. The creation process consumes pseudo-nodes, and they must be removed at the end. The algorithm involved is complex and resource-intensive. Regarding branching, complex algorithms are needed to swap the order of layers to reduce intersections, and even then, intersections are not guaranteed to be eliminated. Furthermore, the S-layout is only suitable for acyclic graphs and not for circular graphs. For circular graphs, the cycles need to be eliminated first, which requires a cycle elimination algorithm. The implementation of cycle elimination algorithms is very complex, making the S-layout very inefficient.

[0072] Figure 1 This is a flowchart of a hierarchical layout method for directed graphs provided in Embodiment 1 of the present invention. The hierarchical layout method for directed graphs specifically includes the following steps. Depending on different requirements, the order of the steps in this flowchart can be changed, and some steps can be omitted.

[0073] S11, in response to the instruction to lay out the directed graph, obtain the directed weight information of the directed graph.

[0074] The directed graphs in the embodiments of the present invention may include directed acyclic graphs and directed cyclic graphs.

[0075] If arrows indicate that the edges have a direction, then such a graph is called a directed graph. If a directed graph cannot be returned to a given node by traversing several edges, then the graph is a directed acyclic graph (DAG), which is a directed graph without cycles. Figure 2 As shown, this is a directed acyclic graph. Figure 2 In a graph, it is impossible to return to any given node by traversing any number of edges from that node. If a directed graph allows a return path from any given node to that node by traversing any number of edges, then the graph is a directed graph with a cycle. For example... Figure 3 As shown, this is a directed graph with cycles. Figure 3A path starts from node B, travels to node D, passes through node E, and returns to node B, forming a loop. If... Figure 3 If the direction of the edge from node E to node B is changed to be from node B to node E, it becomes a directed acyclic graph.

[0076] Users can upload directed graphs locally, to a server, or to a blockchain. Correspondingly, electronic devices can retrieve directed graphs locally, from a server, or from the blockchain. Once a directed graph is retrieved, the electronic device triggers an instruction to perform a hierarchical layout of the retrieved graph and, in response to this instruction, obtains the directed weight information of the graph.

[0077] The directed weight information may include, but is not limited to, node identifiers, edge directions between nodes, and node widths. A node identifier is a string that uniquely identifies a node, and a node width refers to the width of the string representing the node. For example, if the string for node A is "company," then the node width for node A can be 7; if the string for node A is "department," then the node width for node A can be 10.

[0078] S12, construct a first-level graph based on the directed weight information of the directed graph.

[0079] After obtaining the directed weight information of the directed graph, the electronic device establishes a first-level graph with a hierarchical structure based on the directed weight information.

[0080] In an optional implementation, constructing the first-level graph based on the directed weight information of the directed graph includes:

[0081] The parent node and leaf node in the directed graph are determined based on the directed weight information of the directed graph;

[0082] A node array is generated based on the node identifier of the parent node and the node identifiers of the leaf nodes of the parent node, and the node array is stored in the parent node;

[0083] Construct a first-level graph based on the parent node, the leaf node, and the hierarchy of the leaf nodes.

[0084] In a directed graph, arrows have direction, pointing from one node to another. The number of arrows pointing to a node is its in-degree, and the number of arrows pointing out of a node is its out-degree. Electronic devices determine the in-degree and out-degree of each node based on the edge directions in the directed weight information, designating nodes with an in-degree of zero as parent nodes. Nodes pointed to by parent nodes are designated as leaf nodes, and nodes pointed to by leaf nodes are designated as leaf nodes.

[0085] like Figure 3As shown, Figure 3 The nodes in the array are labeled A, B, C, D, and E. Since node A has an in-degree of zero, it is designated as the parent node. Nodes B and C, which the parent node points to, are designated as leaf nodes of node A. Node D, which node B points to, is designated as a leaf node of node B. Node E, which node D points to, is designated as a leaf node of node D. Node B, which node E points to, is designated as a leaf node of node E. Therefore, the node array stored in node A is [A:B,C], in node B is [B:D], in node C is [C:], in node D is [D:E], and in node E is [E:B].

[0086] It should be understood that the parent node in this implementation can be one or more.

[0087] In an optional implementation, constructing the first hierarchical graph based on the parent node, the leaf node, and the hierarchy of the leaf nodes includes:

[0088] Calculate the number of parent nodes;

[0089] Determine whether the quantity is 1;

[0090] When the quantity is 1, the parent node is determined as the root node in the first level graph;

[0091] When the number is greater than 1, a pseudo node is generated and the pseudo node is used as the root node of the multiple parent nodes in the first level graph.

[0092] The purpose of this invention is to hierarchically arrange a directed graph to obtain a directed tree. Since a directed tree can only have one root node, when the number of parent nodes in the first-level graph is one, this parent node can be used as the root node of the first-level graph, which is also the root node of the subsequently generated directed tree. However, when there are multiple parent nodes, a virtual node needs to be generated as the root node of these multiple parent nodes; that is, this virtual node is forged as the root node of the subsequently generated directed tree.

[0093] like Figure 4 As shown in the diagram, there are two parent nodes A and F. A virtual node is generated to serve as the root node of the directed tree.

[0094] S13, Eliminate loops in the first-level graph to obtain the second-level graph.

[0095] The electronic device traverses the first-level graph and cuts the loops in the first-level graph, thereby eliminating the loops in the first-level graph and obtaining the second-level graph.

[0096] The loop also includes self-loops.

[0097] In an optional implementation, the step of eliminating loops in the first-level graph to obtain the second-level graph includes:

[0098] Initialize the link path array;

[0099] Traverse the graph from the root node of the first level along the direction of the leaf nodes;

[0100] For each node visited, determine whether the visited node is in the link path array;

[0101] When it is determined that the traversed node is not in the link path array, the link path array is updated according to the traversed node, and the leaf nodes of the node are traversed again to determine whether the traversed leaf is in the updated link path array.

[0102] When it is determined that the traversed node is in the link path array, the link between the traversed node and its parent node is disconnected according to the node array, thus obtaining the second-level graph.

[0103] The link path array initialized by the electronic device can be an empty array. Starting from the root node, the electronic device traverses the first-level graph using a depth-first recursive approach along the leaf nodes. After reaching the root node, the electronic device updates the initialized link path array, and then continues the depth-first recursive approach from the root node along the leaf nodes. At each node reached, it checks whether the node is in the updated link path array.

[0104] If the node is not in the updated link path array, it indicates that no self-loop or loop has been generated. Then, the node is written into the link path array to update the link path array. The leaf nodes of the node are traversed, and the above process is repeated until all nodes are traversed and the final link path array is obtained.

[0105] If the node in the updated link path array indicates the presence of a self-loop or loop, then disconnecting the link between the traversed node and its parent node according to the node array includes: removing the last node from the link path array and removing the traversed node from the node array corresponding to the removed node, thereby disconnecting the link between the traversed node and its parent node, and thus achieving the purpose of eliminating self-loops or loops in the first-level graph.

[0106] like Figure 5The diagram shown is a schematic of a first-level graph with a self-loop. Node A is the root node, and nodes B and C are the leaf nodes of the root node A. The leaf node of node B is node B itself, meaning that a self-loop is generated at node B. Figure 5 In the example, node A stores the node array [A:B,C], node B stores the node array [B:B], and node C stores the node array [C:].

[0107] The electronic device starts from node A and performs a depth-first traversal along the leaf nodes. First, it traverses node A. Since node A is the root node, it is naturally not in the initialized link path array (an empty array), so the link path array is updated to [A] based on node A. Next, the electronic device traverses the leaf node B of node A, checking if node B is in the updated link path array [A]. Since node B is not in the updated link path array [A], the link path array is updated to [A, B] based on node B. The electronic device continues to traverse the leaf node B of node B. Clearly, node B is in the updated link path array [A, B]. The electronic device then removes the last node B from the link path array [A, B] and removes the node B it is traversing from the node array [B:B] corresponding to the removed node B. The node array stored in node B is then [B:]. In this way, the electronic device disconnects the link between the traversed leaf node B and its parent node B. The electronic device then traverses the leaf node C of node A and determines whether node C is in the updated link path array [A, B]. Since node C is not in the updated link path array [A, B], the link path array is updated to [A, B, C] based on node C.

[0108] like Figure 6 The diagram shown is a schematic of the first-level graph with a loop. Node A is the root node, node B is a leaf node of the root node A, node D is a leaf node of node B, node E is a leaf node of node D, and node B is a leaf node of node E. It can be seen that a loop is generated between nodes B, D, and E. Figure 6 In the diagram, node A stores the node array [A:B], node B stores the node array [B:D], node D stores the node array [D:E], and node E stores the node array [E:B].

[0109] The electronic device starts from node A and performs a depth-first traversal along the leaf nodes. First, it traverses node A. Since node A is the root node, it is not in the initialized link path array (an empty array), so the link path array is updated to [A]. Next, the electronic device traverses the leaf node B of node A and checks if node B is in the updated link path array [A]. Since node B is not in the updated link path array [A], the link path array is updated to [A, B] based on node B. It then continues traversing the leaf node D of node B. It checks if node D is in the updated link path array [A, B]. Since node D is not in the updated link path array [A, B], the link path array is updated to [A, B, D]. Finally, it traverses the leaf node E of node D, thus updating the link path array to [A, B, D, E]. When the electronic device continues to traverse the leaf node B of node E, it determines that node B is in the updated link path array [A, B, D, E]. The electronic device removes the last node E from the link path array [A, B, D, E] and removes the traversed node B from the node array [E: B] corresponding to the removed node E. In this way, the electronic device disconnects the link between the traversed node B and its parent node E, thereby achieving the purpose of eliminating the loop BDE.

[0110] S14, disconnect the network in the second-level graph to obtain the initial level tree.

[0111] Although the resulting second-level graph does not include loops, it could be either a tree or a network. In a tree, there is only one link from the root node to any leaf node. In a network, there are multiple links from the root node to any leaf node; the network structure indicates that at least one leaf node in the second-level graph has multiple parent nodes.

[0112] For the second-level graph of the mesh structure, the electronic device retains the link with the longest link length among the multiple links and cuts off the other links, thereby disconnecting the mesh structure of the second-level graph and obtaining the initial hierarchical tree.

[0113] In an optional implementation, the step of disconnecting the network in the second hierarchical graph to obtain the initial hierarchical tree includes:

[0114] Traverse from the root node of the second-level graph;

[0115] For each node visited, obtain the link from the root node to that node;

[0116] When there are multiple links, calculate the link length of each link;

[0117] The link with the longest length among the multiple links is selected as the target link.

[0118] Each of the multiple links, except for the target link, is compared with the target link from the end to the beginning to obtain the different nodes in each link from the target link;

[0119] Based on the node array, the links between different nodes in each link and the leaf nodes of the different nodes are disconnected to obtain the initial hierarchical tree.

[0120] The electronic device traverses the second-level graph using a breadth-first recursive approach, starting from the root node and proceeding along the leaf nodes. At each node visited, the electronic device obtains all links from the root node to that node. If there is only one link between the root node and the visited node, it indicates that there is no mesh structure between them. If there are multiple links between the root node and the visited node, it indicates that a mesh structure exists between them.

[0121] The electronic device can sort multiple links in ascending or descending order of link length, and obtain the longest link length based on the sorting result. This divides the links into two groups: the first group contains the links with the longest lengths, designated as the target links; the second group contains all remaining links except the target links. The electronic device compares each of the remaining links with the target link, starting from the end and moving backward. If the last two nodes are the same, the comparison continues with the second-to-last two nodes. If the second-to-last two nodes are the same, the comparison continues with the third-to-last two nodes, and so on, until two nodes are different. If two nodes are not the same, the link between the different nodes and their leaf nodes is disconnected according to the node array. This includes removing the node immediately following the node from the node array, thus disconnecting the link between the different nodes and their leaf nodes, thereby disabling the mesh structure in the second-level diagram.

[0122] Once the electronic device has compared each of the remaining links with the target link and removed any of them, the breadth-first traversal ends, and a hierarchical tree is generated.

[0123] like Figure 7 The diagram shown is a hierarchical diagram with a network structure. Figure 7In the diagram, node A stores the node array [A:B,C], node B stores the node array [B:D], node C stores the node array [C:H], node D stores the node array [D:E,F], node E stores the node array [E:], node F stores the node array [F:H], and node H stores the node array [H:E].

[0124] from Figure 7 It can be observed that for node E, there are multiple links. For example, link 1 is ABDE, link 2 is ABDFHE, and link 3 is ACHE.

[0125] The first step is to determine link 2 as the target link since link 2 has the longest link length.

[0126] The second step involves comparing link 1 and link 2 from the end. Specifically, the last node E of link 1 is compared with the last node E of link 2. Since these two nodes are the same, the second-to-last node D of link 1 is compared with the second-to-last node H of link 2. These two nodes are different. Therefore, from the node array [D:E,F] of node D, the node E following node D in link 1 is removed, thus breaking the link between node D and its leaf node E.

[0127] The third step involves comparing link 3 and link 2 from the end. Specifically, the last node E of link 3 is compared with the last node E of link 2. Since these two nodes are the same, the second-to-last node H of link 3 is compared with the second-to-last node H of link 2. These two nodes are also the same. Then, the third-to-last node C of link 3 is compared with the third-to-last node F of link 2. These two nodes are different. Therefore, from the node array [C:H] of node C, the node H following node C in link 3 is removed, thus achieving the goal of disconnecting the link between node C and its leaf node H.

[0128] S15, determine the position of the node and the branch width of the node in the hierarchical tree.

[0129] After the electronic device obtains the hierarchical tree based on the second-level diagram, in order to further visualize the hierarchical tree, it is necessary to set the nodes of the same level on the same horizontal line without overlapping. By calculating the position of the nodes in the hierarchical tree and the branch width between the nodes, the hierarchical tree can be rearranged.

[0130] In an optional implementation, determining the position of a node and the branch width of the node in the hierarchical tree includes:

[0131] Starting from the root node, traverse to the target leaf node, which is the target leaf node;

[0132] Determine the first position of the target leaf node;

[0133] Based on the first position, the sibling nodes of the target leaf node are determined sequentially until the second position of the rightmost sibling node is reached;

[0134] The third position of the parent node of the target leaf node is determined based on the first position and the second position;

[0135] The branch width of the parent node is determined based on the first position, the second position, and the third position.

[0136] Electronic devices can use a depth-first traversal to traverse from the root node of the hierarchical tree. The advantage of depth-first traversal is that it can quickly traverse to the target leaf node.

[0137] Electronic devices can determine the first position of a target leaf node based on the size of the display screen. For example, if the size of the display screen is W*H, with the top left corner of the display screen as the origin, the horizontal direction to the right of the display screen as the X-axis, and the vertical direction downwards of the display screen as the Y-axis, then the first position of the target leaf node in the hierarchical tree can be determined as (the node width of the target leaf node, H).

[0138] If the target leaf node has sibling nodes, the second position of the first sibling node closest to the target leaf node is determined based on the position of the target leaf node, the width of the first sibling node, and the preset horizontal spacing between the two nodes. The second position of the second sibling node closest to the target leaf node is determined based on the position of the first sibling node, the width of the second sibling node, and the preset horizontal spacing between the two nodes. This process continues until the second position of the rightmost sibling node is determined.

[0139] The electronic device determines the third position of the parent node of the target leaf node based on the first position and the second position. Specifically, the electronic device determines the third position of the parent node of the target leaf node based on the first position of the target leaf node and the second position of its rightmost sibling node. The third position of the parent node of the target leaf node can be determined based on the center point of the leftmost leaf node and the rightmost sibling node, as well as the vertical distance between preset nodes and the vertical distance between preset nodes.

[0140] The electronic device determines the branch width of the parent node based on the first position, the second position, and the third position. Specifically, the electronic device calculates the difference between the first position of the target leaf node and the first position of its rightmost sibling node, and then compares the difference with the node width of the target leaf node's parent node. If the difference is greater than the node width of the target leaf node's parent node, the branch width of the target leaf node's parent node is determined as the difference. If the difference is less than the node width of the target leaf node's parent node, the branch width of the target leaf node's parent node is determined as the node width of the target leaf node's parent node.

[0141] After determining the position of the parent node of the target leaf node, the electronic device can determine the position of the parent node's sibling nodes. Then, based on the positions of the parent node and its sibling nodes, it can determine the position of the parent node's parent node and the branch width. This process continues until the position and branch width of the root node are determined.

[0142] like Figure 8 As shown, node A is the root node, node B is a leaf node of node A, and nodes C, D and E are all leaf nodes of node B, and nodes C, D and E are sibling nodes.

[0143] Assume the width of the display screen is W, the length is H, the horizontal spacing between two nodes is L1, the vertical spacing between two nodes is L2, and the node width of node i is denoted as i. X (i = A, B, C, D, E, for example, the node width of node A is represented as A.) X The electronic device uses a depth-first recursive approach to traverse from the root node A along the direction of the leaf nodes, finds the leftmost leaf node of the last level as node C, and determines the position of leaf node C (C). X , H). Node D is the closest sibling node to node C, and the electronic device is determined based on the position of node C (C). X H) determines the position of node D (C). X +D. X +L1, H), then determine the position of sibling node E (C) based on the position of node D. X +D. X +E. X +2L1, H).

[0144] The electronic device determines the position of the parent node B of leaf node C based on the leftmost leaf node C and the rightmost leaf node E (1 / 2(2C). X+ +D. X +E. X +2L1), H-L2).

[0145] The electronic device determines the position of node A, the parent node of node B (1 / 2(2C).X+ +D. X +E. X +2L1), H-2L2).

[0146] S16, Connect two nodes with a parent-child relationship in the initial hierarchical tree according to the position and branch width of the node to obtain the target hierarchical tree.

[0147] Electronic devices connect two nodes with a parent-child relationship based on the node's position and branch width. When all nodes with a parent-child relationship have been connected, a hierarchical tree is generated, thus completing the hierarchical layout of the directed graph.

[0148] In an optional implementation, the step of connecting two nodes with a parent-child relationship in the initial hierarchical tree according to the position and branch width of the node to obtain the target hierarchical tree includes:

[0149] Generate a preset number of virtual nodes between two nodes that have a parent-child relationship;

[0150] The position of each virtual node is determined according to the preset coordinate calculation rules;

[0151] Connect any two adjacent virtual nodes to obtain the target hierarchical tree.

[0152] The preset number can be 7, meaning that the electronic device generates 7 virtual nodes between two nodes with a parent-child relationship, thereby abstracting the connection between the two nodes with a parent-child relationship into 6 line segments.

[0153] like Figure 9 As shown, the two nodes with a parent-child relationship are P and Q, and node Q is a leaf node of node P. The seven virtual nodes generated are P1, P2, P3, T, Q1, Q2, and Q3 in sequence. Then the line segments are P1P2, P2P3, P3T, TQ3, Q3Q2, and Q2Q1.

[0154] Let P represent the x-coordinate of node P, Py represent the y-coordinate, P.width represent the width of node P, and P.height represent the height of node P. Let Q represent the x-coordinate of node Q, Qy represent the y-coordinate, Q.width represent the width of node Q, and Q.height represent the height of node Q. The coordinate calculation rules for these 7 virtual nodes are as follows:

[0155] Q1(Q.x+Q.width / 2, Qy);

[0156] Q2(Q1.x, Qy-Q.height / 2);

[0157] Q3(Q2.x+dir*(Q.width / 2+space), Q2.y); dir is 1 when node Q is to the left of node P, and -1 when node Q is to the right of node P; space is the distance between nodes.

[0158] P1(P.x+P.width / 2,P.y+p.height);

[0159] P2(P1.x, P1.y + P.height / 2);

[0160] P3(P2.x, P2.yP.height / 2);

[0161] T(P3.x,Q3.y).

[0162] The above optional implementation method generates virtual nodes and connects two adjacent virtual nodes to connect two nodes with a parent-child relationship. This effectively avoids the phenomenon of node connections crossing and reduces mutual interference between connections.

[0163] In one alternative implementation, virtual node collapse may occur during virtual node generation. For example, if virtual node Q3 and virtual node P3 are collinear (but not parallel), the electronic device will align virtual node Q3 with virtual node Q2, and virtual node P3 with virtual node P2. Similarly, if virtual node T and virtual node Q2 are collinear (but not parallel), the electronic device will align virtual node T with virtual node Q3.

[0164] After completing the hierarchical layout of the directed graph to obtain the target hierarchical tree, the electronic device can also display the shortest link in the target hierarchical tree using a first display method and the longest link in the target hierarchical tree using a second display method. The first and second display methods are different to distinguish the shortest and longest links for user convenience. The first display method can use red markers, and the second display method can use blue markers. When the electronic device detects that a node in the target hierarchical tree has received a touch command, it can obtain all links containing the touched node and highlight them. When the electronic device detects a zoom command received on the target hierarchical tree, it zooms in and out of the target hierarchical tree.

[0165] In summary, the hierarchical layout method for directed graphs provided by this invention obtains the directed weight information of the directed graph, constructs a first-level graph based on this information, and eliminates loops (including self-loops) and mesh structures in the first-level graph by removing loops to obtain a second-level graph. Then, the mesh in the second-level graph is broken to obtain an initial hierarchical tree. The initial hierarchical tree contains neither loops nor mesh structures. Therefore, by determining the position and branch width of nodes in the hierarchical tree, a line can be drawn between two nodes with a parent-child relationship in the initial hierarchical tree based on the node's position and branch width to obtain the target hierarchical tree, thus completing the hierarchical layout of the directed graph. This invention does not employ a crossover exclusion algorithm; the branch width is obtained directly when generating the hierarchical tree, and lines pass through the gaps between branches, preventing node intersections. Therefore, it is easy to implement and improves layout efficiency.

[0166] Example 2

[0167] Figure 10 This is a structural diagram of the directed graph hierarchical layout device provided in Embodiment 2 of the present invention.

[0168] In some embodiments, the directed graph hierarchical layout device 100 may include a plurality of functional modules composed of computer program segments. The computer programs of each program segment in the directed graph hierarchical layout device 100 may be stored in the memory of an electronic device and executed by at least one processor to perform (see details). Figure 1 (Description) Functionality of hierarchical layout of directed graphs.

[0169] In this embodiment, the directed graph hierarchical layout device 100 can be divided into multiple functional modules according to its functions. These functional modules may include: an acquisition module 1001, a construction module 1002, a loop elimination module 1003, a network disconnection module 1004, a calculation module 1005, and a connection module 1006. The module referred to in this invention is a series of computer program segments that can be executed by at least one processor and perform a fixed function, stored in memory. In this embodiment, the functions of each module will be detailed in subsequent embodiments.

[0170] The acquisition module 1001 is used to acquire the directed weight information of the directed graph in response to an instruction to lay out the directed graph.

[0171] The directed graphs in the embodiments of the present invention may include directed acyclic graphs and directed cyclic graphs.

[0172] If arrows indicate that the edges have a direction, then such a graph is called a directed graph. If a directed graph cannot be returned to a given node by traversing several edges, then the graph is a directed acyclic graph (DAG), which is a directed graph without cycles. Figure 2 As shown, this is a directed acyclic graph. Figure 2 In a graph, it is impossible to return to any given node by traversing any number of edges from that node. If a directed graph allows a return path from any given node to that node by traversing any number of edges, then the graph is a directed graph with a cycle. For example... Figure 3 As shown, this is a directed graph with cycles. Figure 3 A path starts from node B, travels to node D, passes through node E, and returns to node B, forming a loop. If... Figure 3 If the direction of the edge from node E to node B is changed to be from node B to node E, it becomes a directed acyclic graph.

[0173] Users can upload directed graphs locally, to a server, or to a blockchain. Correspondingly, electronic devices can retrieve directed graphs locally, from a server, or from the blockchain. Once a directed graph is retrieved, the electronic device triggers an instruction to perform a hierarchical layout of the retrieved graph and, in response to this instruction, obtains the directed weight information of the graph.

[0174] The directed weight information may include, but is not limited to, node identifiers, edge directions between nodes, and node widths. A node identifier is a string that uniquely identifies a node, and a node width refers to the width of the string representing the node. For example, if the string for node A is "company," then the node width for node A can be 7; if the string for node A is "department," then the node width for node A can be 10.

[0175] The construction module 1002 is used to construct a first-level graph based on the directed weight information of the directed graph.

[0176] After obtaining the directed weight information of the directed graph, the electronic device establishes a first-level graph with a hierarchical structure based on the directed weight information.

[0177] In an optional implementation, constructing the first-level graph based on the directed weight information of the directed graph includes:

[0178] The parent node and leaf node in the directed graph are determined based on the directed weight information of the directed graph;

[0179] A node array is generated based on the node identifier of the parent node and the node identifiers of the leaf nodes of the parent node, and the node array is stored in the parent node;

[0180] Construct a first-level graph based on the parent node, the leaf node, and the hierarchy of the leaf nodes.

[0181] In a directed graph, arrows have direction, pointing from one node to another. The number of arrows pointing to a node is its in-degree, and the number of arrows pointing out of a node is its out-degree. Electronic devices determine the in-degree and out-degree of each node based on the edge directions in the directed weight information, designating nodes with an in-degree of zero as parent nodes. Nodes pointed to by parent nodes are designated as leaf nodes, and nodes pointed to by leaf nodes are designated as leaf nodes.

[0182] like Figure 3 As shown, Figure 3 The nodes in the array are labeled A, B, C, D, and E. Since node A has an in-degree of zero, it is designated as the parent node. Nodes B and C, which the parent node points to, are designated as leaf nodes of node A. Node D, which node B points to, is designated as a leaf node of node B. Node E, which node D points to, is designated as a leaf node of node D. Node B, which node E points to, is designated as a leaf node of node E. Therefore, the node array stored in node A is [A:B,C], in node B is [B:D], in node C is [C:], in node D is [D:E], and in node E is [E:B].

[0183] It should be understood that the parent node in this implementation can be one or more.

[0184] In an optional implementation, constructing the first hierarchical graph based on the parent node, the leaf node, and the hierarchy of the leaf nodes includes:

[0185] Calculate the number of parent nodes;

[0186] Determine whether the quantity is 1;

[0187] When the quantity is 1, the parent node is determined as the root node in the first level graph;

[0188] When the number is greater than 1, a pseudo node is generated and the pseudo node is used as the root node of the multiple parent nodes in the first level graph.

[0189] The purpose of this invention is to hierarchically arrange a directed graph to obtain a directed tree. Since a directed tree can only have one root node, when the number of parent nodes in the first-level graph is one, this parent node can be used as the root node of the first-level graph, which is also the root node of the subsequently generated directed tree. However, when there are multiple parent nodes, a virtual node needs to be generated as the root node of these multiple parent nodes; that is, this virtual node is forged as the root node of the subsequently generated directed tree.

[0190] like Figure 4 As shown in the diagram, there are two parent nodes A and F. A virtual node is generated to serve as the root node of the directed tree.

[0191] The loop elimination module 1003 is used to eliminate loops in the first-level diagram to obtain the second-level diagram.

[0192] The electronic device traverses the first-level graph and cuts the loops in the first-level graph, thereby eliminating the loops in the first-level graph and obtaining the second-level graph.

[0193] The loop also includes self-loops.

[0194] In an optional implementation, the step of eliminating loops in the first-level graph to obtain the second-level graph includes:

[0195] Initialize the link path array;

[0196] Traverse the graph from the root node of the first level along the direction of the leaf nodes;

[0197] For each node visited, determine whether the visited node is in the link path array;

[0198] When it is determined that the traversed node is not in the link path array, the link path array is updated according to the traversed node, and the leaf nodes of the node are traversed again to determine whether the traversed leaf is in the updated link path array.

[0199] When it is determined that the traversed node is in the link path array, the link between the traversed node and its parent node is disconnected according to the node array, thus obtaining the second-level graph.

[0200] The link path array initialized by the electronic device can be an empty array. Starting from the root node, the electronic device traverses the first-level graph using a depth-first recursive approach along the leaf nodes. After reaching the root node, the electronic device updates the initialized link path array, and then continues the depth-first recursive approach from the root node along the leaf nodes. At each node reached, it checks whether the node is in the updated link path array.

[0201] If the node is not in the updated link path array, it indicates that no self-loop or loop has been generated. Then, the node is written into the link path array to update the link path array. The leaf nodes of the node are traversed, and the above process is repeated until all nodes are traversed and the final link path array is obtained.

[0202] If the node in the updated link path array indicates the presence of a self-loop or loop, then disconnecting the link between the traversed node and its parent node according to the node array includes: removing the last node from the link path array and removing the traversed node from the node array corresponding to the removed node, thereby disconnecting the link between the traversed node and its parent node, and thus achieving the purpose of eliminating self-loops or loops in the first-level graph.

[0203] like Figure 5 The diagram shown is a schematic of a first-level graph with a self-loop. Node A is the root node, and nodes B and C are the leaf nodes of the root node A. The leaf node of node B is node B itself, meaning that a self-loop is generated at node B. Figure 5 In the example, node A stores the node array [A:B,C], node B stores the node array [B:B], and node C stores the node array [C:].

[0204] The electronic device starts from node A and performs a depth-first traversal along the leaf nodes. First, it traverses node A. Since node A is the root node, it is naturally not in the initialized link path array (an empty array), so the link path array is updated to [A] based on node A. Next, the electronic device traverses the leaf node B of node A, checking if node B is in the updated link path array [A]. Since node B is not in the updated link path array [A], the link path array is updated to [A, B] based on node B. The electronic device continues to traverse the leaf node B of node B. Clearly, node B is in the updated link path array [A, B]. The electronic device then removes the last node B from the link path array [A, B] and removes the node B it is traversing from the node array [B:B] corresponding to the removed node B. The node array stored in node B is then [B:]. In this way, the electronic device disconnects the link between the traversed leaf node B and its parent node B. The electronic device then traverses the leaf node C of node A and determines whether node C is in the updated link path array [A, B]. Since node C is not in the updated link path array [A, B], the link path array is updated to [A, B, C] based on node C.

[0205] like Figure 6 The diagram shown is a schematic of the first-level graph with a loop. Node A is the root node, node B is a leaf node of the root node A, node D is a leaf node of node B, node E is a leaf node of node D, and node B is a leaf node of node E. It can be seen that a loop is generated between nodes B, D, and E. Figure 6 In the diagram, node A stores the node array [A:B], node B stores the node array [B:D], node D stores the node array [D:E], and node E stores the node array [E:B].

[0206] The electronic device starts from node A and performs a depth-first traversal along the leaf nodes. First, it traverses node A. Since node A is the root node, it is not in the initialized link path array (an empty array), so the link path array is updated to [A]. Next, the electronic device traverses the leaf node B of node A and checks if node B is in the updated link path array [A]. Since node B is not in the updated link path array [A], the link path array is updated to [A, B] based on node B. It then continues traversing the leaf node D of node B. It checks if node D is in the updated link path array [A, B]. Since node D is not in the updated link path array [A, B], the link path array is updated to [A, B, D]. Finally, it traverses the leaf node E of node D, thus updating the link path array to [A, B, D, E]. When the electronic device continues to traverse the leaf node B of node E, it determines that node B is in the updated link path array [A, B, D, E]. The electronic device removes the last node E from the link path array [A, B, D, E] and removes the traversed node B from the node array [E: B] corresponding to the removed node E. In this way, the electronic device disconnects the link between the traversed node B and its parent node E, thereby achieving the purpose of eliminating the loop BDE.

[0207] The network disconnection module 1004 is used to disconnect the network of the second-level graph to obtain the initial-level tree.

[0208] Although the resulting second-level graph does not include loops, it could be either a tree or a network. In a tree, there is only one link from the root node to any leaf node. In a network, there are multiple links from the root node to any leaf node; the network structure indicates that at least one leaf node in the second-level graph has multiple parent nodes.

[0209] For the second-level graph of the mesh structure, the electronic device retains the link with the longest link length among the multiple links and cuts off the other links, thereby disconnecting the mesh structure of the second-level graph and obtaining the initial hierarchical tree.

[0210] In an optional implementation, the step of disconnecting the network in the second hierarchical graph to obtain the initial hierarchical tree includes:

[0211] Traverse from the root node of the second-level graph;

[0212] For each node visited, obtain the link from the root node to that node;

[0213] When there are multiple links, calculate the link length of each link;

[0214] The link with the longest length among the multiple links is selected as the target link.

[0215] Each of the multiple links, except for the target link, is compared with the target link from the end to the beginning to obtain the different nodes in each link from the target link;

[0216] Based on the node array, the links between different nodes in each link and the leaf nodes of the different nodes are disconnected to obtain the initial hierarchical tree.

[0217] The electronic device traverses the second-level graph using a breadth-first recursive approach, starting from the root node and proceeding along the leaf nodes. At each node visited, the electronic device obtains all links from the root node to that node. If there is only one link between the root node and the visited node, it indicates that there is no mesh structure between them. If there are multiple links between the root node and the visited node, it indicates that a mesh structure exists between them.

[0218] The electronic device can sort multiple links in ascending or descending order of link length, and obtain the longest link length based on the sorting result. This divides the links into two groups: the first group contains the links with the longest lengths, designated as the target links; the second group contains all remaining links except the target links. The electronic device compares each of the remaining links with the target link, starting from the end and moving backward. If the last two nodes are the same, the comparison continues with the second-to-last two nodes. If the second-to-last two nodes are the same, the comparison continues with the third-to-last two nodes, and so on, until two nodes are different. If two nodes are not the same, the link between the different nodes and their leaf nodes is disconnected according to the node array. This includes removing the node immediately following the node from the node array, thus disconnecting the link between the different nodes and their leaf nodes, thereby disabling the mesh structure in the second-level diagram.

[0219] Once the electronic device has compared each of the remaining links with the target link and removed any of them, the breadth-first traversal ends, and a hierarchical tree is generated.

[0220] like Figure 7 The diagram shown is a hierarchical diagram with a network structure. Figure 7In the diagram, node A stores the node array [A:B,C], node B stores the node array [B:D], node C stores the node array [C:H], node D stores the node array [D:E,F], node E stores the node array [E:], node F stores the node array [F:H], and node H stores the node array [H:E].

[0221] from Figure 7 It can be observed that for node E, there are multiple links. For example, link 1 is ABDE, link 2 is ABDFHE, and link 3 is ACHE.

[0222] The first step is to determine link 2 as the target link since link 2 has the longest link length.

[0223] The second step involves comparing link 1 and link 2 from the end. Specifically, the last node E of link 1 is compared with the last node E of link 2. Since these two nodes are the same, the second-to-last node D of link 1 is compared with the second-to-last node H of link 2. These two nodes are different. Therefore, from the node array [D:E,F] of node D, the node E following node D in link 1 is removed, thus breaking the link between node D and its leaf node E.

[0224] The third step involves comparing link 3 and link 2 from the end. Specifically, the last node E of link 3 is compared with the last node E of link 2. Since these two nodes are the same, the second-to-last node H of link 3 is compared with the second-to-last node H of link 2. These two nodes are also the same. Then, the third-to-last node C of link 3 is compared with the third-to-last node F of link 2. These two nodes are different. Therefore, from the node array [C:H] of node C, the node H following node C in link 3 is removed, thus achieving the goal of disconnecting the link between node C and its leaf node H.

[0225] The calculation module 1005 is used to determine the position of the node and the branch width of the node in the hierarchical tree.

[0226] After the electronic device obtains the hierarchical tree based on the second-level diagram, in order to further visualize the hierarchical tree, it is necessary to set the nodes of the same level on the same horizontal line without overlapping. By calculating the position of the nodes in the hierarchical tree and the branch width between the nodes, the hierarchical tree can be rearranged.

[0227] In an optional implementation, determining the position of a node and the branch width of the node in the hierarchical tree includes:

[0228] Starting from the root node, traverse to the target leaf node, which is the target leaf node;

[0229] Determine the first position of the target leaf node;

[0230] Based on the first position, the sibling nodes of the target leaf node are determined sequentially until the second position of the rightmost sibling node is reached;

[0231] The third position of the parent node of the target leaf node is determined based on the first position and the second position;

[0232] The branch width of the parent node is determined based on the first position, the second position, and the third position.

[0233] Electronic devices can use a depth-first traversal to traverse from the root node of the hierarchical tree. The advantage of depth-first traversal is that it can quickly traverse to the target leaf node.

[0234] Electronic devices can determine the first position of a target leaf node based on the size of the display screen. For example, if the size of the display screen is W*H, with the top left corner of the display screen as the origin, the horizontal direction to the right of the display screen as the X-axis, and the vertical direction downwards of the display screen as the Y-axis, then the first position of the target leaf node in the hierarchical tree can be determined as (the node width of the target leaf node, H).

[0235] If the target leaf node has sibling nodes, the second position of the first sibling node closest to the target leaf node is determined based on the position of the target leaf node, the width of the first sibling node, and the preset horizontal spacing between the two nodes. The second position of the second sibling node closest to the target leaf node is determined based on the position of the first sibling node, the width of the second sibling node, and the preset horizontal spacing between the two nodes. This process continues until the second position of the rightmost sibling node is determined.

[0236] The electronic device determines the third position of the parent node of the target leaf node based on the first position and the second position. Specifically, the electronic device determines the third position of the parent node of the target leaf node based on the first position of the target leaf node and the second position of its rightmost sibling node. The third position of the parent node of the target leaf node can be determined based on the center point of the leftmost leaf node and the rightmost sibling node, as well as the vertical distance between preset nodes and the vertical distance between preset nodes.

[0237] The electronic device determines the branch width of the parent node based on the first position, the second position, and the third position. Specifically, the electronic device calculates the difference between the first position of the target leaf node and the first position of its rightmost sibling node, and then compares the difference with the node width of the target leaf node's parent node. If the difference is greater than the node width of the target leaf node's parent node, the branch width of the target leaf node's parent node is determined as the difference. If the difference is less than the node width of the target leaf node's parent node, the branch width of the target leaf node's parent node is determined as the node width of the target leaf node's parent node.

[0238] After determining the position of the parent node of the target leaf node, the electronic device can determine the position of the parent node's sibling nodes. Then, based on the positions of the parent node and its sibling nodes, it can determine the position of the parent node's parent node and the branch width. This process continues until the position and branch width of the root node are determined.

[0239] like Figure 8 As shown, node A is the root node, node B is a leaf node of node A, and nodes C, D and E are all leaf nodes of node B, and nodes C, D and E are sibling nodes.

[0240] Assume the width of the display screen is W, the length is H, the horizontal spacing between two nodes is L1, the vertical spacing between two nodes is L2, and the node width of node i is denoted as i. X (i = A, B, C, D, E, for example, the node width of node A is represented as A.) X The electronic device uses a depth-first recursive approach to traverse from the root node A along the direction of the leaf nodes, finds the leftmost leaf node of the last level as node C, and determines the position of leaf node C (C). X , H). Node D is the closest sibling node to node C, and the electronic device is determined based on the position of node C (C). X H) determines the position of node D (C). X +D. X +L1, H), then determine the position of sibling node E (C) based on the position of node D. X +D. X +E. X +2L1, H).

[0241] The electronic device determines the position of the parent node B of leaf node C based on the leftmost leaf node C and the rightmost leaf node E (1 / 2(2C). X+ +D. X +E. X +2L1), H-L2).

[0242] The electronic device determines the position of node A, the parent node of node B (1 / 2(2C).X+ +D. X +E. X +2L1), H-2L2).

[0243] The connection module 1006 is used to connect two nodes with a parent-child relationship in the initial hierarchical tree according to the position and branch width of the node, so as to obtain the target hierarchical tree.

[0244] Electronic devices connect two nodes with a parent-child relationship based on the node's position and branch width. When all nodes with a parent-child relationship have been connected, a hierarchical tree is generated, thus completing the hierarchical layout of the directed graph.

[0245] In an optional implementation, the step of connecting two nodes with a parent-child relationship in the initial hierarchical tree according to the position and branch width of the node to obtain the target hierarchical tree includes:

[0246] Generate a preset number of virtual nodes between two nodes that have a parent-child relationship;

[0247] The position of each virtual node is determined according to the preset coordinate calculation rules;

[0248] Connect any two adjacent virtual nodes to obtain the target hierarchical tree.

[0249] The preset number can be 7, meaning that the electronic device generates 7 virtual nodes between two nodes with a parent-child relationship, thereby abstracting the connection between the two nodes with a parent-child relationship into 6 line segments.

[0250] like Figure 9 As shown, the two nodes with a parent-child relationship are P and Q, and node Q is a leaf node of node P. The seven virtual nodes generated are P1, P2, P3, T, Q1, Q2, and Q3 in sequence. Then the line segments are P1P2, P2P3, P3T, TQ3, Q3Q2, and Q2Q1.

[0251] Let P represent the x-coordinate of node P, Py represent the y-coordinate, P.width represent the width of node P, and P.height represent the height of node P. Let Q represent the x-coordinate of node Q, Qy represent the y-coordinate, Q.width represent the width of node Q, and Q.height represent the height of node Q. The coordinate calculation rules for these 7 virtual nodes are as follows:

[0252] Q1(Q.x+Q.width / 2, Qy);

[0253] Q2(Q1.x, Qy-Q.height / 2);

[0254] Q3(Q2.x+dir*(Q.width / 2+space), Q2.y); dir is 1 when node Q is to the left of node P, and -1 when node Q is to the right of node P; space is the distance between nodes.

[0255] P1(P.x+P.width / 2,P.y+p.height);

[0256] P2(P1.x, P1.y + P.height / 2);

[0257] P3(P2.x, P2.yP.height / 2);

[0258] T(P3.x,Q3.y).

[0259] The above optional implementation method generates virtual nodes and connects two adjacent virtual nodes to connect two nodes with a parent-child relationship. This effectively avoids the phenomenon of node connections crossing and reduces mutual interference between connections.

[0260] In one alternative implementation, virtual node collapse may occur during virtual node generation. For example, if virtual node Q3 and virtual node P3 are collinear (but not parallel), the electronic device will align virtual node Q3 with virtual node Q2, and virtual node P3 with virtual node P2. Similarly, if virtual node T and virtual node Q2 are collinear (but not parallel), the electronic device will align virtual node T with virtual node Q3.

[0261] After completing the hierarchical layout of the directed graph to obtain the target hierarchical tree, the electronic device can also display the shortest link in the target hierarchical tree using a first display method and the longest link in the target hierarchical tree using a second display method. The first and second display methods are different to distinguish the shortest and longest links for user convenience. The first display method can use red markers, and the second display method can use blue markers. When the electronic device detects that a node in the target hierarchical tree has received a touch command, it can obtain all links containing the touched node and highlight them. When the electronic device detects a zoom command received on the target hierarchical tree, it zooms in and out of the target hierarchical tree.

[0262] In summary, the hierarchical layout apparatus for directed graphs provided in this invention, after obtaining the directed weight information of the directed graph, constructs a first-level graph based on the directed weight information. Since the first-level graph may contain loops (including self-loops) and mesh structures, loops in the first-level graph are eliminated to obtain a second-level graph. Then, the mesh in the second-level graph is broken to obtain an initial hierarchical tree. The obtained initial hierarchical tree contains neither loops nor mesh structures. Therefore, by determining the position and branch width of nodes in the hierarchical tree, two nodes with a parent-child relationship in the initial hierarchical tree can be connected according to the position and branch width to obtain the target hierarchical tree, thus completing the hierarchical layout of the directed graph. This invention does not use a crossover exclusion algorithm; the branch width is obtained directly when generating the hierarchical tree. Lines pass through the gaps between branches, avoiding node intersections, thus making it easy to implement and improving layout efficiency.

[0263] Example 3

[0264] This embodiment provides a computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the steps in the above-described embodiment of the hierarchical layout method for directed graphs. Figure 1 S11-S16 as shown:

[0265] S11, in response to the instruction to lay out the directed graph, obtain the directed weight information of the directed graph;

[0266] S12, Construct a first-level graph based on the directed weight information of the directed graph;

[0267] S13, Eliminate loops in the first-level graph to obtain the second-level graph;

[0268] S14, Disconnect the mesh from the second-level graph to obtain the initial hierarchical tree;

[0269] S15, determine the position of the node and the branch width of the node in the hierarchical tree;

[0270] S16, Connect two nodes with a parent-child relationship in the initial hierarchical tree according to the position and branch width of the node to obtain the target hierarchical tree.

[0271] Alternatively, when the computer program is executed by the processor, it implements the functions of each module / unit in the above-described device embodiments, for example... Figure 10 Modules 1001-1006 in the middle:

[0272] The acquisition module 1001 is used to acquire the directed weight information of the directed graph in response to an instruction to lay out the directed graph.

[0273] The construction module 1002 is used to construct a first-level graph based on the directed weight information of the directed graph;

[0274] The loop elimination module 1003 is used to eliminate loops in the first-level diagram to obtain a second-level diagram.

[0275] The network disconnection module 1004 is used to disconnect the network of the second hierarchical graph to obtain the initial hierarchical tree;

[0276] The calculation module 1005 is used to determine the position of the node and the branch width of the node in the hierarchical tree;

[0277] The connection module 1006 is used to connect two nodes with a parent-child relationship in the initial hierarchical tree according to the position and branch width of the node, so as to obtain the target hierarchical tree.

[0278] Example 4

[0279] See Figure 11 The diagram shown is a structural schematic of an electronic device provided in Embodiment 3 of the present invention. In a preferred embodiment of the present invention, the electronic device 110 includes a memory 1101, at least one processor 1102, at least one communication bus 1103, and a transceiver 1104.

[0280] Those skilled in the art should understand that Figure 11 The structure of the electronic device shown does not constitute a limitation of the embodiments of the present invention. It can be a bus structure or a star structure. The electronic device 110 may also include more or fewer other hardware or software than shown, or different component arrangements.

[0281] In some embodiments, the electronic device 110 is a device capable of automatically performing numerical calculations and / or information processing according to pre-set or stored instructions. Its hardware includes, but is not limited to, microprocessors, application-specific integrated circuits (ASICs), programmable gate arrays (FPGAs), digital processors, and embedded devices. The electronic device 110 may also include client devices, including, but not limited to, any electronic product capable of human-computer interaction with a client via a keyboard, mouse, remote control, touchpad, or voice control device, such as personal computers, tablets, smartphones, and digital cameras.

[0282] The electronic device 110 described herein is merely an example. Other existing or future electronic products that are adaptable to this invention should also be included within the scope of protection of this invention and are incorporated herein by reference.

[0283] In some embodiments, the memory 1101 stores a computer program that, when executed by the at least one processor 1102, implements all or part of the steps in the hierarchical layout method of the directed graph as described. The memory 1101 includes read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium capable of carrying or storing data.

[0284] Furthermore, the computer-readable storage medium may primarily include a program storage area and a data storage area, wherein the program storage area may store the operating system, at least one application required for a function, etc.; and the data storage area may store data created based on the use of blockchain nodes, etc.

[0285] The blockchain referred to in this invention is a novel application model of computer technologies such as distributed data storage, peer-to-peer transmission, consensus mechanisms, and encryption algorithms. Essentially, a blockchain is a decentralized database, a chain of data blocks linked together using cryptographic methods. Each data block contains information about a batch of network transactions, used to verify the validity of the information (anti-counterfeiting) and generate the next block. A blockchain can include an underlying blockchain platform, a platform product service layer, and an application service layer.

[0286] In some embodiments, the at least one processor 1102 is the control unit of the electronic device 110, connecting various components of the electronic device 110 via various interfaces and lines. It executes programs or modules stored in the memory 1101 and calls data stored in the memory 1101 to perform various functions and process data of the electronic device 110. For example, when the at least one processor 1102 executes a computer program stored in the memory, it implements all or part of the steps of the directed graph hierarchical layout method described in this embodiment of the invention; or it implements all or part of the functions of the directed graph hierarchical layout device. The at least one processor 1102 may be composed of integrated circuits, such as a single-packaged integrated circuit or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips.

[0287] In some embodiments, the at least one communication bus 1103 is configured to enable communication between the memory 1101 and the at least one processor 1102, etc.

[0288] Although not shown, the electronic device 110 may also include a power supply (such as a battery) to power various components. Preferably, the power supply can be logically connected to the at least one processor 1102 via a power management device, thereby enabling functions such as charging, discharging, and power consumption management through the power management device. The power supply may also include one or more DC or AC power supplies, recharging devices, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device 110 may also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be described in detail here.

[0289] The integrated unit implemented as a software functional module described above can be stored in a computer-readable storage medium. This software functional module, stored in a storage medium, includes several instructions to cause a computer device (which may be a personal computer, electronic device, or network device, etc.) or processor to execute portions of the methods described in the various embodiments of the present invention.

[0290] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for example, the division of modules is merely a logical functional division, and other division methods may be used in actual implementation.

[0291] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0292] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0293] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be embraced within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims. Furthermore, it is clear that the word "comprising" does not exclude other elements, and the singular does not exclude the plural. Multiple elements or devices recited in the specification may also be implemented by a single element or device in software or hardware. The terms "first," "second," etc., are used to indicate names and do not indicate any particular order.

[0294] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A hierarchical layout method for directed graphs, characterized in that, The method includes: In response to an instruction to lay out a directed graph, the directed weight information of the directed graph is obtained; Construct a first-level graph based on the directed weight information of the directed graph; Eliminate the loops in the first-level graph to obtain the second-level graph; Disconnecting the network in the second-level graph to obtain an initial hierarchical tree includes: retaining the link with the longest link length among multiple links in the second-level graph of the mesh structure, and cutting off the other links among the multiple links to obtain the initial hierarchical tree, in which loops and mesh structures do not exist; Determining the position and branch width of a node in the initial hierarchical tree includes: traversing from the root node to a target leaf node, which is designated as the target leaf node; determining the first position of the target leaf node; determining the sibling nodes of the target leaf node sequentially based on the first position, up to the second position of the rightmost sibling node; determining the third position of the parent node of the target leaf node based on the first and second positions; and determining the branch width of the parent node based on the first, second, and third positions. Connecting two nodes with a parent-child relationship in the initial hierarchical tree according to the node's position and branch width to obtain the target hierarchical tree includes: generating a preset number of virtual nodes between two nodes with a parent-child relationship; determining the position of each virtual node according to a preset coordinate calculation rule; and connecting every two adjacent virtual nodes to obtain the target hierarchical tree.

2. The hierarchical layout method for directed graphs as described in claim 1, characterized in that, The construction of the first-level graph based on the directed weight information of the directed graph includes: The parent node and leaf node in the directed graph are determined based on the directed weight information of the directed graph; A node array is generated based on the node identifier of the parent node and the node identifiers of the leaf nodes of the parent node, and the node array is stored in the parent node; Construct a first-level graph based on the parent node, the leaf node, and the hierarchy of the leaf nodes.

3. The hierarchical layout method for directed graphs as described in claim 2, characterized in that, The construction of the first-level graph based on the parent node, the leaf node, and the hierarchy of the leaf nodes includes: Calculate the number of parent nodes; Determine whether the quantity is 1; When the quantity is 1, the parent node is determined as the root node in the first level graph; When the number is greater than 1, a pseudo node is generated and the pseudo node is used as the root node of the multiple parent nodes in the first level graph.

4. The hierarchical layout method for directed graphs as described in claim 2, characterized in that, The process of eliminating loops in the first-level graph to obtain the second-level graph includes: Initialize the link path array; Traverse the graph from the root node of the first level along the direction of the leaf nodes; For each node visited, determine whether the visited node is in the link path array; When it is determined that the traversed node is not in the link path array, the link path array is updated according to the traversed node, and the leaf nodes of the node are traversed again to determine whether the traversed leaf is in the updated link path array. When it is determined that the traversed node is in the link path array, the link between the traversed node and its parent node is disconnected according to the node array, thus obtaining the second level graph.

5. The hierarchical layout method for directed graphs as described in claim 4, characterized in that, The process of disconnecting the network in the second-level graph to obtain the initial hierarchical tree includes: Traverse from the root node of the second-level graph; For each node visited, obtain the link from the root node to that node; When there are multiple links, calculate the link length of each link; The link with the longest length among the multiple links is selected as the target link. Each of the multiple links, except for the target link, is compared with the target link from the end to the beginning to obtain the different nodes in each link from the target link; Based on the node array, the links between different nodes in each link and the leaf nodes of the different nodes are disconnected to obtain the initial hierarchical tree.

6. A hierarchical layout device for directed graphs, characterized in that, The apparatus is used to implement the hierarchical layout method of a directed graph as described in any one of claims 1 to 5, the apparatus comprising: The acquisition module is used to acquire the directed weight information of the directed graph in response to an instruction to lay out the directed graph; A construction module is used to construct a first-level graph based on the directed weight information of the directed graph; The loop elimination module is used to eliminate loops in the first-level graph to obtain the second-level graph. The network disconnection module is used to disconnect the network of the second-level graph to obtain the initial level tree; A calculation module is used to determine the position of nodes and the branch width of nodes in the hierarchical tree; The connection module is used to connect two nodes with a parent-child relationship in the initial hierarchical tree according to the position and branch width of the node, so as to obtain the target hierarchical tree.

7. An electronic device, characterized in that, The electronic device includes a processor and a memory, the processor being configured to implement the hierarchical layout method of the directed graph as described in any one of claims 1 to 5 when executing a computer program stored in the memory.

8. A computer-readable storage medium storing a computer program thereon, characterized in that, When the computer program is executed by a processor, it implements the hierarchical layout method for directed graphs as described in any one of claims 1 to 5.

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