A two-step search based incremental sigma delta adc parameter optimization system

Abstract

The application claims a two-step search-based incremental sigma delta ADC parameter optimization method, comprising a feedback path, a quantizer, a first stage, a second stage integrator, a first, a second and a third feedforward path, a to-be-determined coefficient b and a to-be-determined coefficient c. The feedback path is connected between a summing node before the to-be-determined coefficient b and an output end of the quantizer, and a feedback signal is obtained by processing an output signal output by the quantizer; the first feedforward path is connected between an output end of a modulator and an input end of the quantizer, the second feedforward path is connected between an output end of the first stage integrator and the input end of the quantizer, and the third feedforward path is connected between an output end of the second stage integrator and the input end of the quantizer; the feedforward paths perform weighted summation on an input signal and output signals of the first stage and the second stage integrators before quantization; the to-be-determined coefficient b and the to-be-determined coefficient c are connected before the first stage and the second stage integrators respectively and are determined through an algorithm; and the application is more accurate and fast.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit design technology, specifically relating to an incremental sigma delta ADC parameter optimization algorithm based on two-step search. Background Technology

[0002] Based on the ratio of sampling frequency to input signal bandwidth, ADCs can be roughly divided into two types: Nyquist ADCs and Sigma-delta ADCs. Among them, Sigma-delta ADCs can significantly increase the effective number of bits by using oversampling and noise shaping techniques. Incremental Sigma-delta ADCs have made certain improvements on the basis of traditional Sigma-delta ADCs. They have almost inherited all the advantages of Sigma-delta ADCs and adopted the working mode of Nyquist ADCs. At the same time, incremental Sigma-delta ADCs have their own unique working characteristics: (1) the converter can operate in discontinuous mode; (2) the analog integrator and digital filter are reset before each conversion; (3) the design difficulty of digital decimation filter is reduced.

[0003] Incremental Sigma-delta ADCs typically employ a CIFF (Cascade of Intergrators, FeedForward) structure. Compared to traditional Sigma-delta ADCs, the input signal of an incremental Sigma-delta ADC remains unchanged within a single conversion cycle. After each conversion, a Reset signal resets the integrator and subsequent filter before starting the next conversion cycle. The following nonlinear relationship exists between its effective number of bits (ENOB), the number of conversion cycles (M), and the undetermined coefficients (b, c):

[0004] ENOB=2log2(M)+log2(bc)-1 (3)

[0005] Since the values ​​of b and c are between 0 and 1, and M >> 1, we can obtain from equation (3) that the larger the product of b and c, the larger ENOB is, and the larger the value of M, the larger ENOB is. However, too large values ​​of b and c will cause the integrator to swing too much, which will increase the power consumption of the ADC and reduce its linearity. Too large a value of M will cause the number of cycles required for a single conversion to be too large, which will make the ADC too slow. This involves the compromise of parameter selection. In fact, ENOB is usually a fixed index in the design, and when ENOB is determined, the value of M is completely determined by the product of b and c.

[0006]

[0007] From equation (4), we can see that the larger the product of b and c, the fewer cycles M are required for a single conversion. Therefore, when modeling an incremental sigma delta ADC, we need to consider how to reasonably select the values ​​of b and c under the fixed ENOB condition so that the swing of the integrator is controlled within a small range while obtaining a small value of M to ensure that the conversion speed of the ADC is not too slow.

[0008] There are two existing methods for determining the values ​​of b and c: 1. Direct calculation using SD tools. This method is mainly used for traditional sigma delta ADCs, but the values ​​obtained are not entirely applicable to incremental sigma delta ADCs; 2. Manual iteration to obtain values ​​that meet the conditions through multiple modeling and simulations. The values ​​obtained by this method can meet the basic operating conditions of incremental sigma delta ADCs, but they are not accurate enough and are time-consuming.

[0009] To address the shortcomings of existing technologies, this invention proposes an incremental sigma delta ADC parameter optimization system based on a two-step search. This system is specifically designed for determining the b and c values ​​of incremental sigma delta ADCs and can quickly and accurately solve for the optimal b and c values ​​that meet the conditions. This allows the ADC to operate at its fastest speed while meeting design specifications such as accuracy and integrator swing. Summary of the Invention

[0010] The present invention aims to solve the problems of the prior art mentioned above. A method is proposed. The technical solution of the present invention is as follows:

[0011] A parameter optimization system for an incremental sigma-delta ADC based on a two-step search includes: a feedback path, a quantizer, a first-stage integrator, a second-stage integrator, a first feedforward path, a second feedforward path, a third feedforward path, undetermined coefficients b and c. The feedback path connects the summation node before the undetermined coefficient b to the output of the quantizer, processing the output signal of the quantizer to obtain the feedback signal. The first feedforward path connects the output of the modulator to the input of the quantizer, the second feedforward path connects the output of the first-stage integrator to the input of the quantizer, and the third feedforward path connects the output of the second-stage integrator to the input of the quantizer. The feedforward path performs a weighted summation of the input signal and the output signals of the first and second-stage integrators before quantization. The undetermined coefficients b and c are connected before the first and second-stage integrators, respectively. Based on the traditional incremental sigma-delta ADC, a two-step search algorithm is introduced to solve for the optimal b and c values ​​that meet the design requirements.

[0012] Furthermore, the incremental sigma delta ADC exhibits the following nonlinear relationship between its effective number of bits ENOB, number of conversion cycles M, and undetermined coefficients b and c:

[0013] ENOB=2log2(M)+log2(bc)-1 (1)

[0014] During the design phase, ENOB is a fixed metric, and when ENOB is determined, the value of M is entirely determined by the product of b and c:

[0015]

[0016] From equation (2), we can see that the larger the product of b and c, the fewer cycles M are required for a single conversion.

[0017] Furthermore, based on the traditional incremental Sigma-delta ADC, a two-step search algorithm is introduced to solve for the optimal b and c values ​​that meet the design requirements, including the following steps:

[0018] First, a second-order incremental Sigma-delta ADC model is built in Simulink, with the input signal amplitude, integrator sampling frequency, and forward path coefficients b and c set as variables. After modeling, the input signal amplitude, oversampling rate, integrator sampling frequency, and maximum integrator swing index are set in MATLAB according to design requirements. The forward path coefficients b and c are initialized to obtain an initial number of cycles. After initialization, a coarse search is performed, assigning values ​​to b and c in increments of 0.1 from 1 to 0.1. The Simulink model is called to calculate the maximum integrator swing, recording the results after each calculation before starting the next calculation. The search stops when both b and c are ≤ 0.1, and the initial screening values ​​of b and c are output. The b and c values ​​obtained from the coarse search are used as a fixed point. Values ​​within ±0.2 around this point are assigned to b and c in increments of 0.01 for a second fine search. After multiple calculations and comparisons, the final values ​​of b and c are output, which is the optimal solution that meets the design requirements.

[0019] Furthermore, in the Simulink modeling process, a CIFF modulator model is selected, and the following parameters are set as variables: the maximum amplitude of the input signal, umax, the number of single conversion cycles M (M is also the oversampling rate in incremental sigma delta ADC), the integrator sampling frequency 1 / M, and the undetermined forward path coefficients b and c.

[0020] Furthermore, during the initialization process, the effective number of ADC bits ENOB, the maximum amplitude of the input signal umax, the number of single conversion cycles M, the maximum swing of the first-stage integrator out1max, and the maximum swing of the second-stage integrator out2max are assigned values ​​according to the design requirements. The undetermined forward path coefficients b and c are initialized, and b and c are both initialized to 0.01. At the same time, the initial minimum value Mmin of M is calculated by equation (2).

[0021] Furthermore, during the rough search, values ​​of b and c are assigned sequentially from 1 to 0.1 in increments of 0.1, and the corresponding M value is calculated. If M is less than the current minimum number of cycles Mmin, the Simulink model is called to calculate the integrator swing. If the swings out1 and out2 of the two-stage integrator do not exceed the design requirements out1max and out2max, the b and c values ​​of this calculation are recorded, and the number of cycles M obtained in this calculation is recorded as the minimum number of cycles Mmin. Then, the next calculation begins. When both b and c are ≤ 0.1, the search stops and the last recorded b, c values ​​and Mmin value are output. The output of this step can locate the approximate location of the optimal solution.

[0022] Furthermore, during the fine search process, the b and c values ​​obtained from the rough search are used as fixed points. Values ​​within ±0.2 around this point are assigned to b and c in increments of 0.01, and the corresponding M value is calculated. If M is less than the current minimum cycle number Mmin, the Simulink model is called to calculate the integrator swing. If the swings out1 and out2 of the two-stage integrator do not exceed the design requirements out1max and out2max, the b and c values ​​calculated in this instance are recorded, and the cycle number M obtained in this instance is recorded as the minimum cycle number Mmin. Then, the next calculation begins. When b and c exceed the range of ±0.2 of the initial screening value or exceed the value boundary of 0.01-1, the search stops, and the last recorded b, c, and Mmin values ​​are output, which is the optimal solution that meets the design requirements.

[0023] The advantages and beneficial effects of this invention are as follows:

[0024] 1. This invention is based on the fundamental theory of incremental sigma delta ADC and has written relevant code programs and Simulink mathematical models. By continuously calling the simulation results of the model, the optimal b and c values ​​are obtained by solving and comparing them multiple times. Designers can directly input their requirements to obtain the optimal solution of the feedforward path coefficient of incremental sigma delta ADC. Compared with the traditional method of manual simulation and parameter iteration, this method is more accurate and faster, and achieves a certain degree of automation in electronic design.

[0025] 2. This invention employs a two-step search algorithm to find the optimal parameters. First, a coarse location with a precision of 0.1 is performed, and then a fine search with a precision of 0.01 is performed within a range of ±0.2 around that point. Compared with the exhaustive search method, most unnecessary calculations are omitted. While calculating the optimal solution, the computation time is fully considered. Test results show that the optimal parameters can be solved within 30 seconds, saving a lot of time. Attached Figure Description

[0026] Figure 1 This is a block diagram of a second-order CIFF sigma delta modulator system used in the present invention, provided in a preferred embodiment.

[0027] Figure 2 This is a flowchart of the algorithm used in this invention;

[0028] Figure 3 This is the output of the first-stage integrator when b = 0.62, c = 0.67, and umax = 0.6.

[0029] Figure 4 This is the output of the second-stage integrator when b = 0.62, c = 0.67, and umax = 0.6;

[0030] Figure 5 It is the quantization error of the ADC when b = 0.62, c = 0.67, and the input signal is -0.6 to 0.6. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. The described embodiments are merely some embodiments of the present invention.

[0032] The technical solution of the present invention to solve the above-mentioned technical problems is:

[0033] This application introduces a two-step search algorithm based on the traditional incremental Sigma-delta ADC. By using the nonlinear relationship between the undetermined coefficients b and c and the number of ADC conversion cycles M and the effective number of bits ENOB, ENOB = 2log2(M) + log2(bc)-1, the optimal b and c values ​​that meet the design requirements can be solved within the range of 0.01-1. Compared with the traditional method, this method can more accurately and quickly determine the best trade-off point between speed, accuracy and power consumption of the incremental Sigma-delta ADC.

[0034] Example

[0035] Assuming the design requirement is an ADC effective bit length ENOB ≥ 12 bits, a maximum input signal swing umax = 0.6, and the absolute values ​​of the maximum output swings out1max and out2max of the two-stage integrator are both 0.5, the steps to solve for the b and c values ​​that minimize the number of ADC single conversion cycles M using the incremental sigma delta ADC parameter optimization algorithm based on two-step search proposed in this invention are as follows:

[0036] First refer to Figure 1 The system block diagram is shown below. A second-order CIFF sigma-delta modulator is built in Simulink, with the input signal set to 0.6 and the integrator sampling frequency set to 1 / M. After the model is built, it looks like this: Figure 2 As shown, the variables such as the maximum swing of the two-stage integrator out1max, out2max, the maximum swing of the input signal umax, ENOB, and the forward path coefficients b and c are initialized.

[0037] After the variables are set, follow Figure 2 The algorithm is run directly in the process. After two rounds of search, namely coarse search and fine search, the optimal solution is finally obtained: b = 0.62, c = 0.67, M = 214.

[0038] To verify the correctness of the obtained parameters, these parameters were substituted into the Simulink model and simulation was run. Figure 3 , Figure 4 It can be seen that the swing amplitude of both integrators is within ±0.5, indicating that the obtained solution can satisfy the condition that the integrator does not overflow and makes full use of the swing range of the integrator.

[0039] After verifying that the swing meets the standard, it is also necessary to verify whether the ADC can achieve the predetermined ENOB ≥ 12 bits under this set of parameters. The method used here is to use... Figure 1 The model measures the output digital code of the ADC when the input signal varies between -0.6 and 0.6. After converting the output digital code into an analog value, the difference between the analog value and the true input value is calculated. The result is divided by the minimum resolution 1 / 2^12 to obtain the magnitude of the quantization error over the entire range.

[0040] The final measured curve of quantization error as a function of input signal is as follows: Figure 5 As shown, the quantization error of the ADC is within ±0.3 LSB throughout the entire measurement range, which meets the design requirements.

[0041] Those skilled in the art should understand that the two-step search incremental sigma delta ADC parameter optimization algorithm disclosed in this invention can be improved in various ways without departing from the scope of this invention.

[0042] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0043] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0044] The above embodiments should be understood as illustrative only and not as limiting the scope of protection of the present invention. After reading the description of the present invention, those skilled in the art can make various alterations or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. An incremental sigma-delta ADC parameter optimization system based on a two-step search, characterized in that, include: The system comprises a feedback path, a quantizer, a first-stage integrator, a second-stage integrator, a first feedforward path, a second feedforward path, a third feedforward path, undetermined coefficients b and c, wherein the feedback path is connected between the summation node before the undetermined coefficient b and the output of the quantizer, and the feedback path is used to process the output signal of the quantizer to obtain a feedback signal for the next calculation; the first-stage integrator is connected between the undetermined coefficient b and the second feedforward path, and the second-stage integrator is connected between the undetermined coefficient c and the third feedforward path, and the integrator is used for Sigma. The analog voltage addition and subtraction operations in the delta modulator are performed. The first feedforward path is connected between the output of the modulator and the input of the quantizer. The second feedforward path is connected between the output of the first-stage integrator and the input of the quantizer. The third feedforward path is connected between the output of the second-stage integrator and the input of the quantizer. The function of the feedforward path is to perform a weighted summation of the input signal and the output signals of the first and second-stage integrators before quantization. Undetermined coefficients b and c are connected before the first and second-stage integrators, respectively. The undetermined coefficients are used to determine the closed-loop gain of the integrator. Based on the traditional incremental sigma delta ADC, a two-step search algorithm is introduced to solve for the optimal b and c values ​​that meet the design requirements. The ratio of the sampling capacitor to the integrating capacitor is used to realize and apply the sigma delta modulator in the circuit. The incremental sigma delta ADC exhibits the following nonlinear relationship between its effective number of bits ENOB, number of conversion cycles M, and undetermined coefficients b and c: （1） During the design phase, ENOB is a fixed metric, and when ENOB is determined, the value of M is entirely determined by the product of b and c: （2） From equation (2), we can see that the larger the product of b and c, the fewer cycles M are required for a single conversion; The method, based on the traditional incremental Sigma-delta ADC, introduces a two-step search algorithm to solve for the optimal b and c values ​​that meet the design requirements, including the following steps: First, a second-order incremental Sigma-delta ADC model is built in Simulink, with the input signal amplitude, integrator sampling frequency, and forward path coefficients b and c set as variables. After modeling, in MATLAB, values ​​are assigned to the input signal amplitude, oversampling rate, integrator sampling frequency, and maximum integrator swing according to design requirements. The forward path coefficients b and c are initialized to obtain an initial number of cycles. After initialization, a coarse search is performed, assigning values ​​to b and c sequentially from 1 to 0.1 in steps of 0.

1. The Simulink model is called to calculate the maximum integrator swing. After each calculation, the result is recorded before starting the next calculation. The search stops when both b and c are ≤ 0.1, and the initial screening values ​​of b and c are output. The b and c values ​​obtained from the coarse search are used as a fixed point. Values ​​within ±0.2 around this point are assigned to b and c in steps of 0.01 for the second fine search. After multiple calculations and comparisons, the final values ​​of b and c are output, which is the optimal solution that meets the design requirements. In the Simulink modeling process, a CIFF modulator model is selected, and the following parameters are set as variables: maximum amplitude of input signal umax, number of single conversion cycles M, integrator sampling frequency 1 / M, and undetermined forward path coefficients b and c. During the initialization process, the effective number of ADC bits ENOB, the maximum amplitude of the input signal umax, the number of single conversion cycles M, the maximum swing of the first-stage integrator out1max, and the maximum swing of the second-stage integrator out2max are assigned according to the design requirements. The undetermined forward path coefficients b and c are initialized. The initial values ​​of b and c are both 0.

01. At the same time, the initial minimum value Mmin of M is calculated by equation (2). During the rough search, values ​​b and c are assigned sequentially from 1 to 0.1 in increments of 0.1, and the corresponding M value is calculated. If M is less than the current minimum number of cycles Mmin, the Simulink model is called to calculate the integrator swing. If the swings out1 and out2 of the two-stage integrator do not exceed the design requirements out1max and out2max, the b and c values ​​of this calculation are recorded, and the number of cycles M obtained in this calculation is recorded as the minimum number of cycles Mmin. Then the next calculation begins. When both b and c are ≤ 0.1, the search stops and the last recorded b, c values ​​and Mmin value are output. The output of this step can locate the approximate location of the optimal solution. During the fine search, the b and c values ​​obtained from the rough search are used as fixed points. Values ​​within ±0.2 around this point are assigned to b and c in increments of 0.01, and the corresponding M value is calculated. If M is less than the current minimum cycle number Mmin, the Simulink model is called to calculate the integrator swing. If the swings out1 and out2 of the two integrators do not exceed the design requirements out1max and out2max, the b and c values ​​calculated in this iteration are recorded, and the cycle number M obtained in this iteration is recorded as the minimum cycle number Mmin. Then, the next calculation begins. When b and c exceed the range of ±0.2 of the initial screening value or exceed the value boundary of 0.01-1, the search stops, and the last recorded b, c, and Mmin values ​​are output, which is the optimal solution that meets the design requirements.

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