Pixel circuit and driving method thereof, display panel, and display device

Abstract

Provided are a pixel circuit and a driving method thereof, a display panel, and a display device, belonging to the field of display technology. The pixel circuit includes a light-emitting control circuit, a driving circuit, and a negative feedback circuit. The light-emitting control circuit can control the potential of each node from the first node to the fourth node in the pixel circuit. The driving circuit can control the potential of the third node based on the potential of the first node and the second node. When the third node and the fourth node are connected, the light-emitting element can emit light based on the potential of the third node. The negative feedback circuit can adjust the potential of the first node based on the potential of the target node among the third node and the fourth node, so that the potential of the first node and the potential of the target node undergo the same change, thereby enabling the driving circuit to control the potential of the third node based on the adjusted potential of the first node, so as to reliably drive the light-emitting element to emit light, thereby ensuring that the display effect of the display panel can be better.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display panel, and a display device. Background Art

[0002] Organic light-emitting diode (OLED) display panels are widely used in various display devices due to their advantages such as self-luminescence, fast response speed, and low energy consumption.

[0003] In the related art, an OLED display panel generally includes: a substrate, and a plurality of pixels located on the substrate. Each pixel includes a pixel circuit and a light-emitting element. Among them, the pixel circuit includes a driving transistor, and the pixel circuit is respectively coupled to multiple signal terminals (such as gate signal terminals) and light-emitting elements. The pixel circuit is used to generate a driving current through the driving transistor based on the signals provided by the multiple signal terminals and transmit it to the light-emitting element to drive the light-emitting element to emit light, so that the OLED display panel can display the desired display image.

[0004] However, due to the bias state of the driving transistor in the pixel circuit (such as the negative bias state of the P-type transistor), the driving current transmitted by the pixel circuit to the light-emitting element will change, causing the light-emitting element to be unable to emit light reliably, and the display effect of the OLED display panel is poor. Summary of the Invention

[0005] Provided are a pixel circuit and a driving method thereof, a display panel, and a display device, which can solve the problem in the related art that the light-emitting element cannot emit light reliably due to changes in the driving current transmitted by the pixel circuit to the light-emitting element, resulting in poor display quality of the display panel. The technical solution is as follows:

[0006] In one aspect, a pixel circuit is provided, comprising:

[0007] a light-emitting control circuit, coupled to a gate signal terminal, a reset signal terminal, a light-emitting control signal terminal, a data signal terminal, an initial power supply terminal, a first power supply terminal, a first node, a second node, a third node, and a fourth node, respectively, for controlling the connection and disconnection between the data signal terminal and the second node, controlling the connection and disconnection between the initial power supply terminal and the fourth node, and controlling the connection and disconnection between the third node and the first node in response to a gate drive signal provided by the gate signal terminal; for controlling the connection and disconnection between the initial power supply terminal and the first node in response to a reset signal provided by the reset signal terminal; and for controlling the connection and disconnection between the first power supply terminal and the second node, and controlling the connection and disconnection between the third node and the fourth node in response to a light-emitting control signal provided by the light-emitting control signal terminal;

[0008] a driving circuit, coupled to the first node, the second node, and the third node, respectively, for controlling a potential of the third node based on a potential of the first node and a potential of the second node;

[0009] A negative feedback circuit is coupled to the first node and is also coupled to a target node among the fourth node and the third node, and is used to adjust the potential of the first node based on the potential of the target node. The fourth node is also used to couple to the first pole of the light-emitting element, and the second pole of the light-emitting element is also coupled to the second power supply terminal. The light-emitting element is used to emit light based on the potential of the first pole and the potential of the second pole.

[0010] Optionally, the negative feedback circuit includes: a coupling element, wherein the coupling element is configured to adjust the potential of the first node based on the potential of the target node through a coupling effect.

[0011] Optionally, the coupling element includes: a coupling capacitor, one end of the coupling capacitor is coupled to the target node, and the other end of the coupling capacitor is coupled to the first node.

[0012] Optionally, the target node is the fourth node.

[0013] Optionally, the driving circuit includes: a driving transistor;

[0014] The gate of the driving transistor is coupled to the first node, the first electrode of the driving transistor is coupled to the second node, and the second electrode of the driving transistor is coupled to the third node.

[0015] Optionally, the driving transistor is a P-type transistor.

[0016] Optionally, the light emitting control circuit is further configured to adjust the potential of the first node based on a first power signal provided by the first power supply terminal; the light emitting control circuit includes:

[0017] a data writing sub-circuit, coupled to the gate signal terminal, the data signal terminal and the second node respectively, for controlling the connection and disconnection between the data signal terminal and the second node in response to the gate driving signal;

[0018] a compensation sub-circuit, coupled to the gate signal terminal, the third node, and the first node, respectively, for controlling the connection and disconnection of the third node and the first node in response to the gate drive signal;

[0019] a reset subcircuit, coupled to the gate signal terminal, the reset signal terminal, the initial power supply terminal, the first node, and the fourth node, respectively, for controlling the connection and disconnection between the initial power supply terminal and the fourth node in response to the gate drive signal, and for controlling the connection and disconnection between the initial power supply terminal and the first node in response to the reset signal;

[0020] a light-emitting control subcircuit, coupled to the light-emitting control signal terminal, the first power terminal, the second node, the third node, and the fourth node, respectively, for controlling the connection and disconnection between the first power terminal and the second node, and controlling the connection and disconnection between the third node and the fourth node in response to the light-emitting control signal;

[0021] The regulating sub-circuit is coupled to the first power supply terminal and the first node respectively, and is used to regulate the potential of the first node based on the first power supply signal.

[0022] Optionally, the data writing subcircuit includes: a data writing transistor; the compensation subcircuit includes: a compensation transistor; the reset subcircuit includes: a first reset transistor and a second reset transistor; the light emitting control subcircuit includes: a first light emitting control transistor and a second light emitting control transistor; the regulation subcircuit includes: a storage capacitor;

[0023] The gate of the data writing transistor is coupled to the gate signal terminal, the first electrode of the data writing transistor is coupled to the data signal terminal, and the second electrode of the data writing transistor is coupled to the second node;

[0024] The gate of the compensation transistor is coupled to the gate signal terminal, the first electrode of the compensation transistor is coupled to the third node, and the second electrode of the compensation transistor is coupled to the first node;

[0025] The gate of the first reset transistor is coupled to the reset signal terminal, the first electrode of the first reset transistor is coupled to the initial power supply terminal, and the second electrode of the first reset transistor is coupled to the first node;

[0026] The gate of the second reset transistor is coupled to the gate signal terminal, the first electrode of the second reset transistor is coupled to the initial power supply terminal, and the second electrode of the second reset transistor is coupled to the fourth node;

[0027] The gate of the first light emitting control transistor is coupled to the light emitting control signal terminal, the first electrode of the first light emitting control transistor is coupled to the first power supply terminal, and the second electrode of the first light emitting control transistor is coupled to the second node;

[0028] The gate of the second light emitting control transistor is coupled to the light emitting control signal terminal, the first electrode of the second light emitting control transistor is coupled to the third node, and the second electrode of the second light emitting control transistor is coupled to the fourth node;

[0029] One end of the storage capacitor is coupled to the first power supply end, and the other end of the storage capacitor is coupled to the first node.

[0030] Optionally, the data writing transistor, the first light emission control transistor, the second light emission control transistor and the second reset transistor are all P-type transistors; the first reset transistor and the compensation transistor are both N-type transistors;

[0031] The gate signal terminal includes: a first gate signal terminal and a second gate signal terminal providing gate drive signals with different potentials; the initial power supply terminal includes: a first initial power supply terminal and a second initial power supply terminal providing initial power supply signals with different potentials;

[0032] The gate of the data writing transistor and the gate of the second reset transistor are both coupled to the first gate signal terminal, and the gate of the compensation transistor is coupled to the second gate signal terminal;

[0033] A first electrode of the first reset transistor is coupled to the first initial power supply terminal, and a second electrode of the second reset transistor is coupled to the second initial power supply terminal.

[0034] Optionally, in the pixel circuit, the active layer material of the P-type transistor includes: low-temperature polysilicon material; the active layer material of the N-type transistor includes: oxide material.

[0035] On the other hand, a method for driving a pixel circuit is provided, which is applied to the pixel circuit according to the above aspect, and the method includes:

[0036] In the first stage, the light emitting control circuit controls the initial power supply terminal to be connected to the first node in response to the reset signal provided by the reset signal terminal;

[0037] In the second stage, the light emitting control circuit controls the initial power supply terminal to be connected to the fourth node, controls the data signal terminal to be connected to the second node, and controls the third node to be connected to the first node in response to the gate driving signal provided by the gate signal terminal.

[0038] In a third stage, the light emitting control circuit controls the first power supply terminal to be electrically connected to the second node, and controls the third node to be electrically connected to the fourth node in response to the light emitting control signal provided by the light emitting control signal terminal. The driving circuit controls the potential of the third node based on the potential of the first node and the potential of the second node, so that the light emitting element emits light based on the potentials of the first electrode and the second electrode of the light emitting element.

[0039] In the fourth stage, the negative feedback circuit adjusts the potential of the first node based on the potential of the target node among the third node and the fourth node, so that the potential change of the first node is the same as the potential change of the target node;

[0040] The first stage, the second stage and the third stage are located in a refresh frame, and the fourth stage is located in a hold frame after the refresh frame.

[0041] Optionally, the negative feedback circuit adjusts the potential of the first node based on the potential of a target node among the third node and the fourth node, including:

[0042] The negative feedback circuit adjusts the potential of the first node based on the potential of a target node between the third node and the fourth node through a coupling effect.

[0043] In yet another aspect, a display panel is provided, comprising: a substrate, and a plurality of pixels located on the substrate;

[0044] Among them, at least one pixel includes: a light-emitting element, and a pixel circuit as described in the above aspect, wherein the pixel circuit is coupled to the light-emitting element and is used to drive the light-emitting element to emit light.

[0045] In another aspect, a display device is provided, comprising: a signal providing circuit, and the display panel according to the above aspect;

[0046] The signal providing circuit is coupled to each signal terminal coupled to pixels in the display panel and is used to provide a signal to each signal terminal.

[0047] In summary, the beneficial effects brought about by the technical solutions provided by the embodiments of the present disclosure may include at least:

[0048] Provided are a pixel circuit and a driving method thereof, a display panel, and a display device. The pixel circuit includes a light-emitting control circuit, a driving circuit, and a negative feedback circuit. The light-emitting control circuit is capable of controlling the potential of each node from the first node to the fourth node in the pixel circuit. The driving circuit is capable of controlling the potential of the third node based on the potentials of the first node and the second node. When the third node and the fourth node are conductive, the light-emitting element can emit light based on the potential of the third node. The negative feedback circuit is capable of adjusting the potential of the first node based on the potential of a target node among the third node and the fourth node, so that the potential of the first node and the potential of the target node undergo the same change, thereby enabling the driving circuit to control the potential of the third node based on the adjusted potential of the first node, thereby reliably driving the light-emitting element to emit light and ensuring a better display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0050] Figure 1 This is a brightness waveform diagram when switching to display different grayscale images provided by an embodiment of the present disclosure;

[0051] Figure 2 is a structural diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0052] Figure 3 is a structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0053] Figure 4 is a structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0054] Figure 5 is a structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0055] Figure 6 is a flowchart of a driving method of a pixel circuit provided by an embodiment of the present disclosure;

[0056] Figure 7 is a timing diagram of a signal terminal coupled to a pixel circuit provided by an embodiment of the present disclosure;

[0057] Figure 8 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0058] Figure 9It is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0060] For display products such as OLED display panels, low-frequency or high-frequency driving is generally used to display the screen. Among them, low frequency and high frequency are relative. Low frequency generally refers to a few hertz (Hz) or more than ten Hz, such as the common 1Hz and 10Hz. High frequency generally refers to several hundred Hz, such as the common 120Hz. Among them, low-frequency driving can help reduce system power consumption and improve the battery life of the display panel compared to high-frequency driving. However, for screen refresh, it is smoother under high-frequency driving, and when driven at low frequency, due to the longer frame cycle time, the human eye can clearly perceive the refresh feeling, and flickering problems are more likely to occur.

[0061] For example, taking a low frequency of 1Hz and a LongV driving method in which the charging time remains unchanged at low frequency compared to high frequency driving, at a base frequency of 120Hz, a 1Hz frame period generally includes 1 refresh frame and 119 hold frames, a total of 120 sub-frames (sub-Frame). Data can be written in the refresh frame, and the picture can be maintained in the hold frame, that is, the state of the displayed picture is maintained. The frame period of this low frequency 1Hz is generally 1 second (s). When switching to display different grayscale pictures, the operating voltage of the driving transistor in the OLED display panel will change, and the threshold voltage Vth of the driving transistor cannot be effectively compensated. In this way, there are differences in the driving current generated by the driving transistor to drive the light-emitting element to emit light, which in turn causes a continuous change in brightness within the hold frame, which can be manifested as a continuous increase or a continuous decrease.

[0062] Moreover, taking the switching display from a black screen to a white screen as an example, since the threshold voltage Vth when displaying a white screen is lower than the threshold voltage Vth when displaying a black screen, the threshold voltage Vth needs to gradually transition from one state to another after switching. As time goes by, the threshold voltage Vth can tend to be stable, that is, it no longer changes. Therefore, after the screen switches, the brightness changes in the first few frames are obvious, which can be perceived by the human eye, manifested as a sense of screen refresh, resulting in the so-called low-frequency ghosting display abnormality problem.

[0063] For example, combined with Figure 1 , which takes a low frequency of 10Hz as an example, shows a schematic diagram of brightness after black face switching. Among them, TE signal refers to the refresh frame, and the waveform change after TE signal refers to the brightness change within the maintenance frame. Figure 1It can be seen that when switching from a white image with a grayscale of L0 to a black image with a grayscale of L255, the brightness of the first frame after the switch is generally more noticeable, and the brightness of subsequent frames also experiences brightness attenuation, but the degree of attenuation gradually decreases until the brightness stabilizes. When switching from a white image with a grayscale of L255 to a black image with a grayscale of L32, the brightness of the first frame after the switch is generally more noticeable, and the brightness of subsequent frames also experiences brightness increase, but the degree of increase gradually decreases until the brightness stabilizes. That is, under a low-frequency drive of 10Hz, when switching from a white image with a grayscale of L0 to a black image with a grayscale of L255, the brightness of the frame after the switch is continuously decreasing; when switching from a white image with a grayscale of L255 to a black image with a grayscale of L32, the brightness of the frame after the switch is continuously increasing.

[0064] It should be noted that the process of threshold voltage Vth changing from large to small can be called negative drift, and the process of threshold voltage Vth changing from small to large can be called positive drift. Here, positive drift and negative drift are relative. In addition, black screen and white screen are also relative and are not used to limit specific grayscale values. For example, Figure 1 , the picture of grayscale L0 and the picture of grayscale L32 can both be called black pictures relative to the white picture of grayscale L255.

[0065] It should also be noted that the disclosed embodiments focus on improving the low-frequency ghosting problem. This primarily addresses the problem of image refresh stuttering caused by the driver transistor's threshold voltage (Vth) remaining uncompensated for a long period of time within the frame during image refresh under low-frequency drive. This is different from the more common FFR and afterimage problems. The FFR (first frame ratio) problem refers to insufficient brightness in the first frame after a frame switch. The afterimage problem refers to the residual content of the previous frame.

[0066] Currently, interpolation is a common approach to addressing low-frequency artifacts. This involves inserting high-frequency frames between frames, essentially switching from low-frequency to high-frequency drive. After refreshing multiple frames, the system switches back to low-frequency drive, for example, switching from 1Hz to 120Hz and then back to 1Hz. However, high-frequency interpolation takes too long (e.g., 2 to 3 seconds), hindering power consumption. This defeats the purpose of low-frequency drive and doesn't meet application requirements.

[0067] The disclosed embodiment provides a pixel circuit design that can effectively suppress the brightness attenuation of the frame during low-frequency driving, improve the ghosting problem of low-frequency image refresh, and will not affect the effect of reducing power consumption.

[0068] Figure 2 Schematic diagram of a pixel circuit provided by an embodiment of the present disclosure. Figure 2As shown, the pixel circuit includes: a light emitting control circuit 01 , a driving circuit 02 , and a negative feedback circuit 03 .

[0069] The light-emitting control circuit 01 is coupled (i.e., electrically connected) to the gate signal terminal Gate, the reset signal terminal Re, the light-emitting control signal terminal EM, the data signal terminal Data, the initial power terminal Vinit, the first power terminal VDD, the first node N1, the second node N2, the third node N3, and the fourth node N4, respectively. The light-emitting control circuit 01 is configured to control the connection between the data signal terminal Data and the second node N2, the connection between the initial power terminal Vinit and the fourth node N4, and the connection between the third node N3 and the first node N1 in response to a gate drive signal provided by the gate signal terminal Gate. It is also configured to control the connection between the initial power terminal Vinit and the first node N1 in response to a reset signal provided by the reset signal terminal Re. It is also configured to control the connection between the first power terminal VDD and the second node N2, and the connection between the third node N3 and the fourth node N4 in response to a light-emitting control signal provided by the light-emitting control signal terminal EM.

[0070] For example, when the gate drive signal provided by the gate signal terminal Gate is at a valid potential, the light-emitting control circuit 01 can control the data signal terminal Data to be electrically conductive with the second node N2, the initial power supply terminal Vinit to be electrically conductive with the fourth node N4, and the third node N3 to be electrically conductive with the first node N1. At this point, the data signal provided by the data signal terminal Data can be further transmitted to the second node N2 to charge the second node N2. The initial power signal provided by the initial power supply terminal Vinit can be further transmitted to the fourth node N4 to reduce noise at the fourth node N4. Furthermore, the potentials of the first node N1 and the third node N3 can affect each other. Furthermore, when the gate drive signal provided by the gate signal terminal Gate is at a valid potential, the light-emitting control circuit 01 can control the data signal terminal Data to be decoupled from the second node N2, the initial power supply terminal Vinit to be decoupled from the fourth node N4, and the third node N3 to be decoupled from the first node N1.

[0071] Similarly, the light-emission control circuit 01 can control the initial power supply terminal Vinit to be electrically connected to the first node N1 when the reset signal provided by the reset signal terminal Re is at an active potential. In this case, the initial power signal provided by the initial power supply terminal Vinit can be further transmitted to the first node N1 to reduce noise at the first node N1. Furthermore, the light-emission control circuit 01 can control the initial power supply terminal Vinit to be disconnected from the first node N1 when the reset signal provided by the reset signal terminal Re is at an inactive potential.

[0072] Similarly, when the potential of the light-emitting control signal provided by the light-emitting control signal terminal EM is at an active potential, the light-emitting control circuit 01 can control the first power supply terminal VDD to be electrically connected to the second node N2, and can also control the third node N3 to be electrically connected to the fourth node N4. In this case, the first power supply signal provided by the first power supply terminal VDD can be further transmitted to the second node N2, and the signal transmitted to the third node N3 can be further transmitted to the fourth node N4. Furthermore, when the potential of the light-emitting control signal provided by the light-emitting control signal terminal EM is at an inactive potential, the light-emitting control circuit 01 can control the first power supply terminal VDD to be decoupled from the second node N2, and can control the third node N3 to be decoupled from the fourth node N4.

[0073] It should be noted that, of the effective potential and the invalid potential, one can be a high potential and the other can be a low potential, and the high potential and low potential here are also relative. Furthermore, taking the transistor coupled to the gate signal terminal Gate in the light-emitting control circuit 01 as an example, if the transistor is an N-type transistor, then for the transistor, the effective potential of the gate drive signal provided by the gate signal terminal Gate can be a high potential, and the invalid potential of the gate drive signal can be a low potential. If the transistor is a P-type transistor, then for the transistor, the effective potential of the gate drive signal can be a low potential, and the invalid potential of the gate drive signal can be a high potential. The same applies to other transistors and will not be described in detail.

[0074] The driving circuit 02 is coupled to the first node N1, the second node N2 and the third node N3 respectively. The driving circuit 02 is used to control the potential of the third node N3 based on the potential of the first node N1 and the potential of the second node N2.

[0075] For example, when applied to an OLED display panel, the driving circuit 02 can generate a light-emitting driving signal (ie, a driving current) for driving the OLED to emit light based on the potential of the first node N1 and the potential of the second node N2, and transmit it to the third node N3.

[0076] Negative feedback circuit 03 is coupled to first node N1 and also to a target node, either fourth node N4 or third node N3. Specifically, it may be coupled to either fourth node N4 or third node N3. Of course, in some other embodiments, it may also be coupled to fourth node N4 and / or third node N3. Negative feedback circuit 03 is configured to adjust the potential of first node N1 based on the potential of the target node. Furthermore, fourth node N4 is also coupled to a first electrode of light-emitting element L1. A second electrode of light-emitting element L1 is also coupled to second power supply terminal VSS. Light-emitting element L1 is configured to emit light based on the potentials of the first electrode and the second electrode.

[0077] For example, when the light-emitting control circuit 01 controls the third node N3 and the fourth node N4 to be turned on, the potential of the third node N3 (e.g., the light-emitting drive signal generated by the drive circuit 02) can be further transmitted to the fourth node N4. The light-emitting element L1 can emit light based on the voltage difference between the light-emitting drive signal and the second power signal provided by the second power supply terminal VSS. Optionally, one of the first and second poles of the light-emitting element L1 can be an anode and the other can be a cathode. The embodiment of the present disclosure is described by taking the first pole as an anode and the second pole as a cathode as an example. On this basis, the potential of the first power signal provided by the first power supply terminal VDD can be a high potential, and the potential of the second power signal provided by the second power supply terminal VSS can be a low potential.

[0078] It should be noted that, in the embodiment of the present disclosure, the negative feedback circuit 03 can adjust the potential of the first node N1 based on the potential of the target node, so that the potential change of the first node N1 is the same as the potential change of the target node. The potential change includes: the change mode (such as reduction) and the change size (such as reducing the potential of the same size at the same time). In this way, the signal generated by the driving circuit 02 based on the potential of the first node N1 (such as a light-emitting driving signal in the form of a driving current) can be indirectly reverse-regulated to form a negative feedback. For example, in the scenario of low-frequency driving of the OLED display panel, when the potential of the target node is reduced, the negative feedback circuit 03 can control the potential of the first node N1 to decrease synchronously with the potential of the target node, thereby reversely increasing the driving current generated by the driving circuit 02 based on the potential of the first node N1, suppressing the problem of maintaining brightness attenuation within the frame due to the reduction in the potential of the target node, thereby effectively improving the low-frequency smearing problem.

[0079] In summary, an embodiment of the present disclosure provides a pixel circuit. The pixel circuit includes a light-emitting control circuit, a driving circuit, and a negative feedback circuit. The light-emitting control circuit is capable of controlling the potential of each node from the first node to the fourth node in the pixel circuit. The driving circuit is capable of controlling the potential of the third node based on the potentials of the first node and the second node. When the third node and the fourth node are turned on, the light-emitting element can emit light based on the potential of the third node. The negative feedback circuit is capable of adjusting the potential of the first node based on the potential of the target node among the third node and the fourth node, so that the potential of the first node and the potential of the target node undergo the same change, thereby enabling the driving circuit to control the potential of the third node based on the adjusted potential of the first node, so as to reliably drive the light-emitting element to emit light, thereby ensuring that the display effect of the display panel can be better.

[0080] Optionally, the light emitting control circuit 01 may also be configured to adjust the potential of the first node N1 based on a first power signal provided by the first power terminal VDD.

[0081] On this basis, reference Figure 3As can be seen from the structural schematic diagram of another pixel circuit shown, the light-emitting control circuit 01 recorded in the embodiment of the present disclosure may include: a data writing sub-circuit 011, a compensation sub-circuit 012, a reset sub-circuit 013, a light-emitting control sub-circuit 014, and a regulation sub-circuit 015.

[0082] The data writing sub-circuit 011 can be coupled to the gate signal terminal Gate, the data signal terminal Data and the second node N2 respectively, and can be used to control the connection and disconnection of the data signal terminal Data and the second node N2 in response to the gate driving signal.

[0083] For example, the data writing sub-circuit 011 can control the data signal terminal Data to be connected to the second node N2 when the potential of the received gate drive signal is a valid potential, and can control the data signal terminal Data to be disconnected from the second node N2 when the potential of the received gate drive signal is an invalid potential.

[0084] The compensation sub-circuit 012 may be coupled to the gate signal terminal Gate, the third node N3 and the first node N1 respectively, and may be used to control the connection and disconnection between the third node N3 and the first node N1 in response to the gate driving signal.

[0085] For example, the compensation sub-circuit 012 can control the third node N3 to be conductive with the first node N1 when the potential of the received gate drive signal is a valid potential, and can control the third node N3 to be disconnected from the first node N1 when the potential of the received gate drive signal is an invalid potential.

[0086] The reset sub-circuit 013 can be coupled to the gate signal terminal Gate, the reset signal terminal Re, the initial power supply terminal Vinit, the first node N1 and the fourth node N4 respectively, and can be used to control the connection and disconnection of the initial power supply terminal Vinit and the fourth node N4 in response to the gate drive signal, and to control the connection and disconnection of the initial power supply terminal Vinit and the first node N1 in response to the reset signal.

[0087] For example, the reset sub-circuit 013 can control the initial power supply terminal Vinit to be electrically connected to the fourth node N4 when the potential of the received gate drive signal is a valid potential, and can control the initial power supply terminal Vinit to be disconnected from the fourth node N4 when the potential of the received gate drive signal is a de-asserted potential. Similarly, the reset sub-circuit 013 can control the initial power supply terminal Vinit to be electrically connected to the first node N1 when the potential of the received reset signal is a valid potential, and can control the initial power supply terminal Vinit to be disconnected from the first node N1 when the potential of the received reset signal is a de-asserted potential.

[0088] The light-emitting control sub-circuit 014 can be coupled to the light-emitting control signal terminal EM, the first power supply terminal VDD, the second node N2, the third node N3 and the fourth node N4 respectively, and can be used to control the on-off of the first power supply terminal VDD and the second node N2, and control the on-off of the third node N3 and the fourth node N4 in response to the light-emitting control signal.

[0089] For example, the light-emitting control subcircuit 014 can control the first power supply terminal VDD to be connected to the second node N2 and the third node N3 to be connected to the fourth node N4 when the potential of the received light-emitting control signal is a valid potential, and can control the first power supply terminal VDD to be disconnected from the second node N2 and the third node N3 to be disconnected from the fourth node N4 when the potential of the received light-emitting control signal is an invalid potential.

[0090] The regulating sub-circuit 015 may be coupled to the first power supply terminal VDD and the first node N1 respectively, and configured to regulate the potential of the first node N1 based on the first power supply signal.

[0091] Optionally, the negative feedback circuit 03 described in the embodiment of the present disclosure may include: a coupling element. The coupling element may be used to adjust the potential of the first node N1 based on the potential to the target node through the coupling effect. For example, refer to Figure 4 It can be seen from the structure of another pixel circuit that the coupling element in the embodiment of the present disclosure may include: a coupling capacitor C1.

[0092] One end of the coupling capacitor C1 may be coupled to the target node, and the other end of the coupling capacitor C1 may be coupled to the first node N1. Of course, in some other embodiments, the coupling element may also be other electronic elements with the same coupling function, such as a coupling transformer.

[0093] Optionally, the target node recorded in the embodiment of the present disclosure may be the fourth node N4. Figure 4 As shown, one end of the coupling capacitor C1 can be coupled to the fourth node N4. Accordingly, the coupling capacitor C1 can adjust the potential of the first node N1 based on the potential of the fourth node N4. Because the fourth node N4 is directly coupled to the light-emitting element L1, the potential of the first node N1 can be further reliably adjusted, forming a good negative feedback mechanism, avoiding changes in the driving current used to drive the light-emitting element L1, and effectively improving the low-frequency smear problem.

[0094] Alternatively, refer to Figure 5 As can be seen from the structure of another pixel circuit shown, the target node may be the third node N3 , that is, one end of the coupling capacitor C1 may be coupled to the third node N3 .

[0095] Optional, continue to refer to Figure 4 and Figure 5 It can be seen that the driving circuit 02 described in the embodiment of the present disclosure may include: a driving transistor T1.

[0096] A gate electrode of the driving transistor T1 may be coupled to the first node N1 , a first electrode of the driving transistor T1 may be coupled to the second node N2 , and a second electrode of the driving transistor T1 may be coupled to the third node N3 .

[0097] It should be noted that, for a transistor, among its first electrode and second electrode, one electrode may be a source (S) electrode, and the other electrode may be a drain (D) electrode.

[0098] Optionally, the driving transistor T1 can be a P-type transistor. Accordingly, the effective potential it receives is a low potential, and it is in a negative bias state for a long time, and the threshold voltage Vth will drift negatively. On this basis, when the potential of the target node is reduced due to the negative drift of the threshold voltage Vth of the driving transistor T1, the negative feedback circuit 03 can control the potential of the first node N1 to decrease synchronously through its coupling effect, that is, the gate potential of the driving transistor T1 is reduced, and then the gate-source voltage difference Vgs of the driving transistor will increase, and the driving current generated by the driving transistor T1 will also increase accordingly, forming a negative feedback as described in the above embodiment, suppressing the phenomenon of continuous attenuation of frame brightness under low-frequency driving caused by DTFT NBTS, and improving the low-frequency smearing problem. DTFT NBTS is generally used to measure the stability of the driving transistor characteristics under long-term negative bias.

[0099] Optional, continue to refer to Figure 4 and Figure 5 As can be seen, the data writing sub-circuit 011 may include a data writing transistor T2. The compensation sub-circuit 012 may include a compensation transistor T3. The reset sub-circuit 013 may include a first reset transistor T4 and a second reset transistor T5. The light emission control sub-circuit 014 may include a first light emission control transistor T6 and a second light emission control transistor T7. The regulation sub-circuit 015 may include a storage capacitor Cst.

[0100] The gate of the data writing transistor T2 may be coupled to the gate signal terminal Gate, the first electrode of the data writing transistor T2 may be coupled to the data signal terminal Data, and the second electrode of the data writing transistor T2 may be coupled to the second node N2.

[0101] A gate of the compensation transistor T3 may be coupled to the gate signal terminal Gate, a first electrode of the compensation transistor T3 may be coupled to the third node N3 , and a second electrode of the compensation transistor T3 may be coupled to the first node N1 .

[0102] A gate of the first reset transistor T4 may be coupled to the reset signal terminal Re, a first electrode of the first reset transistor T4 may be coupled to the initial power terminal Vinit, and a second electrode of the first reset transistor T4 may be coupled to the first node N1.

[0103] A gate of the second reset transistor T5 may be coupled to the gate signal terminal Gate, a first electrode of the second reset transistor T5 may be coupled to the initial power supply terminal Vinit, and a second electrode of the second reset transistor T5 may be coupled to the fourth node N4.

[0104] A gate of the first light emitting control transistor T6 may be coupled to the light emitting control signal terminal EM, a first electrode of the first light emitting control transistor T6 may be coupled to the first power supply terminal VDD, and a second electrode of the first light emitting control transistor T6 may be coupled to the second node N2.

[0105] A gate of the second light emitting control transistor T7 may be coupled to the light emitting control signal terminal EM, a first electrode of the second light emitting control transistor T7 may be coupled to the third node N3, and a second electrode of the second light emitting control transistor T7 may be coupled to the fourth node N4.

[0106] One end of the storage capacitor Cst may be coupled to the first power supply terminal VDD, and the other end of the storage capacitor Cst may be coupled to the first node N1.

[0107] Optional, reference Figure 4 and Figure 5 It can also be seen that in the embodiment of the present disclosure, like the driving transistor T1, the data writing transistor T2, the first emission control transistor T6, the second emission control transistor T7, and the second reset transistor T5 can all be P-type transistors. The first reset transistor T4 and the compensation transistor T3 can all be N-type transistors.

[0108] Optionally, the active layer material of the P-type transistor may include a low-temperature polysilicon (LTPS) material. The active layer material of the N-type transistor may include an oxide material. On this basis, a pixel circuit including both P-type and N-type transistors may be referred to as an LTPO pixel circuit, and a pixel circuit including only P-type transistors may be referred to as an LTPS pixel circuit.

[0109] Figure 4 and Figure 5The pixel circuits shown are all LTPO pixel circuits, and all of them are based on the 7T1C (i.e., 7 transistors and 1 storage capacitor) pixel circuit structure with a new coupling capacitor C1. That is, the pixel circuit design method provided in the embodiment of the present disclosure can be applied to the 7T1C LTPO pixel circuit. Of course, in some other embodiments, it is also applicable to LTPO pixel circuits of other structures (such as 6T1C). Alternatively, it is also applicable to the LTPS pixel circuit described in the above embodiment.

[0110] Since transistors made of oxide materials have low leakage characteristics, the second reset transistor T5 for resetting the anode of the light-emitting element L1 (i.e., the fourth node N4) is set to an oxide N-type transistor. This allows the anode of the light-emitting element L1 to be reset at a high frequency for noise reduction, thereby reducing the low-frequency component during low-frequency driving, effectively improving the voltage holding rate of a long frame period under low-frequency driving, and reducing the flicker visibility to the human eye.

[0111] It should be noted that, continue to refer to Figure 4 and Figure 5 It can also be seen that based on the LTPO pixel circuit design, the gate signal terminal Gate may include: a first gate signal terminal Gate-P and a second gate signal terminal Gate-N providing gate drive signals with different potentials. The initial power supply terminal Vinit includes: a first initial power supply terminal Vinit-1 and a second initial power supply terminal Vinit-2 providing initial power supply signals with different potentials.

[0112] Among them, the gate of the data write transistor T2, which is a P-type transistor, and the gate of the second reset transistor T5 can both be coupled to the first gate signal terminal Gate-P, and the gate of the compensation transistor T3, which is an N-type transistor, can be coupled to the second gate signal terminal Gate-N. The first electrode of the first reset transistor T4, which is an N-type transistor, can be coupled to the first initial power supply terminal Vinit-1, and the second electrode of the second reset transistor T5, which is a P-type transistor, can be coupled to the second initial power supply terminal Vinit-2. And on this basis, it can be seen that the effective potential of the gate drive signal provided by the first gate signal terminal Gate-P is a low potential relative to the invalid potential. The effective potential of the gate drive signal provided by the second gate signal terminal Gate-N is a high potential relative to the invalid potential.

[0113] In summary, an embodiment of the present disclosure provides a pixel circuit. The pixel circuit includes a light-emitting control circuit, a driving circuit, and a negative feedback circuit. The light-emitting control circuit is capable of controlling the potential of each node from the first node to the fourth node in the pixel circuit. The driving circuit is capable of controlling the potential of the third node based on the potentials of the first node and the second node. When the third node and the fourth node are turned on, the light-emitting element can emit light based on the potential of the third node. The negative feedback circuit is capable of adjusting the potential of the first node based on the potential of the target node among the third node and the fourth node, so that the potential of the first node and the potential of the target node undergo the same change, thereby enabling the driving circuit to control the potential of the third node based on the adjusted potential of the first node, so as to reliably drive the light-emitting element to emit light, thereby ensuring that the display effect of the display panel can be better.

[0114] Figure 6 This is a flowchart of a driving method for a pixel circuit provided by an embodiment of the present disclosure. The method is applied to Figures 2 to 5 In any of the pixel circuits shown. Figure 6 As shown, the method includes:

[0115] Step 601, in the first stage, the light emitting control circuit controls the initial power supply terminal to be connected to the first node in response to the reset signal provided by the reset signal terminal.

[0116] At this time, the initial power signal provided by the initial power terminal can be transmitted to the first node to reset the first node. Accordingly, this first stage can also be called a reset stage.

[0117] Step 602, second stage, the light emitting control circuit controls the initial power supply terminal to be connected to the fourth node, controls the data signal terminal to be connected to the second node, and controls the third node to be connected to the first node in response to the gate driving signal provided by the gate signal terminal.

[0118] At this point, the data signal provided by the data signal terminal can be transmitted to the second node to charge the second node. Furthermore, the potential of the first node and the potential of the third node can interact with each other, thereby achieving threshold voltage compensation. Accordingly, this first stage can also be called the data writing and Vth compensation stage.

[0119] Step 603, the third stage, the light-emitting control circuit controls the first power supply terminal and the second node to be conductive, and controls the third node and the fourth node to be conductive in response to the light-emitting control signal provided by the light-emitting control signal terminal, and the driving circuit controls the potential of the third node based on the potential of the first node and the potential of the second node, so that the light-emitting element emits light based on the potential of the first pole and the second pole of the light-emitting element.

[0120] At this point, a path is formed between the first power supply terminal and the fourth node, and the pixel circuit can generate a driving current through the driving transistor and transmit it to the fourth node, that is, to the first electrode of the light-emitting element, thereby driving the light-emitting element to emit light. Accordingly, this third stage can also be called the light-emitting stage.

[0121] Step 604 , the fourth stage: the negative feedback circuit adjusts the potential of the first node based on the potential of the target node among the third node and the fourth node, so that the potential change of the first node is the same as the potential change of the target node.

[0122] For example, based on the above embodiments, it can be seen that when the potential of the target node decreases due to the negative bias of the driving transistor, the negative feedback circuit can synchronously adjust the potential of the first node to decrease, thereby reversely increasing the drive current generated by the driving circuit based on the adjusted potential of the first node, suppressing the problem of brightness attenuation within the frame caused by the decrease in the potential of the target node, thereby effectively improving the low-frequency smearing problem. Accordingly, this fourth stage can also be called the negative feedback stage.

[0123] The first stage, the second stage and the third stage may be located in a refresh frame, and the fourth stage may be located in a hold frame after the refresh frame.

[0124] Optional, such as Figure 4 and Figure 5 As shown, the negative feedback circuit 03 described in the embodiment of the present disclosure includes a coupling capacitor C1. Accordingly, in the above step 604, the negative feedback circuit adjusts the potential of the first node based on the potential of the target node among the third node and the fourth node, which may include: the negative feedback circuit adjusts the potential of the first node based on the potential of the target node among the third node and the fourth node through the coupling effect.

[0125] by Figure 4 Take the structure shown as an example, Figure 7 FIG1 shows a timing diagram of each signal terminal coupled to a pixel circuit. Figure 7 As shown, the driving process of the pixel circuit may include refresh frames and hold frames executed sequentially. Taking 1 Hz low-frequency driving as an example, as described in the above embodiment, at a base frequency of 120 Hz, a 1 Hz frame period generally includes 1 refresh frame and 119 hold frames, totaling 120 subframes.

[0126] The refresh frame may include a first phase (ie, a reset phase), a second phase (ie, a data writing and Vth compensation phase), and a third phase (ie, a light emitting phase) that are sequentially executed.

[0127] In the first phase t1, the potential of the gate driving signal provided by the first gate signal terminal Gate-P may be high, the potential of the gate driving signal provided by the second gate signal terminal Gate-N may be low, the potential of the reset signal provided by the reset signal terminal Re may be high, and the potential of the light emitting control signal provided by the light emitting control signal terminal EM may be high. Accordingly, Figure 4 Among the multiple transistors included in the pixel circuit shown, the first reset transistor T4 can be turned on, and the remaining transistors such as the data writing transistor T2, the compensation transistor T3, the second reset transistor T5, the first light-emitting control transistor T6 and the second light-emitting control transistor T7 can all be turned off. At this time, the initial power signal provided by the first initial power supply terminal Vinit-1 can be transmitted to the first node N1 through the turned-on first reset transistor T4 to perform noise reduction reset on the first node N1. Accordingly, the driving transistor T1 can be turned off. Since the driving transistor T1 is a P-type transistor, the potential of the initial power signal can be a high potential. That is, in the first stage t1, the potential of the driving transistor T1 can be reset to V Vinit-1 , V Vinit-1 Refers to the potential of the initial power supply signal.

[0128] In the second phase t2, the potential of the gate driving signal provided by the first gate signal terminal Gate-P may be low, the potential of the gate driving signal provided by the second gate signal terminal Gate-N may be high, the potential of the reset signal provided by the reset signal terminal Re may be low, and the potential of the light emitting control signal provided by the light emitting control signal terminal EM may be high. Accordingly, Figure 4 Among the multiple transistors included in the pixel circuit shown, the data write transistor T2, the second reset transistor T5, and the compensation transistor T3 can all be turned on, and the remaining transistors, such as the first reset transistor T4, the first light-emitting control transistor T6, and the second light-emitting control transistor T7, can all be turned off. At this time, the data signal provided by the data signal terminal Data can be transmitted to the second node N2 through the turned-on data write transistor T2. The initial power signal provided by the second initial power terminal Vinit-2 can be transmitted to the fourth node N4 through the turned-on second reset transistor T5 to perform noise reduction and reset on the fourth node N4 (i.e., the anode of the light-emitting element L1), preparing for the subsequent light-emitting stage and improving the light-emitting contrast. The driving transistor T1 can be regarded as a diode connection method, and the storage capacitor Cst can be charged until the potential of the first node N1 becomes: Vdata+Vth. Wherein, Vdata refers to the potential of the data signal, and Vth refers to the threshold voltage of the driving transistor T1.

[0129] In the third stage t3, the potential of the gate driving signal provided by the first gate signal terminal Gate-P may be high, the potential of the gate driving signal provided by the second gate signal terminal Gate-N may be low, the potential of the reset signal provided by the reset signal terminal Re may be low, and the potential of the light emitting control signal provided by the light emitting control signal terminal EM may be low. Accordingly, Figure 4 Among the multiple transistors included in the pixel circuit shown, the first emission control transistor T6 and the second emission control transistor T7 are both turned on. Drive transistor T1 also remains on at this time due to the action of storage capacitor Cst. The remaining transistors, including the data write transistor T2, the first reset transistor T4, the second reset transistor T5, and the compensation transistor T3, can be turned off. At this point, a path is formed between the first power supply terminal VDD and the fourth node N4 via the first emission control transistor T6, the drive transistor T1, and the second emission control transistor T7, which are all turned on in series. Drive transistor T1 can generate a drive current based on the potentials of the first node N1 and the second node N2. This current is transmitted to the anode of light-emitting element L1 via the fourth node N4, thereby driving light-emitting element L1 to emit light. Furthermore, in the second phase t2, after compensation by compensation transistor T3, the generated drive current is independent of the threshold voltage Vth of drive transistor T1. After this phase, the potential Vn1 of the first node N1 can be: Vn1 = Vdata + Vth. The potential Vn4 of the fourth node N4 can be: Vn4 = Vss + Voled. Vss refers to the potential of the second power signal provided by the second power terminal VSS coupled to the cathode of light-emitting element L1, and Voled refers to the voltage across the anode and cathode of light-emitting element L1. Based on the calculation formula for Vn4, the potential of the fourth node N4 is related to the voltage across the electrodes of light-emitting element L1 when in the light-emitting state. Generally, the voltage across light-emitting element L1 is positively correlated with the drive current flowing through light-emitting element L1. That is, the greater the drive current, the greater the voltage across the electrodes, and thus the brighter the light; conversely, the smaller the drive current, the smaller the voltage across the electrodes, and thus the dimmer the light.

[0130] After that, the holding frame is entered, the potential of the gate driving signal provided by the second gate signal terminal Gate-N can be kept at a low potential, and the potential of the reset signal provided by the reset signal terminal Re can be kept at a low potential. Figure 4 Among the multiple transistors included in the pixel circuit shown, the first reset transistor T4 and the compensation transistor T3 can always be in the off state, and the potential of the first node N1 can be stored and maintained by the storage capacitor Cst without being affected by the data signal again.

[0131] Because the P-type driving transistor T1 is always in a negative bias state, the threshold voltage Vth of the driving transistor T1 inevitably drifts negatively, and the generated driving current decreases, which will cause the brightness attenuation problem described in the above embodiment to occur in the holding frame. In the embodiment of the present disclosure, when the driving current decreases, that is, the potential of the fourth node N4 decreases due to the negative drift of the threshold voltage Vth of the driving transistor T1, the coupling effect of the coupling capacitor C1 can pull the potential of the first node N1 to decrease synchronously in the holding frame, that is, the gate potential of the driving transistor T1 is reduced. As can be seen, the gate-source voltage difference Vgs of the driving transistor T1 will increase accordingly, and the generated driving current will also increase, forming the so-called negative feedback, suppressing the problem of continuous brightness attenuation in the holding frame caused by the driving transistor T1 being in a negative bias state, thereby effectively improving the low-frequency smearing phenomenon and ensuring a good display effect.

[0132] In addition, reference Figure 7 It can also be seen that the potential of the gate drive signal provided by the first gate signal terminal Gate-P and the potential of the light-emitting control signal provided by the light-emitting control signal terminal EM can include high and low potentials. This allows the first light-emitting control transistor T6 and the second light-emitting control transistor T7 to be in a high-frequency (e.g., 240 Hz) on-state to achieve brightness adjustment. Furthermore, the second reset transistor T5 is also in a high-frequency (e.g., 120 Hz) on-state to high-frequency reset the anode of the light-emitting element L1, thereby improving flicker and further ensuring a better display effect.

[0133] In summary, the embodiments of the present disclosure provide a method for driving a pixel circuit. In this method, the light-emitting control circuit included in the pixel circuit is capable of controlling the potential of each node from the first node to the fourth node in the pixel circuit. The driving circuit included in the pixel circuit is capable of controlling the potential of the third node based on the potentials of the first node and the second node. When the third node and the fourth node are turned on, the light-emitting element can emit light based on the potential of the third node. The negative feedback circuit included in the pixel circuit is capable of adjusting the potential of the first node based on the potential of the target node among the third node and the fourth node, so that the potential of the first node and the potential of the target node undergo the same change, thereby enabling the driving circuit to control the potential of the third node based on the adjusted potential of the first node, so as to reliably drive the light-emitting element to emit light, thereby ensuring that the display effect of the display panel can be better.

[0134] Figure 8 Schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Figure 8 As shown, the display panel includes: a substrate B1, and a plurality of pixels P1 located on the substrate B1.

[0135] Wherein, at least one pixel P1 includes: a light emitting element L1, and Figures 2 to 5 In any of the pixel circuits 00 shown, the pixel circuit 00 is coupled to the light-emitting element L1 and is used to drive the light-emitting element L1 to emit light.

[0136] For example, combined with Figures 2 to 5 Pixel circuit 00 can be coupled to the anode of light-emitting element L1, and the cathode of light-emitting element L1 can be coupled to the second power supply terminal VSS. Pixel circuit 00 can transmit a light-emitting drive signal to the anode of light-emitting element L1, and light-emitting element L1 can emit light under the voltage difference between the light-emitting drive signal and the second power supply signal provided by the second power supply terminal VSS.

[0137] Figure 9 Schematic diagram of a display device provided by an embodiment of the present disclosure. Figure 9 As shown, the display device includes: a signal providing circuit 100, and Figure 8 Display panel 000 is shown.

[0138] Among them, combined Figure 8 It can be seen that the signal providing circuit 100 can be coupled to each signal terminal coupled to the pixel P1 in the display panel 000 and is used to provide a signal to each signal terminal.

[0139] For example, the signal providing circuit 100 may include a gate driver circuit and a source driver circuit. The gate driver circuit may be coupled to a gate signal terminal Gate coupled to the pixel circuit 00 in the pixel P1 and configured to provide a gate driver signal to the gate signal terminal Gate. The source driver circuit may be coupled to a data signal terminal Data coupled to the pixel circuit 00 in the pixel P1 and configured to provide a data signal to the data signal terminal Data.

[0140] Optionally, the display device described in the embodiments of the present disclosure may include: an organic light-emitting diode (OLED) display device, a mobile phone, a tablet computer, a flexible display device, a television, a monitor, or any other product or component with a display function.

[0141] The terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the common meaning understood by people with ordinary skills in the field to which the present disclosure belongs.

[0142] For example, in the embodiments of the present disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless otherwise clearly defined.

[0143] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0144] Words such as “include” or “comprising” mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0145] “Up,” “down,” “left,” or “right” are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0146] "And / or" indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0147] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A pixel circuit, characterized in that: The pixel circuit comprises: a light-emitting control circuit, coupled to a gate signal terminal, a reset signal terminal, a light-emitting control signal terminal, a data signal terminal, an initial power supply terminal, a first power supply terminal, a first node, a second node, a third node, and a fourth node, respectively, for controlling the connection and disconnection between the data signal terminal and the second node, controlling the connection and disconnection between the initial power supply terminal and the fourth node, and controlling the connection and disconnection between the third node and the first node in response to a gate drive signal provided by the gate signal terminal; for controlling the connection and disconnection between the initial power supply terminal and the first node in response to a reset signal provided by the reset signal terminal; and for controlling the connection and disconnection between the first power supply terminal and the second node, and controlling the connection and disconnection between the third node and the fourth node in response to a light-emitting control signal provided by the light-emitting control signal terminal; a driving circuit, coupled to the first node, the second node, and the third node, respectively, for controlling a potential of the third node based on a potential of the first node and a potential of the second node; a negative feedback circuit coupled to the first node and also coupled to a target node among the fourth node and the third node, and configured to adjust the potential of the first node based on the potential of the target node; the fourth node is further configured to be coupled to a first electrode of a light-emitting element, a second electrode of the light-emitting element is further coupled to a second power supply terminal, and the light-emitting element is configured to emit light based on the potentials of the first electrode and the second electrode; The negative feedback circuit includes: a coupling capacitor, one end of which is coupled to the target node, and the other end of which is coupled to the first node; the coupling capacitor is used to adjust the potential of the first node based on the potential of the target node.

2. The pixel circuit according to claim 1, wherein: The target node is the fourth node.

3. The pixel circuit according to claim 1, wherein: The driving circuit includes: a driving transistor; The gate of the driving transistor is coupled to the first node, the first electrode of the driving transistor is coupled to the second node, and the second electrode of the driving transistor is coupled to the third node.

4. The pixel circuit according to claim 3, wherein: The driving transistor is a P-type transistor.

5. The pixel circuit according to claim 1 or 4, characterized in that: The light emitting control circuit is further configured to adjust the potential of the first node based on a first power signal provided by the first power terminal; The light emitting control circuit includes: a data writing sub-circuit, coupled to the gate signal terminal, the data signal terminal and the second node respectively, for controlling the connection and disconnection between the data signal terminal and the second node in response to the gate driving signal; a compensation sub-circuit, coupled to the gate signal terminal, the third node, and the first node, respectively, for controlling the connection and disconnection of the third node and the first node in response to the gate drive signal; a reset subcircuit, coupled to the gate signal terminal, the reset signal terminal, the initial power supply terminal, the first node, and the fourth node, respectively, for controlling the connection and disconnection between the initial power supply terminal and the fourth node in response to the gate drive signal, and for controlling the connection and disconnection between the initial power supply terminal and the first node in response to the reset signal; a light-emitting control subcircuit, coupled to the light-emitting control signal terminal, the first power terminal, the second node, the third node, and the fourth node, respectively, for controlling the connection and disconnection between the first power terminal and the second node, and controlling the connection and disconnection between the third node and the fourth node in response to the light-emitting control signal; The regulating sub-circuit is coupled to the first power supply terminal and the first node respectively, and is used to regulate the potential of the first node based on the first power supply signal.

6. The pixel circuit according to claim 5, wherein: The data writing subcircuit includes: a data writing transistor; the compensation subcircuit includes: a compensation transistor; the reset subcircuit includes: a first reset transistor and a second reset transistor; the light emitting control subcircuit includes: a first light emitting control transistor and a second light emitting control transistor; the regulation subcircuit includes: a storage capacitor; The gate of the data writing transistor is coupled to the gate signal terminal, the first electrode of the data writing transistor is coupled to the data signal terminal, and the second electrode of the data writing transistor is coupled to the second node; The gate of the compensation transistor is coupled to the gate signal terminal, the first electrode of the compensation transistor is coupled to the third node, and the second electrode of the compensation transistor is coupled to the first node; The gate of the first reset transistor is coupled to the reset signal terminal, the first electrode of the first reset transistor is coupled to the initial power supply terminal, and the second electrode of the first reset transistor is coupled to the first node; The gate of the second reset transistor is coupled to the gate signal terminal, the first electrode of the second reset transistor is coupled to the initial power supply terminal, and the second electrode of the second reset transistor is coupled to the fourth node; The gate of the first light emitting control transistor is coupled to the light emitting control signal terminal, the first electrode of the first light emitting control transistor is coupled to the first power supply terminal, and the second electrode of the first light emitting control transistor is coupled to the second node; The gate of the second light emitting control transistor is coupled to the light emitting control signal terminal, the first electrode of the second light emitting control transistor is coupled to the third node, and the second electrode of the second light emitting control transistor is coupled to the fourth node; One end of the storage capacitor is coupled to the first power supply terminal, and the other end of the storage capacitor is coupled to the first node.

7. The pixel circuit according to claim 6, wherein: The data writing transistor, the first light emission control transistor, the second light emission control transistor and the second reset transistor are all P-type transistors; The first reset transistor and the compensation transistor are both N-type transistors; Wherein, the gate signal terminal includes: a first gate signal terminal and a second gate signal terminal providing gate drive signals with different potentials; the initial power supply terminal includes: a first initial power supply terminal and a second initial power supply terminal providing initial power supply signals with different potentials; The gate of the data writing transistor and the gate of the second reset transistor are both coupled to the first gate signal terminal, and the gate of the compensation transistor is coupled to the second gate signal terminal; A first electrode of the first reset transistor is coupled to the first initial power supply terminal, and a second electrode of the second reset transistor is coupled to the second initial power supply terminal.

8. The pixel circuit according to claim 7, wherein: In the pixel circuit, the active layer material of the P-type transistor includes: low-temperature polysilicon material; the active layer material of the N-type transistor includes: oxide material.

9. A method for driving a pixel circuit, characterized in that: Applied to the pixel circuit according to any one of claims 1 to 8, the method comprises: In the first stage, the light emitting control circuit controls the initial power supply terminal to be connected to the first node in response to the reset signal provided by the reset signal terminal; In the second stage, the light emitting control circuit controls the initial power supply terminal to be connected to the fourth node, controls the data signal terminal to be connected to the second node, and controls the third node to be connected to the first node in response to the gate driving signal provided by the gate signal terminal. In a third stage, the light emitting control circuit controls the first power supply terminal to be electrically connected to the second node, and controls the third node to be electrically connected to the fourth node in response to the light emitting control signal provided by the light emitting control signal terminal. The driving circuit controls the potential of the third node based on the potential of the first node and the potential of the second node, so that the light emitting element emits light based on the potentials of the first electrode and the second electrode of the light emitting element. In the fourth stage, the negative feedback circuit adjusts the potential of the first node based on the potential of the target node among the third node and the fourth node, so that the potential change of the first node is the same as the potential change of the target node; The first stage, the second stage and the third stage are located in a refresh frame, and the fourth stage is located in a hold frame after the refresh frame.

10. The method according to claim 9, characterized in that The negative feedback circuit adjusts the potential of the first node based on the potential of a target node among the third node and the fourth node, including: The negative feedback circuit adjusts the potential of the first node based on the potential of a target node between the third node and the fourth node through a coupling effect.

11. A display panel, characterized in that: The display panel includes: a substrate, and a plurality of pixels located on the substrate; Wherein, at least one pixel includes: a light-emitting element, and a pixel circuit according to any one of claims 1 to 8, wherein the pixel circuit is coupled to the light-emitting element and is used to drive the light-emitting element to emit light.

12. A display device, characterized in that: The display device comprises: a signal providing circuit, and the display panel according to claim 1; The signal providing circuit is coupled to each signal terminal coupled to each pixel in the display panel and is used to provide a signal to each signal terminal.

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