Method of forming contact structures, semiconductor structures, and memories

Abstract

The application discloses a contact structure forming method, a semiconductor structure and a memory. The method comprises the following steps: providing a substrate, forming a sacrificial layer on the substrate, performing a patterning process on the sacrificial layer to form a first gap exposing the substrate in the sacrificial layer, depositing a dielectric layer in the first gap, removing the sacrificial layer to form a second gap between the dielectric layers, and performing an etching process on at least part of the dielectric layer outside the second gap to expand the opening size of the second gap. The embodiment of the application can avoid the situation of insufficient etching, and help solve the open circuit problem of the contact structure under high aspect ratio etching.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a contact structure, a semiconductor structure, and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. With advancements in DRAM manufacturing processes, the size of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) continues to shrink, while the aspect ratio (AR) of their contact structures becomes increasingly larger. Under-etching is highly susceptible to occur at high aspect ratios (HAR), leading to open circuits. Summary of the Invention

[0003] This application provides a method for forming a contact structure, a semiconductor structure, and a memory, which can obtain a structure with a good aspect ratio and help solve the problem of open circuit caused by insufficient etching in the contact structure at high aspect ratio.

[0004] According to some embodiments, a first aspect of this application provides a method for forming a contact structure, including:

[0005] Provide a substrate, on which a sacrificial layer is formed;

[0006] The sacrificial layer is patterned to form a first gap that exposes the substrate.

[0007] A dielectric layer is deposited in the first gap;

[0008] Remove the sacrificial layer to form a second gap between the dielectric layers;

[0009] At least a portion of the dielectric layer surrounding the second gap is etched to enlarge the opening size of the second gap.

[0010] Optionally, the substrate is a conductive substrate.

[0011] Optionally, a plurality of the first gaps are formed on the substrate, and a sacrificial layer is provided between each of the first gaps. In a direction parallel to the substrate, the sacrificial layer between each of the first gaps has a maximum size, which is less than or equal to one-tenth of the opening size of the first gap.

[0012] Optionally, the sacrificial layer has a first height in a direction perpendicular to the substrate, the first height being not less than one-tenth of the maximum dimension of the sacrificial layer.

[0013] Optionally, the dielectric layer includes a first dielectric layer and a second dielectric layer located on the first dielectric layer. In a direction perpendicular to the substrate, the first dielectric layer has a first thickness, the second dielectric layer has a second thickness, and the first thickness is greater than the second thickness.

[0014] Optionally, adjacent sacrificial layers are spaced apart in a direction parallel to the substrate, the spacing gradually decreasing in a direction perpendicular to the substrate.

[0015] Optionally, the method for forming the contact structure further includes:

[0016] The second gap, after being etched, is filled with conductive material to form a contact structure.

[0017] Optionally, a wet cleaning process may be used to remove the sacrificial layer and / or at least a portion of the deposited medium layer surrounding the second gap.

[0018] According to some embodiments, a second aspect of this application provides a semiconductor structure, including:

[0019] Base;

[0020] A dielectric layer is located on the substrate, and the dielectric layer has a second gap, which has different dimensions in a direction parallel to the substrate;

[0021] A contact structure that fills the second gap.

[0022] Optionally, the substrate includes a layer of metal conductors.

[0023] Optionally, the contact structure has a first height in a direction perpendicular to the substrate, and a maximum dimension in a direction parallel to the substrate, wherein the first height is not less than one-tenth of the maximum dimension.

[0024] Optionally, the dielectric layer includes a first dielectric layer and a second dielectric layer located on the first dielectric layer. In a direction perpendicular to the substrate, the first dielectric layer has a first thickness, the second dielectric layer has a second thickness, and the first thickness is greater than the second thickness.

[0025] Optionally, in a direction parallel to the substrate, the contact structure has a first maximum size in the second gap in the first dielectric layer, and the contact structure has a second maximum size in the second gap in the second dielectric layer, wherein the second maximum size is not less than the first maximum size.

[0026] Optionally, the second maximum size is larger than the first maximum size.

[0027] According to some embodiments, a third aspect of this application provides a semiconductor memory including the contact structure described in any of the foregoing embodiments.

[0028] The above-described technical solutions of this application have at least the following beneficial technical effects:

[0029] The contact structure formation method provided in this application first deposits a sacrificial layer on a substrate, then forms a first gap and a dielectric layer filling the first gap in the sacrificial layer, and finally forms a second gap for filling the contact structure after removing the sacrificial layer. In this method, the second gap is less prone to insufficient etching, which helps solve the problem of open circuits caused by insufficient etching in contact structures with high aspect ratios. Furthermore, before filling the contact structure, the method also etches at least a portion of the dielectric layer surrounding the sacrificial layer, thereby increasing the opening size of the second gap and reducing the contact resistance of the contact structure. Attached Figure Description

[0030] Figure 1 This is a schematic flowchart of a method for forming a contact structure according to an embodiment of this application;

[0031] Figures 2-7 This is a process for forming a contact structure according to an embodiment of this application;

[0032] Figure 8 This is a schematic diagram of a contact structure provided according to an embodiment of this application;

[0033] Figure 9 This is a schematic diagram of a semiconductor structure provided according to an embodiment of this application;

[0034] In the figure, 100 is the substrate; 200 is the sacrificial layer; 300 is the first gap; 400 is the dielectric layer; 410 is the first dielectric layer; 420 is the second dielectric layer; 500 is the second gap; 600 is the contact structure; D is the maximum dimension; H is the first height; h1 is the first thickness; h2 is the second thickness; d1 is the first maximum dimension; and d2 is the second maximum dimension. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to specific implementation methods and accompanying drawings. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the embodiments of this application. Furthermore, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of this application.

[0036] like Figure 1 As shown, a method for forming a contact structure includes:

[0037] S10. Provide a substrate 100 and form a sacrificial layer 200 on the substrate 100.

[0038] S20. The sacrificial layer 200 is patterned to form a first gap 300 in the sacrificial layer 200 that exposes the substrate 100.

[0039] S30, Deposit a medium layer 400 in the first gap 300.

[0040] S40. Remove the sacrificial layer 200 and form a second gap 500 between the dielectric layers 400.

[0041] S50, At least a portion of the dielectric layer 400 surrounding the second gap 500 is etched to enlarge the opening size of the second gap 500.

[0042] The method for forming the contact structure 600 provided in this application embodiment first deposits a sacrificial layer 200 on a substrate 100, then forms a first gap 300 and a dielectric layer 400 filling the first gap 300 in the sacrificial layer 200, and then forms a second gap 500 for filling the contact structure 600 after removing the sacrificial layer 200. In this method, the second gap 500 is less likely to be under-etched, which helps to solve the problem of open circuit caused by under-etching of the contact structure 600 at high aspect ratios.

[0043] In some embodiments, the substrate 100 is a conductive substrate 100.

[0044] For example, the substrate 100 can be a conductive layer on a substrate, wherein the substrate can be a semiconductor substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a single-crystal metal oxide substrate, etc. Multiple deep trenches can be formed on the surface of the substrate, and isolation materials are filled within these trenches to form isolation regions. These isolation regions isolate several active regions from the substrate. The isolation regions can isolate several active regions arranged in an array or other distribution types. The active regions can be formed by implanting impurities into the substrate; for example, active regions can be formed by ion implantation. The conductive layer can be a wire layer electrically connected to the active regions of the substrate, or it can be a wire layer interconnected with other wires. It should be noted that those skilled in the art will understand that the substrate also includes other structures besides the isolation regions and active regions for the normal operation of the memory.

[0045] like Figure 2 As shown, in step S10, a sacrificial layer 200 is formed on the substrate 100.

[0046] In some embodiments, the sacrificial layer 200 may be polycrystalline silicon, monocrystalline silicon, or silicide. The sacrificial layer 200 may be formed by spin-on deposition (SOD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or high-density plasma-enhanced chemical vapor deposition (HDP-CVD). For example, the sacrificial layer 200 may be polycrystalline silicon formed by spin-on deposition, while the sacrificial layer 200 formed by SOD may have better adhesion and gap-filling ability.

[0047] like Figure 3 As shown, in step S20, a first gap 300 is formed in the sacrificial layer 200 to expose the substrate 100.

[0048] In some embodiments, a plurality of first gaps 300 are formed on the substrate 100, and a sacrificial layer 200 is provided between each first gap 300. In a direction parallel to the substrate 100, the sacrificial layer 200 between each first gap 300 has a maximum size D, which is less than or equal to one-tenth of the opening size of the first gap 300.

[0049] In some embodiments, the opening size of the first gap 300 may gradually decrease in a direction perpendicular to the substrate 100, so that the sacrificial layer 200 between the first gaps 300 is trapezoidal, thereby preventing the sacrificial layer 200 from collapsing during the formation of the first gap 300. Exemplarily, adjacent sacrificial layers 200 have a spacing in a direction parallel to the substrate 100, the spacing gradually decreasing in a direction perpendicular to the substrate.

[0050] In other exemplary embodiments, the opening size of the first gap 300 may also remain unchanged in the direction perpendicular to the base 100.

[0051] In some embodiments, the formation process of the first gap 300 can be wet etching or dry etching, for example, wet etching using phosphoric acid (H3PO4) as the etching solution or dry etching using N2 plasma as the etching gas.

[0052] In some embodiments, in order to make the formed contact structure 600 a high aspect ratio structure, the sacrificial layer 200 between each of the first gaps 300 has a first height H in a direction perpendicular to the substrate, the first height H being not less than one-tenth of the maximum dimension D of the sacrificial layer 200.

[0053] like Figure 4 As shown, in step S30, a medium layer 400 is deposited in the first gap 300.

[0054] In some embodiments, the dielectric layer 400 may include silicon oxide, silicon nitride, silicon oxynitride, etc. For example, the dielectric layer 400 can be formed using undoped silicate glass (USG), spin-on glass (SOG), phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate-phosphosilicate glass (BPSG), flowable oxide (FOX), tetraethylorthosilicate (TEOS), plasma-enhanced TEOS (PE-TEOS), Tonen silazane (TOSZ), high-density plasma chemical vapor deposition (HDP-CVD) oxides, etc. These can be used individually or in combination. Furthermore, the dielectric layer 400 can be formed using spin coating processes, chemical vapor deposition (CVD) processes, plasma-enhanced chemical vapor deposition (PECVD) processes, high-density plasma chemical vapor deposition (HDP-CVD) processes, etc.

[0055] In some embodiments, the dielectric layer 400 includes a first dielectric layer 410 and a second dielectric layer 420 located on the first dielectric layer 410. In a direction perpendicular to the substrate 100, the first dielectric layer 410 has a first thickness h1, and the second dielectric layer 420 has a second thickness h2. The first thickness h1 is greater than the second thickness h2.

[0056] For example, the method for forming the dielectric layer 400 may be: depositing a first dielectric film in the first gap 300; removing a portion of the first dielectric film so that its surface reaches a preset height to form a first dielectric layer 410; depositing a second dielectric film in the first gap 300 and on the first dielectric layer 410; removing a portion of the second dielectric film so that its surface is flush with the surface of the sacrificial layer 200 to form a second dielectric layer 420.

[0057] like Figure 5 As shown, in step S40, the sacrificial layer 200 is removed, and a second gap 500 is formed between the dielectric layers 400.

[0058] In some embodiments, the sacrificial layer 200 can be removed by a wet cleaning process, for example, wet etching using phosphoric acid (H3PO4) as the etchant.

[0059] In this embodiment, the wet cleaning method can achieve a certain etching selectivity between the sacrificial layer 200 and the dielectric layer 400 by selecting a suitable etching material. This prevents the etching of the dielectric layer 400 during the etching of the sacrificial layer 200, thus avoiding damage to the structure. In other embodiments, the sacrificial layer 200 is made of a carbon-containing material. During the subsequent removal of the sacrificial layer 200 to form the second gap 500, the sacrificial layer 200 can be removed by ashing. The ashing gas reacts with the carbon-containing material to generate carbon dioxide gas, thereby converting the sacrificial layer 200 into gaseous carbon dioxide and removing it. This avoids a significant impact on the dielectric layer 400 on the sidewall during the formation of the second gap 500, preventing collapse.

[0060] like Figure 6 As shown, in step S50, at least a portion of the dielectric layer 400 surrounding the second gap 500 is etched to enlarge the opening size of the second gap 500.

[0061] In some embodiments, enlarging the opening size of the second gap 500 can be achieved by etching the second dielectric layer 420. After the opening size of the second gap 500 is enlarged, the resulting contact structure 600 can have a smaller contact resistance. Considering that the final size of the second gap 500 is also required, the second dielectric layer 420 does not need to be too thick, because if the second dielectric layer 420 is too thick, it may result in an excessively large top opening size, while the size of the subsequent gaps is not effectively enlarged.

[0062] In some embodiments, a wet etching process can be used to etch at least a portion of the second dielectric layer 420 surrounding the second gap 500. For example, wet etching using phosphoric acid (H3PO4) as the etchant.

[0063] like Figure 7 As shown, in some embodiments, the method of forming the contact structure 600 further includes:

[0064] The second gap 500, after being etched, is filled with conductive material to form a contact structure 600.

[0065] For example, the material of the contact structure 600 may include tungsten, silicon nitride, silicon oxynitride, etc. For instance, the barrier layer may be formed using undoped silicate glass (USG), spin-on glass (SOG), phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate-phosphosilicate glass (BPSG), flowable oxide (FOX), tetraethylorthosilicate (TEOS), plasma-enhanced TEOS (PE-TEOS), Tonen silazane (TOSZ), high-density plasma chemical vapor deposition (HDP-CVD) oxides, etc. These may be used individually or in combination.

[0066] like Figure 8 As shown in the illustration, this application also provides a contact structure, including:

[0067] 100 for the substrate;

[0068] A dielectric layer 400 is located on the substrate 100, and the dielectric layer 400 has a second gap 500, which has different dimensions in a direction parallel to the substrate 100.

[0069] Contact structure 600, the contact structure 600 filling the second gap 500.

[0070] The contact structure 600 provided in this application embodiment can first deposit a sacrificial layer 200 on a substrate 100, then form a first gap 300 and a dielectric layer 400 filling the first gap 300 in the sacrificial layer 200, and then form a second gap 500 for filling the contact structure 600 after removing the sacrificial layer 200. In this method, the second gap 500 is less likely to be under-etched, which helps to solve the problem of open circuit caused by insufficient etching in the contact structure 600 at high aspect ratios.

[0071] In some embodiments, the substrate 100 includes a metal wire layer.

[0072] For example, the substrate 100 includes a conductive layer on a substrate, wherein the substrate may be a semiconductor substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a single-crystal metal oxide substrate, etc. Multiple deep trenches may be formed on the surface region of the substrate, and isolation materials are filled within the deep trenches to form isolation regions. Several active regions are isolated from the substrate by the isolation regions. The isolation regions may isolate several active regions in an array or other distribution type. The active regions can be formed by implanting impurities into the substrate; for example, active regions can be formed by ion implantation. It should be noted that those skilled in the art will understand that the substrate also includes other memory structures besides the isolation regions and active regions for the normal operation of the memory.

[0073] In some embodiments, to make the formed contact structure 600 a high aspect ratio structure, the contact structure 600 has a first height H in the direction perpendicular to the substrate 100 and a maximum dimension D in the direction parallel to the substrate 100, wherein the first height H is not less than one-tenth of the maximum dimension D.

[0074] In some embodiments, in a direction parallel to the substrate 100, the contact structure 600 has a first maximum size d1 in the second gap 500 in the first dielectric layer 410. In this embodiment, the first maximum size d1 is equal to the maximum size D of the contact structure 600. The contact structure 600 has a second maximum size d2 in the second gap 500 in the second dielectric layer 420. The second maximum size d2 is not less than the first maximum size d1.

[0075] For example, the first maximum size d1 can be the size of the end of the contact structure 600 adjacent to the substrate 100, and the second maximum size d2 can be the size of the end of the contact structure 600 in the first dielectric layer 410 away from the substrate 100. The contact structure 600 formed in this way has a large contact area and therefore a small contact resistance.

[0076] To form the contact structure 600 with the first maximum size d1 and the second maximum size d2 at its two ends, a matching second gap 500 can be formed first. For example, to form the matching second gap 500, a trapezoidal gap can be formed in the dielectric layer first, and then the opening of the trapezoidal gap can be enlarged by etching to form the required second gap 500.

[0077] In some embodiments, the dielectric layer 400 can be designed in layers to facilitate enlarging the opening of the trapezoidal gap. However, if the etched portion of the dielectric layer 400 is too thick, it may result in an excessively large top opening size of the second gap 500, while the size of the subsequent gap cannot be effectively enlarged. Therefore, the thickness of the etched portion of the dielectric layer 400 can be reduced.

[0078] For example, the dielectric layer 400 includes a first dielectric layer 410 and a second dielectric layer 420 located on the first dielectric layer 410. In a direction perpendicular to the substrate 100, the first dielectric layer 410 has a first thickness h1, and the second dielectric layer 420 has a second thickness h2. The first thickness h1 is greater than the second thickness h2.

[0079] In some embodiments, the dielectric layer 400 may include silicon oxide, silicon nitride, silicon oxynitride, etc. For example, the dielectric layer 400 can be formed using undoped silicate glass (USG), spin-on glass (SOG), phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate-phosphosilicate glass (BPSG), flowable oxide (FOX), tetraethylorthosilicate (TEOS), plasma-enhanced TEOS (PE-TEOS), Tonen silazane (TOSZ), high-density plasma chemical vapor deposition (HDP-CVD) oxides, etc. These can be used individually or in combination. Furthermore, the dielectric layer 400 can be formed using spin coating processes, chemical vapor deposition (CVD) processes, plasma-enhanced chemical vapor deposition (PECVD) processes, high-density plasma chemical vapor deposition (HDP-CVD) processes, etc.

[0080] In some embodiments, the material of the contact structure 600 may include tungsten, silicon nitride, silicon oxynitride, etc. For example, the barrier layer may be formed using undoped silicate glass (USG), spin-on glass (SOG), phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate-phosphosilicate glass (BPSG), flowable oxide (FOX), tetraethylorthosilicate (TEOS), plasma-enhanced TEOS (PE-TEOS), Tonen silazane (TOSZ), high-density plasma chemical vapor deposition (HDP-CVD) oxides, etc. These may be used individually or in combination.

[0081] like Figure 9 As shown in the embodiments of this application, a semiconductor structure is also provided, including:

[0082] A substrate 700, on which an isolation region 710 and an active region 720 are formed;

[0083] A substrate 100 is formed on the substrate 700 and adjacent to the active region 720;

[0084] A dielectric layer 400 is located on the substrate 100, and the dielectric layer 400 has a second gap 500, which has different dimensions in a direction parallel to the substrate 100.

[0085] Contact structure 600, the contact structure 600 filling the second gap 500.

[0086] The contact structure 600 provided in this application embodiment can first deposit a sacrificial layer 200 on a substrate 100, then form a first gap 300 and a dielectric layer 400 filling the first gap 300 in the sacrificial layer 200, and then form a second gap 500 for filling the contact structure 600 after removing the sacrificial layer 200. In this method, the second gap 500 is less likely to be under-etched, which helps to solve the problem of open circuit caused by insufficient etching in the contact structure 600 at high aspect ratios.

[0087] In some embodiments, the substrate may be a semiconductor substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a single-crystal metal oxide substrate, etc. Multiple deep trenches may be formed on the surface of the substrate, and isolation materials are filled within these trenches to form isolation regions. These isolation regions isolate several active regions from the substrate. The isolation regions may isolate several active regions arranged in an array or other distribution types. The active regions can be formed by implanting impurities into the substrate; for example, active regions can be formed using an ion implantation process. It should be noted that those skilled in the art will understand that the substrate also includes other memory structures besides the isolation regions and active regions for the normal operation of the memory.

[0088] In some embodiments, the substrate 100 includes a metal wire layer.

[0089] In some embodiments, to make the formed contact structure 600 a high aspect ratio structure, the contact structure 600 has a first height H in the direction perpendicular to the substrate 100 and a maximum dimension D in the direction parallel to the substrate 100, wherein the first height H is not less than one-tenth of the maximum dimension D.

[0090] In some embodiments, in a direction parallel to the substrate 100, the contact structure 600 has a first maximum size d1 in the second gap 500 in the first dielectric layer 410. In this embodiment, the first maximum size d1 is equal to the maximum size D of the contact structure 600. The contact structure 600 has a second maximum size d2 in the second gap 500 in the second dielectric layer 420. The second maximum size d2 is not less than the first maximum size d1.

[0091] For example, the first maximum size d1 can be the size of the end of the contact structure 600 adjacent to the substrate 100, and the second maximum size d2 can be the size of the end of the contact structure 600 in the first dielectric layer 410 away from the substrate 100. The contact structure 600 formed in this way has a large contact area and therefore a small contact resistance.

[0092] To form the contact structure 600 with the first maximum size d1 and the second maximum size d2 at its two ends, a matching second gap 500 can be formed first. For example, to form the matching second gap 500, a trapezoidal gap can be formed in the dielectric layer first, and then the opening of the trapezoidal gap can be enlarged by etching to form the required second gap 500.

[0093] In some embodiments, the dielectric layer 400 can be designed in layers to facilitate enlarging the opening of the trapezoidal gap. However, if the etched portion of the dielectric layer 400 is too thick, it may result in an excessively large top opening size of the second gap 500, while the size of the subsequent gap cannot be effectively enlarged. Therefore, the thickness of the etched portion of the dielectric layer 400 can be reduced.

[0094] For example, the dielectric layer 400 includes a first dielectric layer 410 and a second dielectric layer 420 located on the first dielectric layer 410. In a direction perpendicular to the substrate 100, the first dielectric layer 410 has a first thickness h1, and the second dielectric layer 420 has a second thickness h2. The first thickness h1 is greater than the second thickness h2.

[0095] In some embodiments, the dielectric layer 400 may include silicon oxide, silicon nitride, silicon oxynitride, etc. For example, the dielectric layer 400 can be formed using undoped silicate glass (USG), spin-on glass (SOG), phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate-phosphosilicate glass (BPSG), flowable oxide (FOX), tetraethylorthosilicate (TEOS), plasma-enhanced TEOS (PE-TEOS), Tonen silazane (TOSZ), high-density plasma chemical vapor deposition (HDP-CVD) oxides, etc. These can be used individually or in combination. Furthermore, the dielectric layer 400 can be formed using spin coating processes, chemical vapor deposition (CVD) processes, plasma-enhanced chemical vapor deposition (PECVD) processes, high-density plasma chemical vapor deposition (HDP-CVD) processes, etc.

[0096] In some embodiments, the material of the contact structure 600 may include tungsten, silicon nitride, silicon oxynitride, etc. For example, the barrier layer may be formed using undoped silicate glass (USG), spin-on glass (SOG), phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate-phosphosilicate glass (BPSG), flowable oxide (FOX), tetraethylorthosilicate (TEOS), plasma-enhanced TEOS (PE-TEOS), Tonen silazane (TOSZ), high-density plasma chemical vapor deposition (HDP-CVD) oxides, etc. These may be used individually or in combination.

[0097] This application also provides a memory, including the contact structure or semiconductor structure described in the foregoing embodiments.

[0098] The memory may include random access memory (RAM) or read-only memory. Optionally, the memory may include non-transitory computer-readable storage medium. The memory can be used to store instructions, programs, code, code sets, or instruction sets.

[0099] It should be understood that the specific embodiments described above are merely illustrative of the principles of this application and do not constitute a limitation thereof. Therefore, any modifications, equivalent substitutions, or improvements made without departing from the spirit and scope of this application should be included within the protection scope of this application. Furthermore, the appended claims are intended to cover all variations and modifications falling within the scope and boundaries of the appended claims, or equivalent forms of such scope and boundaries.

Claims

1. A method for forming a contact structure, comprising: Provide a substrate, on which a sacrificial layer is formed; The sacrificial layer is patterned to form a first gap that exposes the substrate. A dielectric layer is deposited in the first gap, the dielectric layer comprising a first dielectric layer and a second dielectric layer located on the first dielectric layer, wherein the first dielectric layer has a first thickness and the second dielectric layer has a second thickness in a direction perpendicular to the substrate, and the first thickness is greater than the second thickness; Remove the sacrificial layer to form a second gap between the dielectric layers; At least a portion of the second dielectric layer surrounding the second gap is etched to enlarge the opening size of the second gap. In a direction parallel to the substrate, the contact structure has a first maximum size in the second gap within the first dielectric layer, and the contact structure has a second maximum size in the second gap within the second dielectric layer, wherein the second maximum size is not greater than the first maximum size. The second gap, after being etched, is filled with conductive material to form a contact structure.

2. The method as described in claim 1, wherein, The substrate is a conductive substrate.

3. The method as described in claim 1, wherein, A plurality of the first gaps are formed on the substrate, and a sacrificial layer is provided between each of the first gaps. In a direction parallel to the substrate, the sacrificial layer between each of the first gaps has a maximum size, which is less than or equal to one-tenth of the opening size of the first gap.

4. The method of claim 3, wherein, In a direction perpendicular to the substrate, the sacrificial layer has a first height, which is not less than one-tenth of the maximum dimension of the sacrificial layer.

5. The method of claim 3, wherein, In a direction parallel to the substrate, adjacent sacrificial layers are spaced apart, and the spacing gradually decreases in a direction perpendicular to the substrate.

6. The method of claim 1, wherein, A wet cleaning process is used to remove the sacrificial layer and / or at least a portion of the second dielectric layer surrounding the second gap.

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