Method for reducing damage to work function layer of HKMG device

Abstract

The application provides a method for reducing damage to a work function layer of an HKMG device, which comprises the following steps: step 1) providing a semiconductor structure comprising a substrate and a plurality of gate structures of semiconductor devices formed on the substrate, wherein each gate structure comprises a stack of a gate dielectric layer, a work function layer and a metal gate, the work function layer is formed between the gate dielectric layer and the metal gate, and the work function layer is in a U shape on the sidewall and the bottom of the metal gate; step 2) selectively growing a metal barrier layer on the surface of the work function layer and the metal gate; step 3) forming a dielectric layer on the surface of the structure formed in step 2); and step 4) patterning and etching the dielectric layer to form a contact hole above the metal gate. The application solves the problem that the work function layer is damaged in the process of forming a contact hole in the existing HKMG device, thereby causing threshold voltage drift.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for reducing work function layer damage in HKMG devices. Background Technology

[0002] In the current semiconductor industry, polysilicon is widely used as the standard gate filler material in semiconductor devices such as MOS transistors. However, as the size of MOS transistors decreases, the performance of traditional polysilicon gates deteriorates due to the boron penetration effect. Furthermore, unavoidable depletion effects lead to an increase in the equivalent gate dielectric layer thickness and a decrease in gate capacitance, ultimately resulting in device performance degradation. Therefore, the semiconductor industry has attempted to replace traditional polysilicon gates with new gate filler materials (such as work function (WF) metal layers) as control electrodes for high-dielectric-constant (HK) gate dielectric layers, i.e., metal gates (MG). HKMG has a high-dielectric-constant (HK) gate dielectric layer and a metal gate (MG), hence it is commonly abbreviated as HKMG in this field.

[0003] However, during the process of forming contact holes for semiconductor devices through photolithography, etching, and cleaning, the metal gate and work function metal layer are easily damaged, which can lead to device threshold voltage drift. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for reducing the damage to the work function layer of an HKMG device, which solves the problem of threshold voltage drift caused by damage to the work function layer during the formation of contact holes in existing HKMG devices.

[0005] To achieve the above and other related objectives, the present invention provides a method for reducing work function layer damage in HKMG devices, the method comprising:

[0006] Step 1) Provide a semiconductor structure, including a substrate and a gate structure of a plurality of semiconductor devices formed on the substrate. The gate structure includes a stacked structure of a gate dielectric layer, a work function layer and a metal gate, wherein the work function layer is formed between the gate dielectric layer and the metal gate and is U-shaped and located on the sidewall and bottom of the metal gate.

[0007] Step 2) Selectively grow a metal barrier layer on the surface of the work function layer and the metal gate;

[0008] Step 3) Form a dielectric layer on the surface of the structure formed in step 2);

[0009] Step 4) Pattern the dielectric layer to form contact holes above the metal gate;

[0010] The semiconductor device comprises a PMOS tube and an NMOS tube, and the PMOS tube and the NMOS tube have the same gate structure.

[0011] Optionally, the metal barrier layer is made of at least one of Co, W, Pb or TiSi.

[0012] Optionally, the thickness of the metal barrier layer is 20-50 angstroms.

[0013] Optionally, the metal barrier layer is formed by atomic layer deposition or electroplating when step 2) is performed.

[0014] Optionally, the work function layer of the NMOS tube is made of TiAl, and the work function layer of the PMOS tube is made of TiAlC.

[0015] Optionally, the gate dielectric layer is a high-K dielectric layer.

[0016] Optionally, the metal gate is made of metal Al or metal W.

[0017] Optionally, the semiconductor structure further comprises a sidewall, a stop layer and an interlayer dielectric layer, the sidewall is formed on the sidewall of the gate structure, and the stop layer is formed between the sidewall and the interlayer dielectric layer.

[0018] Optionally, the substrate has the source region and the drain region of the NMOS tube and the source region and the drain region of the PMOS tube formed therein.

[0019] Optionally, the contact hole is formed by etching the dielectric layer above the source region and the drain region of the NMOS tube and above the source region and the drain region of the PMOS tube when step 4) is performed.

[0020] Optionally, the gate structure further comprises a gate barrier layer, and the gate barrier layer is formed between the gate dielectric layer and the work function layer.

[0021] Optionally, after step 4), the method further comprises a step of wet cleaning the structure formed in step 4).

[0022] As described above, the method for reducing damage to the work function layer of the HKMG device can form a metal protection layer on the surface of the metal gate and the work function layer to protect the metal gate and the work function layer, so as to prevent the boundary effect of subsequent processes from damaging the metal gate and the work function layer and avoid causing the threshold voltage of the device to drift. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The flow chart of the method for reducing damage to the work function layer of the HKMG device is shown.

[0024] Figure 2 A cross-sectional structure of a semiconductor structure according to the present application is shown.

[0025] Figure 3 A cross-sectional structure after forming a metal barrier layer on the surface of a semiconductor structure according to the present application is shown.

[0026] Figure 4 A cross-sectional structure after forming a dielectric layer according to the present application is shown.

[0027] Figure 5 A cross-sectional structure after forming a contact hole according to the present application is shown.

[0028] BRIEF DESCRIPTION OF DRAWINGS

[0029] 10: semiconductor structure; 11: substrate; 12: gate structure; 121: gate dielectric layer; 122: work function layer; 123: metal gate; 124: gate barrier layer; 13: sidewall; 14: stop layer; 15: interlayer dielectric layer; 16: shallow trench isolation structure; 20: metal barrier layer; 30: dielectric layer; 40: contact hole; 51: first source region; 52: first drain region; 61: second source region; 62: second drain region DETAILED DESCRIPTION

[0030] The present application is herein described, by way of example only, with reference to the accompanying drawings, wherein:

[0031] Reference will now be made to the drawings, wherein: Figures 1 to 5 It is to be understood that the drawings are to be used only for illustrating the specific embodiments and should not be used to limit the present application. The specific embodiments shown are merely exemplary in nature and are not to be considered as limiting the scope of the application. In the drawings:

[0032] As shown in Figure 1 The present embodiment provides a method for reducing damage to a work function layer of an HKMG device, the method comprising:

[0033] Step 1) Provide a semiconductor structure 10, including a substrate 11 and a gate structure 12 of a plurality of semiconductor devices formed on the substrate 11. The gate structure 12 includes a stacked structure of a gate dielectric layer 121, a work function layer 122 and a metal gate 123, wherein the work function layer 122 is formed between the gate dielectric layer 121 and the metal gate 123, and is U-shaped and located on the sidewall and bottom of the metal gate 123.

[0034] Step 2) Selectively grow a metal barrier layer 20 on the surface of the work function layer 122 and the metal gate 123;

[0035] Step 3) Form a dielectric layer 30 on the surface of the structure formed in step 2);

[0036] Step 4) Pattern etching the dielectric layer 30 to form a contact hole 40 above the metal gate 123;

[0037] The semiconductor device includes a PMOS transistor and an NMOS transistor, and the PMOS transistor and the NMOS transistor have the same gate structure.

[0038] The method for reducing the work function layer loss of HKMG devices provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0039] like Figure 2 As shown, in step 1), a semiconductor structure 10 is provided, including a substrate 11 and a gate structure 12 of a plurality of semiconductor devices formed on the substrate 11. The gate structure 12 includes a stacked structure of a gate dielectric layer 121, a work function layer 122 and a metal gate 123, wherein the work function layer 122 is formed between the gate dielectric layer and the metal gate 123, and is U-shaped and located on the sidewall and bottom of the metal gate 123.

[0040] In this embodiment, the semiconductor structure 10 is divided into a first device region A, a second device region B, and a dummy region C, with the dummy region B located between the first device region A and the second device region B. The first device region A is used to form an NMOS transistor, the second device region B is used to form a PMOS transistor, and the dummy region C is used to form either an NMOS transistor or a PMOS transistor, the specific type to be formed depending on the density of NMOS and PMOS transistors.

[0041] Specifically, the semiconductor structure 10 further includes a sidewall 13, a stop layer 14, and an interlayer dielectric layer 15. The sidewall 13 is formed on the sidewall of the gate structure 12, and the stop layer 13 is formed between the sidewall 14 and the interlayer dielectric layer 15.

[0042] Specifically, the substrate 11 is formed with the source region and the drain region of the NMOS transistor and the source region and the drain region of the PMOS transistor.

[0043] In this embodiment, the source region and the drain region of the NMOS transistor are respectively a first source region 51 and a first drain region 52, and the source region and the drain region of the PMOS transistor are respectively a second source region 61 and a second drain region 62.

[0044] Specifically, the gate dielectric layer 121 is a high-K dielectric layer.

[0045] In this embodiment, the material of the gate dielectric layer 121 includes hafnium dioxide, silicon nitride, aluminum trioxide, tantalum pentoxide, yttrium oxide, hafnium silicate oxide compound, lanthanum oxide or zirconium dioxide, etc.

[0046] Specifically, the material of the work function layer 122 of the NMOS transistor is TiAl, and the material of the work function layer 122 of the PMOS transistor is TiAlC.

[0047] Specifically, the material of the metal gate 123 includes metal Al or metal W.

[0048] Specifically, the gate structure 12 further includes a gate blocking layer 124, which is formed between the gate dielectric layer 121 and the work function layer 122.

[0049] In this embodiment, the material of the gate blocking layer 124 includes titanium nitride or tantalum nitride.

[0050] Further, in this embodiment, a shallow trench isolation structure 16 is also formed in the substrate 11.

[0051] As shown in FIG. 2, in step 2), a metal blocking layer 20 is selectively grown on the surface of the work function layer 122 and the metal gate 123. Figure 3

[0052] In this embodiment, the introduction of the metal blocking layer 20 can prevent the work function layer 122 and the metal gate 123 from being damaged due to etching and cleaning processes in the process of forming the contact hole 40.

[0053] Specifically, when step 2) is performed, the atomic layer deposition process or the electroplating process is used to form the metal blocking layer 20.

[0054] Specifically, the material of the metal blocking layer 20 includes at least one of Co, W, Pb or TiSi.

[0055] Specifically, the thickness of the metal blocking layer 20 includes 20 angstroms to 50 angstroms.

[0056] As shown in FIG. 3, in step 3), a contact hole 40 is formed in the metal blocking layer 20, the work function layer 122, the gate dielectric layer 121, the gate blocking layer 124, the metal gate 123, the shallow trench isolation structure 16 and the substrate 11. Figure 4 ​As shown, in step 3), a dielectric layer 30 is formed on the surface of the structure formed in step 2).

[0057] In this embodiment, a dielectric layer 30 is formed on the surface of the structure formed in step 2) by a deposition process. The dielectric layer 30 is made of silicon oxide.

[0058] like Figure 5 As shown, in step 4), the dielectric layer 30 is patterned and etched to form a contact hole 40 above the metal gate 123.

[0059] Specifically, during step 4), the contact hole is formed by etching the dielectric layer 30 above the source and drain regions of the NMOS transistor and the source and drain regions of the PMOS transistor.

[0060] In this embodiment, the contact hole 40 is formed above the metal gate 123, above the first source region 51 and the first drain region 52 of the NMOS transistor, and above the second source region 61 and the second drain region 62 of the PMOS transistor by etching the dielectric layer 30.

[0061] Specifically, after step 4), the method further includes a step of wet cleaning the structure formed in step 4).

[0062] In this embodiment, ultra-diluted hydrofluoric acid (UDHF) is used for wet cleaning of the structure formed in step 4), with a volume ratio of hydrofluoric acid to water of 1:2000.

[0063] In summary, the method for reducing work function layer damage in HKMG devices according to the present invention protects the metal gate and work function layer by forming a metal protective layer on the surface of the metal gate and work function layer, thereby preventing boundary effects from subsequent processes from damaging the metal gate and work function layer and avoiding device threshold voltage drift. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0064] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of reducing damage to a work function layer of an HKMG device, comprising: The method comprises: Step 1) providing a semiconductor structure comprising a substrate and a plurality of gate structures of semiconductor devices formed on the substrate, wherein each of the gate structures comprises a stack of a gate dielectric layer, a work function layer and a metal gate, and the work function layer is formed between the gate dielectric layer and the metal gate and has a U shape on the sidewall and bottom of the metal gate; Step 2) selectively growing a metal barrier layer on the surface of the work function layer and the metal gate; Step 3) forming a dielectric layer on the surface of the structure formed in step 2); Step 4) patterning and etching the dielectric layer to form a contact hole above the metal gate, and the metal barrier layer prevents the work function layer and the metal gate from being damaged during the process of forming the contact hole; The semiconductor devices comprise PMOS and NMOS, and the PMOS and the NMOS have the same gate structure.

2. The method of claim 1, wherein the method further comprises: The material of the metal barrier layer comprises at least one of Co, W, Pb or TiSi.

3. The method of claim 1, wherein the method further comprises: The thickness of the metal barrier layer is 20-50 angstroms.

4. The method of claims 1-3, wherein the method is performed in a HKMG device. In step 2), the metal barrier layer is formed by atomic layer deposition or electroplating.

5. The method of claim 1, wherein the method further comprises: The material of the work function layer of the NMOS is TiAl, and the material of the work function layer of the PMOS is TiAlC.

6. The method of claim 1, wherein the method further comprises: The gate dielectric layer is a high-K dielectric layer.

7. The method of claim 1, wherein the method further comprises: The material of the metal gate comprises metal Al or metal W.

8. The method of claim 1, wherein the method further comprises: The semiconductor structure further comprises a sidewall formed on the sidewall of the gate structure, a stop layer and an interlayer dielectric layer.

9. The method of claim 1, wherein the method further comprises: The substrate is provided with source and drain regions of the NMOS and source and drain regions of the PMOS.

10. The method of claim 9, wherein the method further comprises: In step 4), the contact hole is formed by etching the dielectric layer above the source and drain regions of the NMOS and above the source and drain regions of the PMOS.

11. The method of claim 1, wherein the method further comprises: The gate structure further comprises a gate barrier layer formed between the gate dielectric layer and the work function layer.

12. The method of claim 1, wherein the method further comprises: After step 4), the method further comprises a step of wet cleaning the structure formed in step 4).

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