Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor packaging device and a manufacturing method thereof. The semiconductor packaging device comprises a first substrate, a second substrate arranged on the first substrate and having an opening, a molding material arranged on the second substrate and between the second substrate and the first substrate, a first chip arranged on the molding material, and a first connecting line covered by the molding material and passing through the opening of the second substrate, a first end of the first connecting line being electrically connected with the first chip. The semiconductor packaging device and the manufacturing method thereof can reduce the area occupied by the electrically connected part in the packaging structure on the second substrate, so that the opening on the second substrate has a large enough size to ensure the smooth flow of the molding material, which is beneficial to ensure the molding effect and improve the product yield.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and more specifically to semiconductor packaging apparatus and manufacturing methods thereof. Background Technology

[0002] In three-dimensional stacked structures, through-holes are typically provided on the upper substrate to allow mold flow to pass through in order to complete the molding process. However, when the component density on the upper substrate is high, the size of the through-holes will be limited, causing the mold flow to be unable to pass through smoothly, which will affect the molding effect (e.g., create voids).

[0003] Therefore, it is necessary to propose a new technical solution to solve at least one of the above-mentioned technical problems. Summary of the Invention

[0004] This disclosure provides a semiconductor packaging device and a method for manufacturing the same.

[0005] In a first aspect, this disclosure provides a semiconductor packaging apparatus, comprising:

[0006] First substrate;

[0007] A second substrate is disposed on the first substrate and has an opening;

[0008] A molding material is disposed on the second substrate and between the second substrate and the first substrate;

[0009] The first chip is set on the molding material;

[0010] A first connecting line is covered by the molding material and passes through the opening in the second substrate, and a first end of the first connecting line is electrically connected to the first chip.

[0011] In some alternative embodiments, a first end of the first connecting line extends to the surface of the molding material and protrudes from the molding material.

[0012] In some alternative embodiments, the surface of the molding material is provided with a conductive pad, which is electrically connected to a first end of the first connecting line and the first chip, respectively.

[0013] In some alternative implementations, the second end of the first connecting line is electrically connected to the first substrate.

[0014] In some alternative embodiments, a second chip is disposed on the first substrate, and a second end of the first connecting line is electrically connected to the second chip.

[0015] In some alternative implementations, the width of the longitudinal cross-section of the electrical connection region of the second chip is smaller than the width of the longitudinal cross-section of the opening.

[0016] In some alternative embodiments, the second chip is attached to the surface of the first substrate.

[0017] In some optional embodiments, the semiconductor packaging device further includes:

[0018] The second connecting line is covered by the molding material and passes through the opening of the second substrate. The two ends of the second connecting line are electrically connected to the second substrate and the first substrate, respectively.

[0019] In some optional embodiments, the semiconductor packaging device further includes:

[0020] The third connecting line is covered by the molding material and its two ends are electrically connected to the first chip and the second substrate, respectively.

[0021] In some alternative embodiments, the second substrate is disposed on the first substrate by solder.

[0022] In some alternative implementations, the number of the first connecting lines is at least two.

[0023] In some alternative embodiments, an underfill material is provided between the first chip and the molding material.

[0024] Secondly, this disclosure also provides a method for manufacturing a semiconductor packaging device, comprising:

[0025] A second substrate is disposed on a first substrate, wherein the second substrate has an opening;

[0026] A first connecting line is provided to pass through the opening;

[0027] Molding is performed over the second substrate to form a molding material, wherein the molding material is located on the second substrate and between the second substrate and the first substrate and covers the first connecting line;

[0028] The thickness of the molding material is reduced by a thinning process to expose the first end of the first connecting line;

[0029] A first chip is disposed on the molding material to obtain a semiconductor packaging device, wherein the first chip is electrically connected to a first end of the first connecting line.

[0030] In some alternative embodiments, a first chip is disposed on the molding material to obtain a semiconductor package device, including:

[0031] A conductive pad is formed on the surface of the molding material, wherein the conductive pad is electrically connected to a first end of the first connecting line;

[0032] The first chip is placed on the conductive pad so that the first chip is electrically connected to the first end of the first connecting line through the conductive pad.

[0033] In the semiconductor packaging apparatus and manufacturing method disclosed herein, by realizing the electrical connection between the first chip and other electronic components through the first connection line, the area occupied by the electrical connection portion in the packaging structure on the second substrate can be reduced. This allows the openings on the second substrate to have a sufficiently large size to ensure smooth flow of the molding fluid, which is beneficial for ensuring the molding effect and improving product yield. Furthermore, by placing the first chip on the molding material in this disclosure, sufficient area can be ensured for placing the first chip, avoiding insufficient placement area for the first chip due to increasing the opening size. Attached Figure Description

[0034] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0035] Figure 1 This is a schematic diagram of a semiconductor packaging device in the prior art;

[0036] Figures 2-5 These are first to fourth schematic diagrams of a semiconductor packaging apparatus according to embodiments of the present invention;

[0037] Figures 6-11 This is a schematic diagram of a method for manufacturing a semiconductor packaging device according to an embodiment of the present invention.

[0038] Symbol explanation:

[0039] 11. Lower substrate; 12. Upper substrate; 13. Upper chip; 14. Through hole; 15. Solder; 16. Molding material; 100. First substrate; 200. Second substrate; 210. Opening; 310. First chip; 320. Second chip; 400. Molding material; 410. Conductive pad; 500. Electrical connection wire; 510. First connection wire; 520. Second connection wire; 530. Third connection wire; 600. Solder; 700. Bottom filler; 910. Wire bonding device. Detailed Implementation

[0040] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0041] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0042] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0043] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0044] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used in this disclosure to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used in this disclosure may be interpreted accordingly.

[0045] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0046] Figure 1 This is a schematic diagram of a semiconductor packaging device in the prior art. For example... Figure 1As shown, the semiconductor packaging device includes a lower substrate 11, an upper substrate 12, and an upper chip 13. The upper substrate 12 is disposed on the upper surface of the lower substrate 11 by solder 15. Similarly, the lower chip is also disposed on the upper surface of the upper substrate 12 by solder. The upper substrate 12 is also provided with a through-hole 14. The through-hole 14 allows mold flow to pass through, so as to form a molding material 16 between the upper substrate 12 and the lower substrate 11. When a large number of electronic components need to be disposed on the surface of the upper substrate 12, the diameter 'a' of the through-hole 14 will be limited, causing the mold flow to be unable to pass through smoothly, further affecting the molding effect, such as forming a gap between the upper substrate 12 and the lower substrate 11 (e.g., Figure 1 (As shown by the dashed line).

[0047] This disclosure provides a semiconductor packaging apparatus. Figures 2-5 These are first to fourth schematic diagrams of a semiconductor packaging apparatus according to embodiments of the present invention.

[0048] Figure 2 A longitudinal cross-section of the semiconductor packaging device is shown. (See figure) Figure 2 As shown, the semiconductor packaging device includes a first substrate 100, a second substrate 200, a molding compound 400, a first chip 310, and a first interconnect 510. The second substrate 200 is disposed on the first substrate 100 and has an opening 210. The molding compound 400 is disposed on the second substrate 200 and between the second substrate 200 and the first substrate 100. The first chip 310 is disposed on the molding compound 400. The first interconnect 510 is covered by the molding compound 400 and passes through the opening 210 of the second substrate 200. The first end of the first interconnect 510 (i.e., Figure 2 The upper end of the first connecting line 510 is electrically connected to the first chip 310. The second end of the first connecting line 510 (i.e., the upper end of the first connecting line 510) is electrically connected to the first chip 310. Figure 2 The lower end of the middle section is electrically connected to the first substrate 100.

[0049] like Figure 2 As shown, the first end of the first connecting line 510 extends to the surface of the molding material 400 and protrudes from the molding material 400. A conductive pad 410 is provided on the surface of the molding material 400, and the conductive pad 410 is electrically connected to the first end of the first connecting line 510 and the first chip 310, respectively.

[0050] In this embodiment, the second substrate 200 is disposed on the first substrate 100 via an electrical connection material. Similarly, the first chip 310 is also disposed on the molding material 400 via an electrical connection material. In this embodiment, the electrical connection material is solder 600. In other embodiments, the electrical connection material may be other conductive materials, such as metals like copper, silver, or gold. The second substrate 200 and the first substrate 100 may be connected by various methods such as soldering or direct metal bonding.

[0051] In this embodiment, by realizing the electrical connection between the first chip 310 and other electronic components through the first connection line 510, the area occupied by the electrical connection part in the package structure on the second substrate 200 can be reduced, so that the opening 210 on the second substrate 200 has a sufficiently large size to ensure that the mold flow passes through smoothly, which is beneficial to ensuring the molding effect and improving the product yield.

[0052] Furthermore, in this embodiment, the first chip 310 is placed on the molding material 400, which ensures that there is enough area to place the first chip 310 and avoids insufficient placement area of ​​the first chip 310 due to increasing the size of the opening 210.

[0053] like Figure 2 As shown, the semiconductor packaging device further includes a second connection line 520. The second connection line 520 is covered by a molding material 400 and passes through an opening 210 in the second substrate 200. The two ends of the second connection line 520 are electrically connected to the second substrate 200 and the first substrate 100, respectively. The second connection line 520 can further reduce the area occupied by the electrical connection between the first substrate 100 and the second substrate 200 on the second substrate 200.

[0054] Figure 3 It shows Figure 2 A top view of a semiconductor packaging device, in which the first chip 310 has been removed. Figure 3 As shown, the second substrate 200 has a plurality of openings 210. Each opening 210 is provided with a plurality of second connecting lines 520. Each second connecting line 520 passes through the corresponding opening 210 and its two ends are electrically connected to the first substrate 100 and the second substrate 200, respectively.

[0055] like Figure 2 As shown, the semiconductor packaging device further includes a third connection line 530. The third connection line 530 is covered by a molding material 400 and its two ends are electrically connected to the first chip 310 and the second substrate 200, respectively. The third connection line 530 enables electrical connection between the first chip 310 and the second substrate 200. The third connection line 530 can further reduce the area occupied by the electrical connection between the first chip 310 and the second substrate 200 on the second substrate 200.

[0056] like Figure 2 As shown, there are multiple first connection lines 510, second connection lines 520 and third connection lines 530, in order to further reduce the area occupied by the electrical connection parts in the packaging structure on the second substrate 200.

[0057] like Figure 2As shown, a bottom filler 700 is provided between the first chip 310 and the molding material 400 to fill the gap between the first chip 310 and the molding material 400 and improve the structural strength.

[0058] Figure 4 It shows Figure 2 A variation of a semiconductor packaging device. For example... Figure 4 As shown, a second chip 320 is disposed on the first substrate 100. The second chip 320 is attached to the surface of the first substrate 100. A first end of a first connecting line 510 is electrically connected to the first chip 310, and a second end of the first connecting line 510 is electrically connected to the second chip 320. Furthermore, a first end of the second connecting line 520 is electrically connected to the second substrate 200, and a second end of the second connecting line 520 is electrically connected to the second chip 320. Figure 4 The semiconductor packaging device in the middle can achieve the same as Figure 2 The similar technical effects of semiconductor packaging devices will not be elaborated here.

[0059] like Figure 4 As shown, the width of the longitudinal cross-section of the electrical connection area of ​​the second chip 320 (i.e., the area for bonding with the first electrical connection line 500 or the second electrical connection line 500) is smaller than the width of the longitudinal cross-section of the opening 210. This facilitates the upward exposure of the electrical connection area of ​​the second chip 320 through the opening 210, enabling the wire bonding operation during the manufacturing process to proceed smoothly.

[0060] Figure 5 It shows Figure 2 Another variation of semiconductor packaging devices. For example... Figure 5 As shown, the semiconductor packaging device includes two second substrates 200. The two second substrates 200 are stacked. The lowermost second substrate 200 is disposed on the first substrate 100. The uppermost second substrate 200 has a first chip 310 disposed on it. Each second substrate 200 has a corresponding opening 210 and a first connection line 510. Each first connection line 510 passes through the corresponding opening 210 and realizes the electrical connection between the electronic components on both sides of the opening 210. Figure 5 This approach is conducive to achieving a wider variety of functional requirements.

[0061] Figure 5 The semiconductor packaging device includes two second substrates 200. In other embodiments, the semiconductor packaging device may include other numbers of second substrates 200, such as three or five, etc., which are not limited in this disclosure.

[0062] In this embodiment, the diameters of the first electrical connection line 510, the second electrical connection line 520, and the third electrical connection line 530 can be greater than 10 micrometers and less than 50 micrometers. The thicknesses of the first substrate 100 and the second substrate 200 can be greater than 20 micrometers and less than 100 micrometers. The spacing between the first substrate 100 and the second substrate 200 can be greater than 50 micrometers and less than 200 micrometers. The thickness of the molding material 400 above the second substrate 200 can be greater than 10 micrometers and less than 100 micrometers. The diameter of the openings 210 on the second substrate 200 can range from several hundred micrometers to several millimeters. The density of electrical connections on the lower surface of the first substrate 100 can be from several hundred to several thousand per square millimeter.

[0063] In this embodiment, the materials of the first electrical connection line 510, the second electrical connection line 520 and the third electrical connection line 530 can be metallic materials such as copper, silver, gold, aluminum, nickel, titanium, lead, platinum, and solder, or non-metallic materials such as graphene.

[0064] In this embodiment, the dielectric materials such as the underfill, adhesive, and substrate in the semiconductor packaging device can be organic materials such as polyimide (PI), epoxy resin, acrylic fiber, Ajinomoto build-up film (ABF), or molding compound, or inorganic materials such as oxides (e.g., silicon oxide, silicon nitride, or tantalum oxide), glass, silicon, or ceramic.

[0065] In this embodiment, the dielectric materials such as the underfill, adhesive, and substrate in the semiconductor packaging device can be formed using organic photosensitive materials, non-photosensitive liquids, or dry film materials, and can be adhered by means of deposition, lamination, printing, potting, or impregnation.

[0066] This disclosure also provides a method for manufacturing a semiconductor packaging device. Figures 6-11 This is a schematic diagram of a method for manufacturing a semiconductor packaging apparatus according to an embodiment of the present invention. Figures 6-11 As shown, the method includes the following steps:

[0067] First step, such as Figure 6 As shown, a second substrate 200 is disposed on a first substrate 100 using solder 600. The second substrate 200 has an opening 210.

[0068] The second step, as Figure 7 As shown, an electrical connection wire 500 is installed through the opening 210 using a wire punching device 910.

[0069] The third step, as Figure 8 As shown, molding is performed on the second substrate 200 to form a molding material 400, wherein the molding material 400 is located on the second substrate 200 and between the second substrate 200 and the first substrate 100 and covers the electrical connection line 500.

[0070] Step four, as Figure 9 As shown, the thickness of the molding material 400 is reduced by a thinning process (such as grinding or etching) so that the upper end of a portion of the electrical connection line 500 is exposed.

[0071] Fifth step, as Figure 10 As shown, a conductive pad 410 is formed on the surface of the molding material 400. The conductive pad 410 is electrically connected to the upper end of a portion of the electrical connection line 500.

[0072] Step 6, as follows Figure 11 As shown, a first chip 310 is disposed on a conductive pad 410 so that the first chip 310 is electrically connected to the first end of a first connecting line 510 through the conductive pad 410, thereby obtaining a semiconductor packaging device. Specifically, an electrical connecting line 500 whose two ends are electrically connected to the first chip 310 and the first substrate 100 respectively forms a first connecting line 510; an electrical connecting line 500 whose two ends are electrically connected to the first substrate 100 and the second substrate 200 respectively forms a second connecting line 520; and an electrical connecting line 500 whose two ends are electrically connected to the first chip 310 and the second substrate 200 respectively forms a third connecting line 530.

[0073] The manufacturing method of the semiconductor packaging device provided in this disclosure can achieve similar technical effects to the semiconductor packaging device described above, and will not be repeated here.

[0074] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed in this disclosure have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated in this disclosure, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor packaging device, comprising: First substrate; A second substrate is disposed on the first substrate and has an opening; A molding material is disposed on the second substrate and between the second substrate and the first substrate; The first chip is set on the molding material; A first connecting line is covered by the molding material and passes through the opening in the second substrate, and a first end of the first connecting line is electrically connected to the first chip.

2. The semiconductor packaging apparatus according to claim 1, wherein, The first end of the first connecting line extends to the surface of the molding material and is exposed from the molding material.

3. The semiconductor packaging apparatus according to claim 2, wherein, The surface of the molding material is provided with a conductive pad, which is electrically connected to the first end of the first connecting line and the first chip respectively.

4. The semiconductor packaging apparatus according to claim 1, wherein, The second end of the first connecting line is electrically connected to the first substrate.

5. The semiconductor packaging apparatus according to claim 1, wherein, A second chip is disposed on the first substrate, and the second end of the first connecting line is electrically connected to the second chip.

6. The semiconductor packaging apparatus according to claim 5, wherein, The second chip is attached to the surface of the first substrate.

7. The semiconductor packaging apparatus according to claim 1, wherein, The semiconductor packaging apparatus further includes: The second connecting line is covered by the molding material and passes through the opening of the second substrate. The two ends of the second connecting line are electrically connected to the second substrate and the first substrate, respectively.

8. The semiconductor packaging apparatus according to claim 1, wherein, The semiconductor packaging apparatus further includes: The third connecting line is covered by the molding material and its two ends are electrically connected to the first chip and the second substrate, respectively.

9. The semiconductor packaging apparatus according to claim 1, wherein, The second substrate is disposed on the first substrate by means of an electrical connection material.

10. The semiconductor packaging apparatus according to claim 1, wherein, The number of the first connecting lines is at least two.

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