Electrostatic discharge protection device and operating method thereof

Abstract

The present invention provides an electrostatic discharge protection device and an operating method thereof. The electrostatic discharge protection device includes: a substrate, a first well region disposed in the substrate and having a first conductivity type, a second well region disposed in the first well region and having a second conductivity type, a first doped region disposed in the second well region and having the first conductivity type, a second doped region disposed in the second well region and having the first conductivity type, a third doped region disposed in the second well region and having the second conductivity type, and a fourth doped region disposed in the substrate and having the first conductivity type. The first conductivity type is different from the second conductivity type. The second well region, the first well region, the substrate, and the fourth doped region constitute a silicon controlled rectifier (SCR). An electrostatic discharge current entering the first doped region flows through the SCR to the fourth doped region.

Description

Technical Field

[0001] The present disclosure relates to semiconductor integrated circuits and applications thereof, and more particularly to electrostatic discharge (ESD) protection devices and operating methods thereof. Background Art

[0002] Electrostatic discharge (ESD) is the transfer of charge between two objects with different electrical potentials. ESD can generate large currents within a short period of time (typically within a few nanoseconds). When high currents generated by ESD flow through semiconductor integrated circuits within a short period of time, they can cause serious damage. ESD is a major cause of IC failure and damage, making the development of effective ESD protection designs in ICs a critical issue in semiconductor manufacturing.

[0003] Stacking low-voltage transistors to create a high-voltage ESD protection device is a common ESD protection design. However, this stacking configuration has the disadvantage of large component size. In other words, in an integrated circuit, an ESD protection device with stacked low-voltage transistors requires a large layout area, increasing manufacturing costs.

[0004] Therefore, there is a need to provide an efficient ESD protection device that can save layout area and has enhanced ESD protection capability to prevent damage to integrated circuits.

[0005] Public content

[0006] The present disclosure relates to an electrostatic discharge protection device and an operating method thereof.

[0007] According to one embodiment of the present disclosure, an electrostatic discharge protection device is proposed. The electrostatic discharge protection device includes: a substrate, a first well region disposed in the substrate and having a first conductivity type, a second well region disposed in the first well region and having a second conductivity type, a first doped region disposed in the second well region and having the first conductivity type, a second doped region disposed in the second well region and having the first conductivity type, a third doped region disposed in the second well region and having the second conductivity type, and a fourth doped region disposed in the substrate and having the first conductivity type. The first conductivity type is different from the second conductivity type. The second well region, the first well region, the substrate, and the fourth doped region constitute a silicon controlled rectifier (SCR), and the electrostatic discharge current entering the first doped region flows to the fourth doped region through the SCR.

[0008] According to another embodiment of the present disclosure, an electrostatic discharge protection device is proposed. The electrostatic discharge protection device includes: a substrate, a first well region disposed in the substrate and having a first conductivity type, a second well region disposed in the first well region and having a second conductivity type, a third well region disposed in the first well region and having a second conductivity type, a first doped region disposed in the second well region and having a first conductivity type, a second doped region disposed in the second well region and having a first conductivity type, a third doped region disposed in the second well region and having a second conductivity type, and a fourth doped region disposed in the third well region and having a first conductivity type. The first conductivity type is different from the second conductivity type. The second well region, the first well region, the third well region, and the fourth doped region constitute a thyristor rectifier, and the electrostatic discharge current entering the first doped region flows to the fourth doped region through the thyristor rectifier.

[0009] According to another embodiment of the present disclosure, a method for operating an electrostatic discharge protection device is provided. The method for operating an electrostatic discharge protection device includes providing an electrostatic discharge protection device electrically connected to an internal circuit. The electrostatic discharge protection device includes: a substrate, a first well region disposed in the substrate and having a first conductivity type, a second well region disposed in the first well region and having a second conductivity type, a first doped region disposed in the second well region and having the first conductivity type, a second doped region disposed in the second well region and having the first conductivity type, a third doped region disposed in the second well region and having the second conductivity type, and a fourth doped region disposed in the substrate and having the first conductivity type. The first conductivity type is different from the second conductivity type. The second well region, the first well region, the substrate, and the fourth doped region constitute a silicon controlled rectifier. The method for operating the electrostatic discharge protection device also includes: when electrostatic discharge stress is applied to the internal circuit, an electrostatic discharge current flows through the silicon controlled rectifier to keep the electrostatic discharge current away from the internal circuit.

[0010] According to another embodiment of the present disclosure, a method for operating an electrostatic discharge protection device is proposed. The method for operating an electrostatic discharge protection device includes: providing an electrostatic discharge protection device electrically connected to an internal circuit. The electrostatic discharge protection device includes: a substrate, a first well region disposed in the substrate and having a first conductivity type, a second well region disposed in the first well region and having a second conductivity type, a third well region disposed in the first well region and having a second conductivity type, a first doped region disposed in the second well region and having a first conductivity type, a second doped region disposed in the second well region and having a first conductivity type, a third doped region disposed in the second well region and having a second conductivity type, and a fourth doped region disposed in the third well region and having a first conductivity type. The first conductivity type is different from the second conductivity type. The second well region, the first well region, the third well region, and the fourth doped region constitute a thyristor rectifier. The method for operating the electrostatic discharge protection device also includes: when electrostatic discharge stress is applied to the internal circuit, an electrostatic discharge current flows through the thyristor rectifier to keep the electrostatic discharge current away from the internal circuit.

[0011] In order to better understand the above and other aspects of the present invention, the following embodiments are specifically described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A cross-sectional view of an electrostatic discharge protection device according to a first embodiment of the present disclosure is shown;

[0013] Figure 2 FIG2 is a cross-sectional view of an electrostatic discharge protection device according to a second embodiment of the present disclosure;

[0014] Figure 3 FIG. 1 is a cross-sectional view of an electrostatic discharge protection device according to a third embodiment of the present disclosure;

[0015] Figure 4 FIG. 1 is a cross-sectional view of an electrostatic discharge protection device according to a fourth embodiment of the present disclosure;

[0016] Figure 5 A cross-sectional view of an electrostatic discharge protection device according to a fifth embodiment of the present disclosure is shown; and

[0017] Figure 6 FIG. 4 is a cross-sectional view of an electrostatic discharge protection device according to a sixth embodiment of the present disclosure.

[0018] Description of Reference Numerals

[0019] 10: Electrostatic discharge protection device

[0020] 101: Substrate

[0021] 102: First well region

[0022] 103: Second well region

[0023] 111: First doped region

[0024] 112: Second doping region

[0025] 113: Third doping region

[0026] 114: Fourth doping region

[0027] 115: Fifth doping region

[0028] 116: Sixth doping region

[0029] 121, 122: Contact pads

[0030] 123: Gate structure

[0031] 128, 129, 130: Metal wires

[0032] 331, 631: Resistor

[0033] 332, 632: nodes

[0034] 404: Third well region

[0035] D1, D2: distance DETAILED DESCRIPTION

[0036] The following is an illustration of some embodiments. It should be noted that the present disclosure does not show all possible embodiments, and other embodiments not proposed in the present disclosure may also be applicable. Furthermore, the dimensional ratios in the drawings are not drawn in proportion to the actual product. Therefore, the description and illustrations are only used to describe the embodiments, and are not used to limit the scope of protection of the present disclosure. In addition, the descriptions in the embodiments, such as detailed structures, process steps and material applications, etc., are only for illustrative purposes and are not intended to limit the scope of protection of the present disclosure. The details of the steps and structures of the embodiments can be changed and modified according to the needs of the actual application process without departing from the spirit and scope of the present disclosure. The following is an illustration of the same / similar elements represented by the same / similar symbols.

[0037] [First embodiment]

[0038] Please refer to Figure 1 , which illustrates a cross-sectional view of an ESD protection device 10 according to a first embodiment of the present disclosure. The ESD protection device 10 includes a substrate 101, a first well region 102, a second well region 103, a first doping region 111, a second doping region 112, and a third doping region 113.

[0039] In some embodiments of the present disclosure, the substrate 101 may be a doped or undoped semiconductor substrate, such as a silicon-containing substrate or a silicon-on-insulator (SOI) substrate. In a first embodiment, the substrate 101 is a P-type substrate.

[0040] A first well region 102 is disposed in a substrate 101. The first well region 102 has a first conductivity type. A second well region 103 is disposed in the first well region 102. The second well region 103 has a second conductivity type. In one embodiment, an ion implantation process may be used to form the first well region 102 and the second well region 103. The depth of the first well region 102 in the substrate 101 may be greater than the depth of the second well region 103 in the substrate 101, so the first well region 102 may also be understood as a deep well region, and the second well region 103 may also be understood as a shallow well region. The width of the first well region 102 may be greater than the width of the second well region 103. The first well region 102 may surround the second well region 103, that is, the second well region 103 is disposed within the outline of the first well region 102.

[0041] The first conductivity type is different from the second conductivity type. The first conductivity type may be opposite to the second conductivity type. In the first embodiment, the first conductivity type may be N-type and the second conductivity type may be P-type, but the present disclosure is not limited thereto.

[0042] The first doping region 111 is disposed in the second well region 103. The first doping region 111 has a first conductivity type and has a doping concentration (also represented by N+) substantially greater than that of the first well region 102 and / or the second well region 103. The second doping region 112 is disposed in the second well region 103. The second doping region 112 has a first conductivity type and has a doping concentration (also represented by N+) substantially greater than that of the first well region 102 and / or the second well region 103. The third doping region 113 is disposed in the second well region 103, and the third doping region 113 has a second conductivity type and has a doping concentration (also represented by P+) substantially greater than that of the first well region 102 and / or the second well region 103. Figure 1 As shown, the second doping region 112 is disposed between the first doping region 111 and the third doping region 113. The first doping region 111, the second doping region 112, and the third doping region 113 may be spaced apart from each other.

[0043] The ESD protection device 10 may further include a contact pad 121, a gate structure 123, and metal wires 128 and 129. The first doped region 111 may be electrically connected to the contact pad 121 via the metal wire 128. The gate structure 123 is disposed on the substrate 101 between the first doped region 111 and the second doped region 112. The second doped region 112 and the third doped region 113 may be electrically connected to the gate structure 123 via the metal wire 129. The second doped region 112 may be electrically connected to the third doped region 113 via the metal wire 129. In one embodiment, the first doped region 111, the second doped region 112, the gate structure 123, and the second well region 103 may form an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET). In this example, the first doped region 111 and the second doped region 112 may serve as source / drain side doping regions of the NMOSFET (also referred to as first source / drain side doping regions and second source / drain side doping regions, respectively).

[0044] The ESD protection device 10 may further include a fourth doped region 114, a fifth doped region 115, a contact pad 122, and a metal wire 130. The fourth doped region 114 and the fifth doped region 115 are both disposed in the substrate 101. The fourth doped region 114 has a first conductivity type and has a substantially higher doping concentration (also represented by N+) than the first well region 102 and / or the second well region 103. The fifth doped region 115 has a second conductivity type and has a substantially higher doping concentration (also represented by P+) than the first well region 102 and / or the second well region 103. The fourth doped region 114 and the fifth doped region 115 may be electrically connected to the contact pad 122 via the metal wire 130. In one embodiment, the fourth doped region 114 and the fifth doped region 115 are connected to ground (i.e., are connected to earth). The fifth doped region 115 may serve as a potential pickup. The fourth doped region 114 and the fifth doped region 115 may be spaced apart from each other. In one embodiment, there is a distance D1 between the second well region 103 and the fourth doping region 114. The distance D1 can be defined as the minimum distance between the second well region 103 and the fourth doping region 114. Figure 1 As shown, the distance D1 may represent the distance between the boundary of the second well region 103 and the boundary of the fourth doping region 114 in a direction parallel to the upper surface of the substrate 101. The distance D1 may be less than 20 micrometers (μm).

[0045] The ESD protection device 10 may further include a sixth doped region 116. The sixth doped region 116 is disposed in the first well region 102. The sixth doped region 116 has the first conductivity type and has a doping concentration (also represented by N+) substantially greater than that of the first well region 102 and / or the second well region 103. The doping concentrations of the first doped region 111, the second doped region 112, the third doped region 113, the fourth doped region 114, the fifth doped region 115, and the sixth doped region 116 may be similar or different.

[0046] In one embodiment, the ESD protection device 10 can be used to protect internal circuits in an integrated circuit from damage caused by electrostatic discharge (ESD) current. The internal circuit can be electrically connected to the contact pad 121 in the ESD protection device 10. When an ESD stress (ESD stress) is applied to the internal circuit, the ESD current is directed away from the internal circuit through the ESD protection device 10. The ESD current can flow from the contact pad 121 through the metal wire 128 into the ESD protection device 10. The ESD current then flows sequentially through the first doped region 111, the second well region 103, the second doped region 112, the third doped region 113, and then through the fourth doped region 114 to the ground or the contact pad 122. Specifically, when ESD stress is applied to the internal circuit, the ESD current flows from contact pad 121 to first doped region 111, flows into second well region 103 through the PN junction formed by first doped region 111 and second well region 103, then flows into second doped region 112 through the PN junction formed by second well region 103 and second doped region 112, and then flows into third doped region 113 via metal wire 129. The ESD current then flows from third doped region 113 into second well region 103, flows into first well region 102 through the PN junction formed by second well region 103 and first well region 102, then flows into substrate 101 through the PN junction formed by first well region 102 and substrate 101, then flows into fourth doped region 114 through the PN junction formed by substrate 101 and fourth doped region 114, and then flows from fourth doped region 114 into contact pad 122 or into ground via metal wire 130. When ESD stress is applied to the internal circuit, first well region 102 can remain in a floating state.

[0047] The second well region 103, the first well region 102, and the substrate 101 form a PNP bipolar junction transistor (BJT) with P-type majority carriers. The first well region 102, the substrate 101, and the fourth doped region 114 form an NPN bipolar junction transistor with N-type majority carriers. The collector of the PNP BJT is connected to the base of the NPN BJT; and the base of the PNP BJT is connected to the collector of the NPN BJT, thereby forming a thyristor rectifier in the electrostatic discharge protection device 10. The second well region 103 can serve as the anode of the thyristor rectifier; the fourth doped region 114 can serve as the cathode of the thyristor rectifier. When ESD stress is applied to the internal circuit electrically connected to the ESD protection device 10 , the ESD current entering the first doped region 111 flows to the fourth doped region 114 through the SCR, thereby directing the ESD current away from the internal circuit.

[0048] [Second embodiment]

[0049] Please refer to Figure 2 , which illustrates a cross-sectional view of an ESD protection device 20 according to a second embodiment of the present disclosure. The difference between the second embodiment and the first embodiment lies in the different positions of the fourth doping region 114 and the fifth doping region 115 relative to the N-type metal oxide semiconductor field effect transistor in the ESD protection device 20 of the second embodiment. Specifically, in the ESD protection device 20 of the second embodiment, the fourth doping region 114 and the fifth doping region 115 are disposed near the first doping region 111, while in the ESD protection device 10 of the first embodiment, the fourth doping region 114 and the fifth doping region 115 are disposed near the third doping region 113.

[0050] In this embodiment, there is a distance D2 between the second well region 103 and the fourth doping region 114. The distance D2 can be defined as the minimum distance between the second well region 103 and the fourth doping region 114. Figure 2 As shown, the distance D2 may represent the distance between the boundary of the second well region 103 and the boundary of the fourth doping region 114 in a direction parallel to the upper surface of the substrate 101. The distance D2 may be less than 20 micrometers.

[0051] When ESD protection device 20 is used to protect internal circuits in an integrated circuit, the internal circuits can be electrically connected to contact pads 121 in ESD protection device 20. When ESD stress is applied to the internal circuits, the ESD path in ESD protection device 20 is the same as that of ESD protection device 10 in the first embodiment, and first well region 102 can remain in a floating state. Second well region 103, first well region 102, substrate 101, and fourth doped region 114 form a thyristor (SCR) in ESD protection device 20. Second well region 103 can serve as the anode of the SCR, and fourth doped region 114 can serve as the cathode of the SCR. When ESD stress is applied to the internal circuits electrically connected to ESD protection device 20, ESD current entering first doped region 111 flows through the SCR to fourth doped region 114, directing the ESD current away from the internal circuits.

[0052] [Third embodiment]

[0053] Please refer to Figure 3 , which illustrates a cross-sectional view of an ESD protection device 30 according to a third embodiment of the present disclosure. The difference between the third embodiment and the first embodiment is that the ESD protection device 30 of the third embodiment further includes a resistor 331 electrically connected to the fifth doped region 115. The fourth doped region 114 is electrically connected to a node 332 between the resistor 331 and the contact pad 122.

[0054] When ESD protection device 30 is used to protect internal circuits in an integrated circuit, the internal circuits can be electrically connected to contact pads 121 in ESD protection device 30. When ESD stress is applied to the internal circuits, the ESD path in ESD protection device 30 is the same as that of ESD protection device 10 in the first embodiment, and first well region 102 can remain in a floating state. Second well region 103, first well region 102, substrate 101, and fourth doped region 114 form a thyristor (SCR) in ESD protection device 30. Second well region 103 can serve as the anode of the SCR, and fourth doped region 114 can serve as the cathode of the SCR. When ESD stress is applied to the internal circuits electrically connected to ESD protection device 30, ESD current entering first doped region 111 flows through the SCR to fourth doped region 114, directing the ESD current away from the internal circuits.

[0055] [Fourth embodiment]

[0056] Please refer to Figure 4, which shows a cross-sectional view of an electrostatic discharge protection device 40 according to the fourth embodiment of the present disclosure. The difference between the fourth embodiment and the first embodiment is that the electrostatic discharge protection device 40 of the fourth embodiment further includes a third well region 404, and the third well region 404 has a second conductivity type. The second well region 103 and the third well region 404 are both disposed in the first well region 102, and the fourth doping region 114 and the fifth doping region 115 are both disposed in the third well region 404. In one embodiment, an ion implantation process can be used to form the third well region 404. The second well region 103 and the third well region 404 can have similar doping concentrations. The second well region 103 and the third well region 404 can be spaced apart from each other. In one embodiment, the lateral distance D1 between the third doping region 113 and the fourth doping region 114 can be less than 20 microns.

[0057] The depth of the first well region 102 in the substrate 101 may be greater than the depths of the second well region 103 and the third well region 404 in the substrate 101. Therefore, the first well region 102 may also be understood as a deep well region, and the second well region 103 and the third well region 404 may also be understood as shallow well regions. The width of the first well region 102 may be greater than the widths of the second well region 103 and the third well region 404. The first well region 102 may surround the second well region 103 and the third well region 404. The second well region 103 and the third well region 404 may both be disposed within the outline of the first well region 102.

[0058] When ESD protection device 40 is used to protect internal circuits in an integrated circuit, the internal circuits can be electrically connected to contact pads 121 in ESD protection device 40. When ESD stress is applied to the internal circuits, ESD current can flow from contact pads 121 through metal wires 128 into ESD protection device 40. The ESD current then flows sequentially through first doped region 111, second well region 103, second doped region 112, and third doped region 113, and then through fourth doped region 114 to ground or contact pads 122. Specifically, when ESD stress is applied to the internal circuits, the ESD current flows from contact pads 121 to first doped region 111, flows through the PN junction formed by first doped region 111 and second well region 103, flows into second well region 103, then flows through the PN junction formed by second well region 103 and second doped region 112 into second doped region 112, and then flows through metal wires 129 to third doped region 113. Then, the ESD current flows from third doped region 113 into second well region 103, flows through the PN junction formed by second well region 103 and first well region 102 into first well region 102, then flows through the PN junction formed by first well region 102 and third well region 404 into third well region 404, then flows through the PN junction formed by third well region 404 and fourth doped region 114 into fourth doped region 114, and then flows from fourth doped region 114 through metal wire 130 to contact pad 122 or into the ground. When ESD stress is applied to the internal circuit, first well region 102 can remain in a floating state.

[0059] The second well region 103, the first well region 102, and the third well region 404 form a PNP bipolar junction transistor with P-type majority carriers. The first well region 102, the third well region 404, and the fourth doped region 114 form an NPN bipolar junction transistor with N-type majority carriers. The collector of the PNP bipolar junction transistor is connected to the base of the NPN bipolar junction transistor; and the base of the PNP bipolar junction transistor is connected to the collector of the NPN bipolar junction transistor, thereby forming a thyristor (SCR) in the ESD protection device 40. The second well region 103 serves as the anode of the SCR; the fourth doped region 114 serves as the cathode of the SCR. When ESD stress is applied to the internal circuit electrically connected to the ESD protection device 40, the ESD current entering the first doped region 111 flows through the SCR to the fourth doped region 114, thereby directing the ESD current away from the internal circuit.

[0060] [Fifth embodiment]

[0061] Please refer to Figure 5, which illustrates a cross-sectional view of an ESD protection device 50 according to a fifth embodiment of the present disclosure. The fifth embodiment differs from the fourth embodiment in that the fifth doped region 115 in the ESD protection device 50 is not electrically connected to the contact pad 122. The metal conductive line 130 in the ESD protection device 50 is not electrically connected to the fifth doped region 115.

[0062] When ESD protection device 50 is used to protect internal circuits in an integrated circuit, the internal circuits can be electrically connected to contact pads 121 in ESD protection device 50. When ESD stress is applied to the internal circuits, the ESD path in ESD protection device 50 is the same as that of ESD protection device 40 in the fourth embodiment. The first well region 102 and the third well region 404 in ESD protection device 50 can remain in a floating state. The second well region 103, the first well region 102, the third well region 404, and the fourth doped region 114 form a thyristor (SCR) in ESD protection device 50. The second well region 103 can serve as the anode of the SCR, and the fourth doped region 114 can serve as the cathode of the SCR. When ESD stress is applied to the internal circuits electrically connected to ESD protection device 50, the ESD current entering the first doped region 111 flows through the SCR to the fourth doped region 114, thereby directing the ESD current away from the internal circuits.

[0063] [Sixth embodiment]

[0064] Please refer to Figure 6 , which illustrates a cross-sectional view of an ESD protection device 60 according to a sixth embodiment of the present disclosure. The difference between the sixth embodiment and the fourth embodiment is that the ESD protection device 60 of the sixth embodiment further includes a resistor 631 electrically connected to the fifth doped region 115. The fourth doped region 114 is electrically connected to a node 632 between the resistor 631 and the contact pad 122.

[0065] When ESD protection device 60 is used to protect internal circuits in an integrated circuit, the internal circuits can be electrically connected to contact pads 121 in ESD protection device 60. When ESD stress is applied to the internal circuits, the ESD path in ESD protection device 60 is the same as that of ESD protection device 40 in the fourth embodiment, and first well region 102 can remain in a floating state. Second well region 103, first well region 102, third well region 404, and fourth doped region 114 form a thyristor (SCR) in ESD protection device 60. Second well region 103 can serve as the anode of the SCR, and fourth doped region 114 can serve as the cathode of the SCR. When ESD stress is applied to the internal circuits electrically connected to ESD protection device 60, ESD current entering first doped region 111 flows through the SCR to fourth doped region 114, directing the ESD current away from the internal circuits.

[0066] The ESD protection device according to an embodiment of the present disclosure may include an N-type metal oxide semiconductor field effect transistor, and the N-type metal oxide semiconductor field effect transistor may be a low voltage N-type metal oxide semiconductor field effect transistor or a medium voltage N-type metal oxide semiconductor field effect transistor. The ESD protection device according to an embodiment of the present disclosure may be a high voltage ESD protection device.

[0067] According to the embodiments of the present disclosure, the electrostatic discharge protection device (e.g., electrostatic protection device 10, 20, 30, 40, 50, 60) includes an N-type metal oxide semiconductor field effect transistor and a doped region 114. This configuration has the advantage of a smaller layout area and a better electrostatic discharge protection capability compared to a high-voltage electrostatic discharge protection device formed by stacking low-voltage transistors. Moreover, the electrostatic discharge protection device (e.g., electrostatic protection device 10, 20, 30, 40, 50, 60) of the present disclosure has a thyristor rectifier, which has a better electrostatic discharge protection capability than an electrostatic discharge protection device including only an N-type metal oxide semiconductor field effect transistor, an electrostatic discharge protection device including only a PNP bipolar junction transistor, and an electrostatic discharge protection device including only an NPN bipolar junction transistor. In addition, in some embodiments, when electrostatic discharge stress is applied to an internal circuit electrically connected to the electrostatic discharge protection device, the electrostatic discharge protection device includes more than one well region in a floating state (e.g., Figure 5 In the fifth embodiment, the first well region 102 and the third well region 404 are in a floating state. This configuration provides stronger ESD protection capabilities than an ESD protection device with only one floating well region. Therefore, the ESD protection device disclosed herein can effectively divert ESD current away from internal circuits, thereby improving the reliability of integrated circuits, increasing the area efficiency of integrated circuits, and reducing the manufacturing cost of integrated circuits.

[0068] It should be noted that the figures, structures and steps described above are used to describe some embodiments or application examples of the present invention, and the present invention is not limited to the scope and application examples of the above structures and steps. Other embodiments with different structural examples, such as known components of different internal components, can be applied, and the structures and steps of the examples can be adjusted according to the needs of actual applications. Therefore, the structure of the figure is only used to illustrate, and is not used to limit the present invention. Those skilled in the art should know that the relevant structures and step processes of the application of the present invention, such as the arrangement or configuration of the relevant elements and layers in the semiconductor structure, or the details of the manufacturing steps, etc., may be adjusted and changed accordingly according to the needs of the actual application examples.

[0069] In summary, although the present invention has been disclosed above with reference to the embodiments, these are not intended to limit the present invention. Persons skilled in the art will readily appreciate that various modifications and variations can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. An electrostatic discharge protection device, characterized in that: include: a substrate; a first well region disposed in the substrate, the first well region having a first conductivity type; a second well region disposed in the first well region, the second well region having a second conductivity type; a first doped region disposed in the second well region, the first doped region having the first conductivity type; a second doped region disposed in the second well region, the second doped region having the first conductivity type; a third doped region disposed in the second well region, the third doped region having the second conductivity type; a fourth doped region disposed in the substrate, the fourth doped region having the first conductivity type; and a metal wire, the second doped region is electrically connected to the third doped region through the metal wire; The first conductivity type is different from the second conductivity type, the second well region, the first well region, the substrate and the fourth doped region constitute a thyristor rectifier, and an electrostatic discharge current entering the first doped region flows to the fourth doped region through the thyristor rectifier.

2. The electrostatic discharge protection device according to claim 1, characterized in that: Also includes: a contact pad electrically connected to the fourth doped region; a fifth doped region disposed in the substrate, the fifth doped region having the second conductivity type; as well as A resistor element is electrically connected to the fifth doped region, wherein the fourth doped region is electrically connected to a node between the resistor element and the contact pad.

3. An electrostatic discharge protection device, characterized in that: include: a substrate; a first well region disposed in the substrate, the first well region having a first conductivity type; a second well region disposed in the first well region, the second well region having a second conductivity type; a third well region disposed in the first well region, the third well region having the second conductivity type; a first doped region disposed in the second well region, the first doped region having the first conductivity type; a second doped region disposed in the second well region, the second doped region having the first conductivity type; a third doped region disposed in the second well region, the third doped region having the second conductivity type; a fourth doped region disposed in the third well region, the fourth doped region having the first conductivity type; a metal wire, the second doped region is electrically connected to the third doped region through the metal wire; The first conductivity type is different from the second conductivity type, the second well region, the first well region, the third well region and the fourth doped region constitute a thyristor rectifier, and an electrostatic discharge current entering the first doped region flows through the thyristor rectifier to the fourth doped region.

4. The electrostatic discharge protection device according to claim 3, characterized in that: Also includes: a contact pad electrically connected to the fourth doped region; a fifth doped region disposed in the third well region, the fifth doped region having the second conductivity type; as well as A resistor element is electrically connected to the fifth doped region, wherein the fourth doped region is electrically connected to a node between the resistor element and the contact pad.

5. A method for operating an electrostatic discharge protection device, characterized in that: include: An electrostatic discharge protection device is provided. The electrostatic discharge protection device is electrically connected to an internal circuit. The electrostatic discharge protection device includes: a substrate; a first well region disposed in the substrate, the first well region having a first conductivity type; a second well region disposed in the first well region, the second well region having a second conductivity type; a first doped region disposed in the second well region, the first doped region having the first conductivity type; a second doped region disposed in the second well region, the second doped region having the first conductivity type; a third doped region disposed in the second well region, the third doped region having the second conductivity type; a fourth doped region disposed in the substrate, the fourth doped region having the first conductivity type; and a metal wire, the second doped region being electrically connected to the third doped region through the metal wire; wherein the first conductivity type is different from the second conductivity type, and the second well region, the first well region, the substrate, and the fourth doped region constitute a silicon controlled rectifier; and When an electrostatic discharge stress is applied to the internal circuit, an electrostatic discharge current flows through the silicon controlled rectifier to keep the electrostatic discharge current away from the internal circuit.

6. The operating method according to claim 5, characterized in that: The method further includes maintaining the first well region in a floating state when the electrostatic discharge stress is applied to the internal circuit.

7. The operating method according to claim 5, characterized in that: The electrostatic discharge current flows from the second doping region to the third doping region through the metal wire.

8. A method for operating an electrostatic discharge protection device, characterized in that: include: An electrostatic discharge protection device is provided. The electrostatic discharge protection device is electrically connected to an internal circuit. The electrostatic discharge protection device includes: a substrate; a first well region disposed in the substrate, the first well region having a first conductivity type; a second well region disposed in the first well region, the second well region having a second conductivity type; a third well region disposed in the first well region, the third well region having the second conductivity type; a first doped region disposed in the second well region, the first doped region having the first conductivity type; a second doped region disposed in the second well region, the second doped region having the first conductivity type; a third doped region disposed in the second well region, the third doped region having the second conductivity type; and a fourth doped region disposed in the third well region, the fourth doped region having the first conductivity type; and a metal wire, the second doped region is electrically connected to the third doped region through the metal wire; wherein the first conductivity type is different from the second conductivity type, and the second well region, the first well region, the third well region, and the fourth doped region constitute a silicon controlled rectifier; and When an electrostatic discharge stress is applied to the internal circuit, an electrostatic discharge current flows through the silicon controlled rectifier to keep the electrostatic discharge current away from the internal circuit.

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