Semiconductor Structure and Method for Preparing the Same

Abstract

The present application discloses a semiconductor structure and a method for manufacturing the same, belonging to the field of semiconductor technology. The method for manufacturing the semiconductor structure includes: providing a substrate; forming a trench in the substrate; performing a first thermal oxidation reaction to form a first oxide layer at the bottom and sidewalls of the trench in an environment with a pressure of 500 to 800 Torr, and the thickness of the first oxide layer gradually decreases along the direction close to the bottom. The thickness of the oxide layer obtained by this method gradually decreases from the edge of the trench towards the bottom of the trench, so that the oxide layer inside the trench presents a stepped coverage. Since oxide layers with different thicknesses are formed on the sidewalls and the bottom of the trench, the thicker sidewalls can reduce gate leakage, and the thinner bottom can enhance the gate control ability. Therefore, this method can improve the reliability of the semiconductor structure and the product yield.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] A memory includes a plurality of memory cells, each memory cell comprising a MOS transistor and a storage capacitor. The MOS transistor is short for Metal-Oxide-Semi-conductor Field-Effect Transistor.

[0003] According to Moore's Law, the size of memory devices will become smaller and smaller, and the channel length of MOS transistors is also continuously shortened. The short-channel effect will cause semiconductor devices to fail and reduce the yield. Summary of the Invention

[0004] The objective of this application is to provide a semiconductor structure and a method for manufacturing the same to at least solve the problem that the yield of existing semiconductor devices is reduced due to the short-channel effect.

[0005] The technical solution of this application is as follows:

[0006] According to an embodiment of this application, a method for manufacturing a word line structure is provided. The method may include: providing a substrate; forming a trench in the substrate; performing a first thermal oxidation reaction in an environment with a pressure of 500 to 800 Torr to form a first oxide layer on the bottom and side walls of the trench, and the thickness of the first oxide layer gradually decreases in a direction close to the bottom.

[0007] In some alternative embodiments of this application, the reaction temperature of the first thermal oxidation reaction may be 800 - 1100 degrees Celsius.

[0008] In some alternative embodiments of this application, the gases for the first thermal oxidation reaction may include: O2, H2, and N2; wherein, the flow rate ratio of H2 to N2 satisfies the following formula:

[0009] Q H2 <4%*(Q N2 +Q H2 );

[0010] wherein, Q H2 is the flow rate of H2 introduced into the first thermal oxidation reaction, and Q N2 is the flow rate of N2 introduced into the first thermal oxidation reaction.

[0011] In some alternative embodiments of the present application, the gas for the first thermal oxidation reaction may include: O2, H2, and an inert gas; wherein, the flow rate ratio of H2 to the inert gas satisfies the following formula:

[0012] Q H2 <3%*(Q 惰 +Q H2 );

[0013] Wherein, Q H2 is the flow rate of H2 introduced into the first thermal oxidation reaction, and Q 惰 is the flow rate of the inert gas introduced into the first thermal oxidation reaction.

[0014] In some alternative embodiments of the present application, the preparation method may further include: annealing the first oxide layer.

[0015] In some alternative embodiments of the present application, the preparation method may further include: performing a second thermal oxidation reaction at a preset pressure on the first oxide layer to form a second oxide layer, and the preset pressure is less than the reaction pressure of the first thermal oxidation reaction;

[0016] In some alternative embodiments of the present application, the reaction temperature of the second thermal oxidation reaction may be 800 - 1100 degrees Celsius.

[0017] In some alternative embodiments of the present application, the preset pressure may be 0 - 20 Torr.

[0018] In some alternative embodiments of the present application, the gas for the second thermal oxidation reaction may include an oxygen-containing gas and H2.

[0019] In some alternative embodiments of the present application, the flow rate ratio of H2 to the oxygen-containing gas may satisfy the following formula:

[0020] Q H2 <30%*(Q 含 +Q H2 );

[0021] Wherein, Q H2 is the flow rate of H2 introduced into the second thermal oxidation reaction, and the Q 含 is the flow rate of the oxygen-containing gas introduced into the second thermal oxidation reaction.

[0022] In some alternative embodiments of the present application, the range of the thickness ratio of the first oxide layer to the second oxide layer may be 1 / 4 to 2 / 3.

[0023] In some alternative embodiments of the present application, the preparation method may further include: forming a barrier layer on the surface of the second oxide layer; filling a conductive metal in the trench, and the conductive metal covering the surface of the barrier layer.

[0024] According to a second aspect of the embodiments of the present application, there is also provided a semiconductor structure, which may include: a substrate having a trench; a first oxide layer covering the bottom and sidewalls of the trench, and the thickness of the first oxide layer gradually decreasing in a direction close to the bottom.

[0025] In some alternative embodiments of the present application, the semiconductor structure may further include: a second oxide layer covering the surface of the first oxide layer; a barrier layer covering the surface of the second oxide layer; a conductive metal filled in the trench, and the conductive metal covering the surface of the barrier layer.

[0026] In some alternative embodiments of the present application, the first oxide layer and the second oxide layer may serve as a gate dielectric layer.

[0027] The method of the embodiments of the present application forms a trench in a substrate and performs a first thermal oxidation reaction in an environment with a pressure of 500 to 800 Torr to form a first oxide layer on the bottom and sidewalls of the trench, and the thickness of the first oxide layer decreases in a gradient manner in a direction close to the bottom. The thickness of the oxide layer obtained by this method gradually decreases from the edge of the trench to the bottom direction, so that the oxide layer inside the trench is step-covered. The obtained oxide layer structure in the embodiments of the present application can serve as a gate dielectric layer of a semiconductor memory device, and then can form a gate structure with a barrier layer and a conductive metal, and form a word line structure. At this time, since oxide layers with different thicknesses are formed on the sidewalls and bottom of the trench, the thicker sidewalls can reduce gate leakage, and the thinner bottom can enhance the gate control ability. Therefore, this method can improve the reliability of the semiconductor structure and the product yield. Description of the Drawings

[0028] Figure 1 is a schematic flowchart of a method for preparing a semiconductor structure according to an exemplary embodiment of the present application;

[0029] Figures 2 - 6 is a structural change diagram of the preparation process of a semiconductor structure according to an exemplary embodiment of the present application;

[0030] Figure 7 is a schematic flowchart of a method for preparing a semiconductor structure according to another exemplary embodiment of the present application

[0031] Figures 8 - 9 is a structural change diagram of the preparation process of a semiconductor structure according to another exemplary embodiment of the present application;

[0032] Figures 10 - 12It is a schematic diagram of a semiconductor structure according to an exemplary embodiment of the present application. Detailed implementation manners

[0033] In order to enable those of ordinary skill in the art to better understand the technical solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0035] According to Moore's Law, the size of memory devices will become smaller and smaller, and the channel length of field-effect transistors is also constantly shortening. The short-channel effect causes device failure and reduces the yield. The inventors have found that the use of an embedded word line design can reduce device failure caused by the short-channel effect. A groove structure is obtained in a silicon substrate by an etching method, and then a uniformly thick oxide layer is formed on the sidewalls and bottom of the groove structure by a thermal oxidation process. However, this method makes the sidewall silicon lattice obtained by etching easily damaged, which easily leads to gate leakage and thus reduces the yield. Therefore, the present application provides a word line structure and its manufacturing method, a semiconductor structure and its manufacturing method to solve this problem.

[0036] The manufacturing method of the word line structure provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings and specific embodiments and their application scenarios.

[0037] As Figure 1 shown, in the first aspect of the embodiments of the present application, a manufacturing method of a semiconductor is provided, and the method may include:

[0038] S110: Provide a substrate 1;

[0039] S120: Form a trench 11 in the substrate 1;

[0040] S130: Under an environment with a pressure of 500 to 800 Torr, perform a first thermal oxidation reaction to form a first oxide layer 21 on the bottom and sidewalls of the trench 11, and the thickness of the first oxide layer 21 gradually decreases in the direction close to the bottom;

[0041] In the method of this embodiment, by controlling the reaction pressure of 500 to 800 Torr, when O2 is introduced for thermal oxidation, the oxygen concentration in the region from the top to the bottom in the trench 11 gradually decreases, so that the thickness of the first oxide layer 21 formed on the inner wall of the trench 11 covers in a stepped manner. As Figure 4 shown, the side walls and the bottom of the trench 11 form the first oxide layer 21 with different thicknesses. The first oxide layer 21 at the side walls has an ideal thickness, which can avoid the problem of some defects generated by etching the substrate to obtain the trench 11. For example, the first oxide layer 21 can effectively reduce gate leakage. The thickness of the first oxide layer 21 at the bottom is relatively thin, which can strengthen the control ability of the gate, improve the reliability of the word line structure, and thus improve the yield of the semiconductor structure product.

[0042] For a clearer description, the above method steps will be described separately as follows:

[0043] First, implement step S110: Provide a substrate 1, as Figure 2 shown.

[0044] The material of the substrate 1 in this step includes but is not limited to silicon crystal or germanium crystal, silicon-on-insulator (SOI) structure or epitaxial layer structure on silicon, compound semiconductor (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysproside), alloy semiconductor (such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or their combinations).

[0045] Implement step S120: Form a trench 11 in the substrate 1, as Figure 3 shown.

[0046] This step may be to form a mask on the substrate 1 and use photolithography and etching processes to form the trench 11 on the substrate 1. The trench 11 may be a word line trench, so that subsequent deposition processes can be carried out in the word line trench to obtain a word line structure. In addition to including the formation of an embedded word line structure, the substrate 1 may include the formation of other semiconductor structures, which is not limited herein.

[0047] Exemplarily, before forming the trench 11, an oxide isolation layer is further formed on the surface of the substrate 1. The oxide isolation layer does not cover the inner surface of the trench 11, but only covers the upper surface of the substrate 1. The oxide isolation layer can protect the upper surface of the substrate 1 in subsequent processes and prevent it from being etched.

[0048] This step is to solve the problem of semiconductor device failure caused by the short-channel effect. In this embodiment, the buried word line method is used to solve the short-channel effect. First, on the substrate 1, a trench 11 is formed by etching means, and the substrate 1 with the trench 11 is obtained. The substrate in this embodiment is a silicon crystal substrate. However, the silicon lattice on the sidewalls of the trench 11 obtained by etching is easily damaged, and the damaged silicon lattice is likely to cause gate leakage, thereby reducing the yield of semiconductor devices. Therefore, to solve this problem, the next step S130 is introduced.

[0049] Implementation step S130: In an environment with a pressure of 500 - 800 Torr, a first thermal oxidation reaction is carried out to form a first oxide layer 21 on the bottom and sidewalls of the trench 11. The thickness of the first oxide layer 21 gradually decreases along the direction close to the bottom, as Figure 4 shown in the locally enlarged area A.

[0050] This step is to solve the problem of gate leakage caused by damaged silicon lattice. A first oxide layer 21 is formed on the inner wall surface of the trench 11, and this first oxide layer 21 can effectively prevent the silicon lattice from being damaged, thereby preventing the occurrence of leakage. Forming the first oxide layer 21 on the inner wall surface of the trench 11 can be achieved by carrying out a first thermal oxidation reaction in an environment with a pressure of 500 - 800 Torr to form the first oxide layer 21 inside the trench 11. At a pressure of 500 - 800 Torr, such as 700 Torr or 760 Torr, under this pressure condition, the reaction gas is not evenly distributed in the trench 11. The concentration of the reaction gas is higher near the mouth of the trench 11 and lower at the bottom of the trench 11. Therefore, during the thermal oxidation reaction, an oxide layer with a thickness decreasing in a gradient trend will be formed on the inner wall of the trench 11. The thickness of the oxide layer in the trench 11 gradually decreases along the edge of the trench towards the bottom of the trench 11.

[0051] In this step, the reaction temperature of the first thermal oxidation reaction can be 800 - 1100 degrees Celsius. For example, the reaction temperature can be 800 degrees Celsius, 850 degrees Celsius, 900 degrees Celsius, 950 degrees Celsius, 1000 degrees Celsius, 1050 degrees Celsius, 1100 degrees Celsius. The oxide layer formed within the range of 800 - 1100 degrees Celsius is relatively dense and can effectively prevent leakage.

[0052] The gas for the first thermal oxidation reaction can include: O2, H2, and N2; among them, the flow rate ratio of H2 to N2 satisfies the following formula:

[0053] Q H2 <4%*(Q N2 +Q H2 );

[0054] where, Q H2 is the flow rate of H2 introduced for the first thermal oxidation reaction, QN2 The flow rate of N2 introduced for the first thermal oxidation reaction. This formula can represent that the flow rate of hydrogen introduced is less than 4% of the total flow rate of hydrogen and nitrogen; the percentage of the flow rate of hydrogen in the total flow rate of hydrogen and nitrogen can represent the concentration of hydrogen. Therefore, this formula can also represent that the concentration of hydrogen is less than 4%. The flow rate ratio of H2 to N2 can be the flow rate ratio for completing the growth process of the first oxide layer 21, for example, 2% or 3%. In this oxidation process, H2 and N2 within the above range are intermittently introduced in an O2 atmosphere to adjust the gradient thickness of the first oxide layer 21 and reduce film layer defects.

[0055] The reaction gases for the first thermal oxidation reaction can also include: O2, H2, and an inert gas; wherein, the flow rate ratio of H2 to the inert gas satisfies the following formula:

[0056] Q H2 <3%*(Q 惰 +Q H2 );

[0057] wherein, Q H2 is the flow rate of H2 introduced for the first thermal oxidation reaction, and Q 惰 is the flow rate of the inert gas introduced for the first thermal oxidation reaction. This formula can represent that the flow rate of hydrogen introduced is less than 3% of the total flow rate of hydrogen and the inert gas; the percentage of the flow rate of hydrogen in the total flow rate of hydrogen and the inert gas can represent the concentration of hydrogen. Therefore, this formula can also represent that the concentration of hydrogen is less than 3%. The flow rate ratio of H2 to the inert gas can be the flow rate ratio for completing the growth process of the first oxide layer 21, for example, 2% or 2.5%. In this oxidation process, H2 and the inert gas within the above range are intermittently introduced in an O2 atmosphere. The inert gas can include Ar, Ne, He, etc., to adjust the gradient thickness of the first oxide layer 21 and reduce film layer defects.

[0058] Exemplarily, this first thermal oxidation reaction is, for example, an in-situ steam oxidation reaction. The reaction pressure is carried out under atmospheric pressure conditions, for example, 760 Torr, and the reaction temperature is 900 degrees Celsius. The reaction gases include: H2, N2, and the oxidant O2. Among them, the flow rate ratio of H2 to N2 is 3%. In this oxidation process, O2 is continuously introduced, and H2 and N2 are intermittently introduced. Through this exemplary method, a dense oxide dielectric layer is formed at the bottom and sidewalls of the trench 11 in the semiconductor structure, and the thickness of this oxide dielectric layer decreases in a gradient along the direction close to the bottom. This can effectively reduce the leakage current on the sidewalls of the trench 11 and increase the electric field control ability.

[0059] In another example, the first thermal oxidation reaction is an in-situ steam oxidation reaction, and the reaction pressure is carried out under atmospheric pressure conditions, such as 760 Torr. The reaction temperature of the in-situ steam oxidation is 900 degrees Celsius. The gases for the first thermal oxidation reaction include: Ar, H2 and the oxidant O2. Among them, the flow ratio of H2 to Ar is less than 2%. O2 is continuously introduced during the oxidation process, and Ar and H2 are intermittently introduced. Through this exemplary method, a dense oxidation dielectric layer is formed at the bottom and sidewalls of the trench 11 in the semiconductor structure, and the thickness of the oxidation dielectric layer decreases in a gradient along the direction close to the bottom. This can effectively reduce the leakage current on the sidewalls of the trench 11 and increase the electric field control ability.

[0060] In some alternative embodiments of the present application, after the first thermal oxidation reaction is carried out to form the first oxide layer 21 at the bottom and sidewalls of the trench 11, to improve the quality of the first oxide layer 21, the method for preparing the semiconductor structure may further include: annealing the first oxide layer 21 to improve the density of the first oxide layer 21. The annealing temperature is, for example, 800 - 1100 degrees Celsius, such as 800 degrees Celsius, 850 degrees Celsius. The annealing temperature can be greater than or equal to the reaction temperature of the first thermal oxidation to ensure the quality of the first oxide layer 21, shield the defects of damaged silicon lattices, and improve the yield of semiconductor devices.

[0061] In some alternative embodiments of the present application, the method for preparing the semiconductor structure further includes forming a barrier layer 3 and filling a conductive metal 4 in the trench 11, as Figure 5 and Figure 6 shown, the barrier layer 3 covers the surface of the first oxide layer 21, and the conductive metal 4 covers the surface of the barrier layer 3. The first oxide layer 21 serves as the gate dielectric layer 2, and together with the barrier layer 3 and the conductive metal 4, they serve as, for example, the gate structure of a semiconductor device and the word line structure, as Figure 6 shown.

[0062] As Figure 7 shown, in some alternative embodiments of the present application, a method for preparing a semiconductor structure is provided, and the method may include:

[0063] S710: Provide a substrate 1;

[0064] S720: Form a trench 11 in the substrate 1;

[0065] S730: Under an environment with a pressure of 500 - 800 Torr, carry out a first thermal oxidation reaction to form a first oxide layer 21 at the bottom and sidewalls of the trench 11, and the thickness of the first oxide layer 21 gradually decreases along the direction close to the bottom;

[0066] S740: On the first oxide layer 21, a second thermal oxidation reaction under a preset pressure is carried out to form a second oxide layer 22, and the preset pressure is less than the reaction pressure of the first thermal oxidation reaction.

[0067] As Figure 8 shown, in this embodiment, the first thermal oxide layer 21 is not annealed, but a second thermal oxidation process is carried out on the surface of the first oxide layer 21 to form a second oxide layer 22 on the surface of the first thermal oxide layer 21. The first oxide layer 21 and the second oxide layer 22 together serve as the gate dielectric layer 2. Among them, the side wall of the first oxide layer 21 is thicker, while the bottom is thinner. Then, through the second thermal oxidation reaction, the second oxide layer 22 is continuously formed along the structure of the first oxide layer 21. In this way, while increasing the overall thickness of the gate dielectric layer 2, the first oxide layer 21 is annealed to improve the reliability of the gate dielectric layer 2 and effectively utilize energy, as Figure 9 shown. Moreover, the obtained word line structure can reduce gate leakage, thereby improving the reliability of the subsequently manufactured semiconductor device.

[0068] In some alternative embodiments of the present application, the reaction temperature of the second thermal oxidation reaction can be 800 - 1100 degrees Celsius. Exemplarily, the reaction temperature can be 800 degrees Celsius, 850 degrees Celsius, 900 degrees Celsius, 950 degrees Celsius, 1000 degrees Celsius, 1050 degrees Celsius, 1100 degrees Celsius. The oxide layer formed within the range of 800 - 1100 degrees Celsius is relatively dense and can effectively prevent leakage.

[0069] Exemplarily, when the reaction temperature of the second thermal oxidation reaction is controlled to be the same as that of the first thermal oxidation reaction, the film quality of the gate dielectric layer 2 can be ensured.

[0070] In some alternative embodiments of the present application, the preset pressure is 0 - 20 Torr, such as 0 Torr, 5 Torr, 10 Torr. The gas under the condition of a pressure of 0 - 20 Torr is relatively uniformly distributed in the region from the top to the bottom in the trench 11, and the concentration of the gas in the trench 11 is relatively uniform. Therefore, the thickness of the second oxide layer 22 formed by the second thermal oxidation process under this preset pressure is uniform. In cooperation with the first thermal oxidation process of 500 - 800 Torr, on the basis of the first oxide layer 21, the first oxide layer 21 is thickened to obtain a gate dielectric layer 2 with a stepped coverage, and the side wall of the gate dielectric layer 2 is thicker than the bottom, preventing leakage caused by side wall etching defects. At the same time, the thinner bottom can enhance the gate control ability.

[0071] In some alternative embodiments of the present application, the gas for the second thermal oxidation reaction may include an oxygen-containing gas and H2. The oxygen-containing gas may include O2, NO, N2O, which provide an oxygen source for the second thermal oxidation reaction. Different from the first thermal oxidation reaction, in the first thermal oxidation process, pure oxygen O2 needs to be used to avoid the first oxide layer 21 with an unexpected structure. However, for the second thermal oxidation reaction, an oxygen-containing gas can be used without special limitation.

[0072] In this embodiment, H2 is introduced intermittently to ensure the uniform distribution of the oxidizing gas, which can make the thickness of the second oxide layer 22 uniform.

[0073] In some alternative embodiments of the present application, the gas for the second thermal oxidation reaction may include: an oxygen-containing gas and H2;

[0074] Q H2 <30%*(Q 含 +Q H2 );

[0075] Wherein, Q H2 is the flow rate of H2 introduced into the second thermal oxidation reaction, and Q 含 is the flow rate of the oxygen-containing gas introduced into the second thermal oxidation reaction. This formula can indicate that the flow rate of hydrogen introduced is less than 30% of the total flow rate of hydrogen and the oxygen-containing gas; the percentage of the flow rate of hydrogen in the total flow rate of hydrogen and the oxygen-containing gas can represent the concentration of hydrogen. Therefore, this formula can also indicate that the concentration of hydrogen is less than 30%; for example, the upper limit values of the concentration of hydrogen can be 18%, 22%, 28%, 30%. In the atmosphere of the oxygen-containing gas introduced during this oxidation process, H2 within the above range is introduced intermittently to form the second oxide layer 22 and reduce film layer defects.

[0076] In this embodiment, H2 is introduced intermittently to ensure the uniform distribution of the oxidizing gas, which can make the thickness of the gate dielectric layer 2 uniform.

[0077] In some alternative embodiments of the present application, the range of the thickness ratio of the first oxide layer 21 to the second oxide layer 22 may be from 1 / 4 to 2 / 3.

[0078] In this embodiment, the range of the thickness ratio of the first oxide layer 21 to the second oxide layer 22 may be the range of the ratio of the average thickness of the first oxide layer 21 to the average thickness of the second oxide layer 22, or may also be the variation range of the ratio of the thickness from the thinnest part to the thickest part of the first oxide layer 21 to the thickness of the second oxide layer 22.

[0079] Exemplarily, the thickness ratio of the first oxide layer 21 near the bottom of the trench 11 to the second oxide layer 22 is 1 / 4, and the thickness ratio of the first oxide layer 21 near the edge of the trench 11 to the second oxide layer 22 is 2 / 3.

[0080] Exemplarily, the growth thickness of the first oxide layer 21 can be controlled to be 20-40% of the thickness of the gate dielectric layer 2, for example 20%, and it can be ensured that the growth thickness of the second oxide layer 22 is 60-80% of the thickness of the gate dielectric layer 2, for example 80%.

[0081] As Figure 10 shown, in an embodiment of the present application, a semiconductor structure is further provided, and the structure may include:

[0082] A substrate 1 having a trench 11;

[0083] A first oxide layer 21 covering the bottom and side walls of the trench 11, and the thickness of the first oxide layer 21 gradually decreases in the direction close to the bottom.

[0084] In this embodiment, the material of the substrate 1 includes but is not limited to silicon crystal or germanium crystal, silicon-on-insulator (SOI) structure or epitaxial layer structure on silicon, compound semiconductor (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysproside), alloy semiconductor (such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or their combinations).

[0085] In this embodiment, oxide layers with different thicknesses are formed on the side walls and bottom of the trench 11 of the semiconductor structure, and the oxide layers can reduce gate leakage and increase the control ability of the gate. Therefore, the reliability of the semiconductor structure is relatively high, and the production yield is also relatively high.

[0086] In some alternative embodiments of the present application, it may further include: a second oxide layer 22 covering the surface of the first oxide layer 21; a barrier layer 3 covering the surface of the second oxide layer 22; a conductive metal 4 filled in the trench 11, and the conductive metal 4 covering the surface of the second oxide layer 22.

[0087] Among them, the barrier layer 3 can be made of titanium nitride, tantalum nitride, etc. The material of the conductive metal 4 includes but is not limited to metals or metal alloys, such as tungsten, aluminum, copper and their alloys, etc.

[0088] A conductive material is filled in the trench 11 to form a conductive metal 4, and the top end of the conductive metal 4 can be lower than the upper edge of the trench 11.

[0089] As Figure 10As shown, in some alternative embodiments of the present application, in forming the word line structure, trench 11, as the word line trench, and a gate oxide layer is formed within the word line trench. The gate oxide layer may use the oxide layer 2 composed of the first thermal oxide layer 21 and / or the second thermal oxide layer 22 in the present application, which is used for insulation between the gate and the substrate 1. The gate dielectric layer 2 can be formed by thermal oxidation. The gate dielectric layer 2 covers at least the inner sidewalls of the trench 11, and the gate dielectric layer 2 has the same shape as the trench 11. For example, if the trench 11 is U-shaped, then the gate dielectric layer 2 is also U-shaped. In some alternative embodiments of the present application, in this specific embodiment, the gate dielectric layer 2 also extends outward to cover the upper surface of the oxide isolation layer.

[0090] As Figure 11 shown, a barrier layer 3 is formed on the gate dielectric layer 2, and the barrier layer 3 covers at least the inner sidewalls of the gate dielectric layer 2. The shape of the barrier layer 3 is the same as the shape of the gate dielectric layer 2. For example, if the shape of the gate dielectric layer 2 is U-shaped, then the shape of the barrier layer 3 is also U-shaped. The material of the barrier layer 3 includes but is not limited to metal nitrides, such as titanium nitride or tantalum nitride. In this specific embodiment, in addition to covering the inner sidewalls of the gate dielectric layer 2, the barrier layer 3 also covers the upper surface of the gate dielectric layer 2.

[0091] As Figure 11 shown, a conductive metal 4 is formed on the barrier layer 3, and the conductive metal 4 at least fills the trench 11. The material of the conductive metal 4 includes but is not limited to metals or metal alloys, such as tungsten, aluminum, copper, and their alloys. After this step is completed, the conductive metal 4 is formed on the barrier layer 3, and the conductive metal 4 at least fills the trench 11, that is, the conductive metal 4 fills the voids formed by the inner sidewalls of the barrier layer 3. In this specific embodiment, the conductive metal 4 not only fills the voids formed by the inner sidewalls of the barrier layer 3 but also covers the upper surface of the barrier layer 3.

[0092] As Figure 12 shown, part of the conductive metal 4 and the barrier layer 3 are etched away, and only part of the conductive metal 4 and the barrier layer 3 located within the trench 11 are retained. After this step is performed, the top of the conductive metal 4 is lower than the upper edge of the trench 11. In this specific embodiment, the top of the barrier layer 3 is lower than the top of the conductive metal 4. In other specific embodiments, the top of the barrier layer 3 may also be flush with the top of the conductive metal 4, or the top of the barrier layer 3 may be higher than the top of the conductive metal 4.

[0093] In this embodiment, the conductive metal 4 can be etched multiple times to make the top end of the conductive metal 4 have a stepped configuration with a higher middle and lower sides. Specifically, the conductive metal 4 is etched multiple times in a direction perpendicular to the top end of the conductive metal 4 to make the top end of the conductive metal 4 have a stepped configuration with a higher middle and lower sides. One way to make the top end of the conductive metal 4 have a stepped configuration with a higher middle and lower sides is to etch the conductive metal 4 multiple times from the edge of the top end of the conductive layer towards the center of the top end of the conductive layer, so that the top end of the conductive metal 4 has a stepped configuration with a higher middle and lower sides. Compared with the existing word line structure with a flat top configuration, the top end of the stepped word line structure is higher than that of the existing word line structure, increasing the area of the word line structure, reducing the resistance of the word line structure, increasing the control ability of the gate over the channel, and improving the ability of the transistor to drive current. In the direction perpendicular to the top end of the word line structure, although the distance from the highest point of the top end of the stepped word line structure to the drain decreases, with the stepped configuration, the distance between the highest point of its top end and the drain in the direction parallel to the top end of the word line structure does not decrease much and is not sufficient to generate leakage current. That is to say, the stepped word line structure can reduce the resistance of the word line structure while avoiding the generation of the GIDL effect.

[0094] The semiconductor structure of this embodiment can be used as the word line structure of the finally obtained semiconductor device. A dense oxide layer is formed on the sidewalls and bottom of the trench 11. The thickness of the gate oxide layer gradually decreases from the edge of the word line trench towards the bottom of the word line trench, so that the gate oxide layer inside the word line trench has a stepped coverage. Since the gate oxide layers with different thicknesses are formed on the sidewalls and bottom of the word line trench, the thicker sidewalls can reduce gate leakage, and the thinner bottom can enhance the control ability of the gate. Therefore, this method can improve the reliability of the semiconductor structure and the product yield.

[0095] Of course, in some other embodiments, the oxide layer disclosed in the embodiments of the present application can also be used as other dielectric materials, such as the filling material and blocking material of the isolation trench. Any oxide layer formed in the trench should be covered within the scope claimed in the present application. The oxide layer of the present application can improve the etching defects on the sidewalls of the trench.

[0096] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them belong to the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that, Including: Providing a substrate; Forming a groove in the substrate; Under an environment with a pressure of 500 - 800 Torr, performing a first thermal oxidation reaction to form a first oxide layer on the bottom and side walls of the groove, and the thickness of the first oxide layer gradually decreases along the direction close to the bottom; On the first oxide layer, performing a second thermal oxidation reaction under a preset pressure to form a second oxide layer, and the preset pressure is less than the reaction pressure of the first thermal oxidation reaction; the range of the thickness ratio of the first oxide layer to the second oxide layer is 1 / 4 to 2 / 3.

2. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The reaction temperature of the first thermal oxidation reaction is 800 - 1100 degrees Celsius.

3. The method for preparing a semiconductor structure according to claim 1, wherein, The gases for the first thermal oxidation reaction include: O2, H2, and N2; Wherein, the flow rate ratio of H2 to N2 satisfies the following formula: Q H2 <4% * Q H2 / (Q N2 + Q H2 ); Among them, Q H2 is the flow rate of H2 introduced for the first thermal oxidation reaction, and Q N2 is the flow rate of N2 introduced for the first thermal oxidation reaction.

4. The method for preparing a semiconductor structure according to claim 1, wherein The gases for the first thermal oxidation reaction include: O2, H2, and an inert gas; Wherein, the flow rate ratio of H2 to the inert gas satisfies the following formula: Q H2 <3% * Q H2 / (Q 惰 + Q H2 ); Among them, Q H2 is the flow rate of the H2 introduced for the first thermal oxidation reaction, and Q 惰 is the flow rate of the inert gas introduced for the first thermal oxidation reaction.

5. The method for preparing a semiconductor structure according to claim 1, wherein The preparation method further includes: annealing the first oxide layer.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein, The preset pressure is 0 - 20 Torr.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein, The reaction temperature of the second thermal oxidation reaction is 800 - 1100 degrees Celsius.

8. The method for preparing a semiconductor structure according to claim 6, wherein The preset pressure is 5 - 10 Torr.

9. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The gases for the second thermal oxidation reaction include an oxygen-containing gas and H2.

10. The manufacturing method of the semiconductor structure according to claim 9, characterized in that, The flow rate ratio of H2 to the oxygen-containing gas satisfies the following formula: Q H2 <30% * Q H2 / (Q 含 + Q H2 ); Among them, Q H2 is the flow rate of H2 introduced for the second thermal oxidation reaction, and the Q 含 is the flow rate of the oxygen-containing gas introduced for the second thermal oxidation reaction.

11. The method for preparing a semiconductor structure according to claim 1, wherein The preparation method further includes: Forming a barrier layer on the surface of the second oxide layer; Filling the groove with a conductive metal, and the conductive metal covers the surface of the barrier layer.

12. A semiconductor structure, characterized in that, Including: A substrate having a groove; A first oxide layer covering the bottom and side walls of the groove, and the thickness of the first oxide layer gradually decreases along the direction close to the bottom; a second oxide layer located on the first oxide layer, and the range of the thickness ratio of the first oxide layer to the second oxide layer is 1 / 4 to 2 / 3.

13. The semiconductor structure according to claim 12, wherein Further including: A barrier layer covering the surface of the second oxide layer; A conductive metal filled in the groove, and the conductive metal covers the surface of the barrier layer.

14. The semiconductor structure according to claim 13, wherein, The first oxide layer and the second oxide layer serve as a gate dielectric layer.

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