Method for preparing semiconductor structure and semiconductor structure

Abstract

An embodiment of the present application provides a method for fabricating a semiconductor structure and a semiconductor structure, relating to the field of semiconductor technology. The method includes: providing a substrate; etching the substrate to form a plurality of bit line grooves extending in a first direction in the substrate; sequentially forming a first isolation layer, a bit line metal line layer, a bit line conductive connection layer, and a first insulating layer in the plurality of bit line grooves to obtain a bit line structure; etching the substrate on which the bit line structure is formed to obtain a plurality of spaced-apart active region structures and a first groove; wherein the bit line structure intersects the plurality of active region structures respectively; filling a second isolation layer in the first groove to obtain a first structure; etching the first structure to form a plurality of word line grooves extending in a direction perpendicular to the first direction in the first structure; sequentially forming a third isolation layer, a word line conductive connection layer, and a second insulating layer in the plurality of word line grooves. Thus, the performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a method for fabricating a semiconductor structure and a semiconductor structure. Background Art

[0002] A dynamic random access memory (DRAM) is a semiconductor memory that writes and reads data rapidly and randomly, and is widely applied to data storage devices or apparatuses. The dynamic random access memory is composed of multiple repetitive memory cells. Each memory cell includes a capacitive structure and a transistor. The gate of the transistor is connected to a word line, the drain is connected to a bit line, and the source is connected to the capacitive structure. The voltage signal on the word line can control the opening or closing of the transistor. Further, data information stored in the capacitive structure is read through the bit line, or data information is written into the capacitive structure through the bit line for storage.

[0003] In related technologies, in the process of fabricating a semiconductor structure, a word line is fabricated first to obtain a word line structure. Further, multiple layers are deposited on the word line structure, and a bit line is formed by performing multiple etching operations on the multiple layers. However, performing multiple etching operations on the multiple layers can cause the formed bit line to be narrow at the top and wide at the bottom, reducing the performance of the semiconductor structure. Summary of the Invention

[0004] According to some embodiments, a first aspect of this application provides a method for fabricating a semiconductor structure to improve the performance of the semiconductor structure. The specific technical solution is as follows:

[0005] Provide a substrate;

[0006] Etch the substrate to form a plurality of bit line grooves extending along a first direction in the substrate;

[0007] Successively form a first isolation layer, a bit line metal wire layer, a bit line conductive connection layer, and a first insulating layer in the plurality of bit line grooves to obtain a bit line structure;

[0008] Etch the substrate forming the bit line structure to obtain a plurality of spaced-apart active region structures and a first groove; wherein, the bit line structures respectively intersect with the plurality of active region structures;

[0009] Fill a second isolation layer in the first groove to obtain a first structure;

[0010] Etch the first structure to form a plurality of word line grooves extending along a vertical direction perpendicular to the first direction in the first structure;

[0011] Successively form a third isolation layer, a word line conductive connection layer, and a second insulating layer in the plurality of word line grooves.

[0012] In a possible implementation manner, the first isolation layer includes a first sub-isolation layer and a second sub-isolation layer;

[0013] Forming a first isolation layer, a bit line metal wire layer, a bit line conductive connection layer, and a first insulating layer in sequence in the plurality of bit line grooves to obtain a bit line structure, including:

[0014] Depositing a first sub-isolation layer at the bottoms of the plurality of bit line grooves;

[0015] Depositing a second sub-isolation layer at the bottoms and sidewalls of the plurality of bit line grooves where the first sub-isolation layer is formed;

[0016] Depositing a barrier layer at the bottoms and sidewalls of the plurality of bit line grooves where the second sub-isolation layer is formed;

[0017] Depositing a bit line metal wire material layer in the plurality of bit line grooves where the barrier layer is formed;

[0018] Etching back the barrier layer and the bit line metal wire material layer to obtain a bit line metal wire layer;

[0019] Depositing a bit line conductive connection layer in the plurality of bit line grooves where the bit line metal wire layer is formed;

[0020] Depositing a first insulating layer in the plurality of bit line grooves where the bit line conductive connection layer is formed to obtain a bit line structure.

[0021] In a possible implementation manner, the word line grooves include a first word line groove, a second word line groove, and a third word line groove;

[0022] Etching the first structure to form a plurality of word line grooves extending in the vertical direction along the first direction in the first structure, including:

[0023] Etching the active region structure to form a first word line groove;

[0024] Etching the second isolation layer to form a second word line groove;

[0025] Etching the bit line structure to form a third word line groove;

[0026] The bottom surface of the first word line groove is lower than the bottom surfaces of the second word line groove and the third word line groove.

[0027] In a possible implementation manner, the bottom surface of the third word line groove is flush with or higher than the upper surface of the bit line metal layer;

[0028] The upper surface of the word line conductive connection layer is higher than the bottom surfaces of the second word line groove and the third word line groove.

[0029] In a possible implementation, etching the first structure to form a plurality of word line grooves extending in a vertical direction along the first direction in the first structure includes:

[0030] Etching the first structure to form a plurality of second grooves extending in a vertical direction along the first direction in the first structure, wherein a bottom surface of the second groove is flush with a lower surface of the bit line conductive connection layer;

[0031] Etching a portion of the active region structure corresponding to the second groove to a first position to form a plurality of word line grooves in the first structure, wherein a bottom surface of the word line groove corresponding to the active region structure is lower than a bottom surface of the word line groove corresponding to the second isolation layer and the bit line structure.

[0032] In a possible implementation, etching the substrate to form a plurality of bit line grooves extending in a first direction in the substrate includes:

[0033] Forming a first mask layer on the substrate; wherein, the first mask layer includes a plurality of first mask strips extending in a first direction, and the plurality of first mask strips are parallel to each other;

[0034] Etching the substrate covered by the first mask layer to form a plurality of bit line grooves extending in the first direction in the substrate.

[0035] In a possible implementation, etching the substrate forming the bit line structure to obtain a plurality of spaced-apart active region structures and first grooves includes:

[0036] Forming a second mask layer on the substrate forming the bit line structure;

[0037] Etching the substrate forming the bit line structure covered by the second mask layer to obtain a plurality of spaced-apart active region structures and first grooves;

[0038] Wherein, the second mask layer includes a plurality of spaced-apart second mask strips, and regions of each second mask strip respectively intersect with a region of a bit line structure.

[0039] In a possible implementation, before etching the substrate forming the bit line structure covered by the second mask layer to obtain a plurality of spaced-apart active region structures and first grooves, the method further includes:

[0040] Providing a third mask layer, the third mask layer includes a plurality of third mask strips extending in a second direction, and the plurality of third mask strips are parallel to each other;

[0041] Cut each of the third mask strips into a plurality of second mask strips with a preset length.

[0042] In a possible implementation manner, the included angle between the first direction and the second direction is 15° to 30°.

[0043] In a possible implementation manner, forming a third isolation layer, a word line conductive connection layer, and a second insulating layer in the plurality of word line grooves in sequence includes:

[0044] Deposit a third isolation layer on the bottoms and side walls of the plurality of word line grooves.

[0045] Deposit a first sub-word line conductive connection layer on the bottoms and side walls of the plurality of word line grooves where the third isolation layer is formed.

[0046] Deposit a second sub-word line conductive connection layer in the plurality of word line grooves where the first sub-word line conductive connection layer is formed.

[0047] Etch back the first sub-word line conductive connection layer and the second sub-word line conductive connection layer to a second position above the bit line metal line layer to form a word line conductive connection layer.

[0048] Deposit a second insulating layer in the plurality of word line grooves where the word line conductive connection layer is formed.

[0049] In a possible implementation manner, the second position is lower than the midpoint of the bit line conductive connection layer and higher than the lower surface of the bit line conductive connection layer.

[0050] According to some embodiments, a second aspect of the present application provides a semiconductor structure, and the semiconductor structure includes:

[0051] A substrate, the substrate includes a plurality of active region structures arranged at intervals;

[0052] A plurality of bit line structures extending in a first direction formed in the substrate, each bit line structure includes a first isolation layer, a bit line metal line layer, a bit line conductive connection layer, and a first insulating layer sequentially distributed from bottom to top, and the bit line structures respectively intersect with a plurality of active region structures;

[0053] A second isolation layer is arranged between the bit line structures;

[0054] A plurality of word line structures extending in a direction perpendicular to the first direction formed in the substrate, each word line structure includes a third isolation layer, a word line conductive connection layer, and a second insulating layer sequentially distributed from bottom to top.

[0055] In a possible implementation manner, each word line structure includes: a first part corresponding to the active region structure, a second part corresponding to the second isolation layer, and a third part corresponding to the bit line structure;

[0056] The lower surface of the first part is lower than the lower surfaces of the second part and the third part.

[0057] In a possible implementation manner, the lower surface of the third part is flush with or higher than the upper surface of the bit line metal layer;

[0058] The upper surface of the word line conductive connection layer is higher than the lower surfaces of the second part and the third part.

[0059] In a possible implementation manner, the upper surface of the word line conductive connection layer is lower than the midpoint of the bit line conductive connection layer and higher than the lower surface of the bit line conductive connection layer.

[0060] In a possible implementation manner, the included angle between the bit line structure and the active region structure is 15° to 30°.

[0061] Advantageous effects of embodiments of the present application:

[0062] The method for preparing a semiconductor structure provided by an embodiment of the present application includes: providing a substrate; etching the substrate to form a plurality of bit line grooves extending along a first direction in the substrate; sequentially forming a first isolation layer, a bit line metal wire layer, a bit line conductive connection layer, and a first insulating layer in the plurality of bit line grooves to obtain a bit line structure; etching the substrate on which the bit line structure is formed to obtain a plurality of spaced-apart active region structures and a first groove; wherein, the bit line structure intersects with the plurality of active region structures respectively; filling a second isolation layer in the first groove to obtain a first structure; etching the first structure to form a plurality of word line grooves extending along a vertical direction perpendicular to the first direction in the first structure; sequentially forming a third isolation layer, a word line conductive connection layer, and a second insulating layer in the plurality of word line grooves.

[0063] Based on the above processing, the bit line is obtained by depositing corresponding materials in the bit line groove, and it is not necessary to form the bit line through multiple etching processes. Furthermore, the situation where the upper part of the bit line is narrow and the lower part is wide caused by multiple etching processes in the related art can be avoided, and the performance of the semiconductor structure can be improved.

[0064] Of course, it is not necessary for any product or method implementing the present application to achieve all the above advantages simultaneously. Description of the Drawings

[0065] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other embodiments can also be obtained based on these drawings.

[0066] Figure 1 Schematic diagram of the structure obtained by etching the layer to be processed in the related art;

[0067] Figure 2 Flowchart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0068] Figure 3 Schematic diagram of a structure including a first mask bar provided in an embodiment of the present application;

[0069] Figure 4 Schematic diagram of a substrate for forming a bit line structure provided in an embodiment of the present application;

[0070] Figure 5 Schematic diagram of a structure including an active region structure and a first groove provided in an embodiment of the present application;

[0071] Figure 6 Schematic diagram of a structure including a third mask bar provided in an embodiment of the present application;

[0072] Figure 7 For Figure 6 Schematic diagram of cutting the third mask bar in the structure shown;

[0073] Figure 8 For Figure 6 Another schematic diagram of cutting the third mask bar in the structure shown;

[0074] Figure 9 Based on the second mask bar, for Figure 6 Schematic diagram of the structure obtained by etching the structure shown;

[0075] Figure 10 For Figure 5 Schematic diagram of the structure obtained by filling the first groove in the structure shown;

[0076] Figure 11 For Figure 10 Top view of the structure obtained by forming a fourth mask bar on the first structure shown;

[0077] Figure 12A For Figure 11 Schematic diagram of the Y2 cross-section of the second structure obtained by etching the structure shown;

[0078] Figure 12B Schematic diagram of the Y1 cross-section of the second structure obtained by etching the structure shown Figure 11 ;

[0079] Figure 12C Schematic diagram of the X cross-section of the second structure obtained by etching the structure shown Figure 11 ;

[0080] Figure 13A Schematic diagram of the Y2 cross-section of the third structure obtained by etching the structure shown Figure 11 ;

[0081] Figure 13B Schematic diagram of the Y1 cross-section of the third structure obtained by etching the structure shown Figure 11 ;

[0082] Figure 13C Schematic diagram of the X cross-section of the third structure obtained by etching the structure shown Figure 11 ;

[0083] Figure 14 Top view of the third structure obtained based on the structure shown Figure 11 ;

[0084] Figure 15A Schematic diagram of the Y2 cross-section of the fourth structure obtained based on the structure shown Figure 14 ;

[0085] Figure 15B Schematic diagram of the Y1 cross-section of the fourth structure obtained based on the structure shown Figure 14 ;

[0086] Figure 15C Schematic diagram of the X cross-section of the fourth structure obtained based on the structure shown Figure 14 ;

[0087] Figure 16A Schematic diagram of the Y2 cross-section of the target structure obtained based on the structure shown Figure 14 ;

[0088] Figure 16B Schematic diagram of the Y1 cross-section of the target structure obtained based on the structure shown Figure 14 ;

[0089] Figure 16C Schematic diagram of the X cross-section of the target structure obtained based on the structure shown Figure 14 ;

[0090] Reference numerals:

[0091] 10: Substrate; 11: First mask strip

[0092] 12: The first isolation layer; 121: The first sub-isolation layer;

[0093] 121: The second sub-isolation layer; 13: The barrier layer;

[0094] 14: The bit line metal wire material layer; 15: The bit line conductive connection layer;

[0095] 16: The first insulating layer; 17: The active region structure;

[0096] 18: The third mask bar; 19: The first isolation structure;

[0097] 20: The second mask bar; 21: The second isolation structure;

[0098] 22: The second isolation layer; 23: The fourth mask bar;

[0099] 24: The second groove; 25: The word line groove;

[0100] 26: The third isolation layer; 27: The word line conductive connection layer;

[0101] 271: The first sub-word line conductive connection layer; 272: The second sub-word line conductive connection layer;

[0102] 28: The second insulating layer. Detailed implementation manners

[0103] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art based on the present application belong to the scope of protection of the present application.

[0104] In the related art, in the process of fabricating a semiconductor structure, the word line is first fabricated to obtain a word line structure. Then, multiple layers (which can be referred to as layers to be processed) are deposited on the word line structure, and the bit line is formed by performing multiple etching operations on the layers to be processed. However, performing multiple etching operations on the layers to be processed will result in the bit line having a narrow upper part and a wide lower part, reducing the performance of the semiconductor structure.

[0105] For example, refer to Figure 1 , Figure 1 which is a schematic diagram of the structure obtained by etching the layers to be processed in the related art. Figure 1 The upper part of the shown structure is the bit line formed by multiple etching operations. Since the etching is performed from top to bottom, it is easy to cause the position near the top in the layer to be processed to be etched more than the position near the bottom in the layer to be processed, resulting in the bit line having a narrow upper part and a wide lower part, reducing the performance of the semiconductor structure.

[0106] In view of the above technical problems, in an embodiment of the present application, a method for preparing a semiconductor structure is provided. Refer to Figure 2 , Figure 2 which is a flowchart of a method for preparing a semiconductor structure provided in an embodiment of the present application. The method may include the following steps:

[0107] S201: Provide a substrate.

[0108] S202: Etch the substrate to form a plurality of bit line grooves extending in a first direction in the substrate.

[0109] S203: Sequentially form a first isolation layer, a bit line metal layer, a bit line conductive connection layer, and a first insulating layer in the plurality of bit line grooves to obtain a bit line structure.

[0110] S204: Etch the substrate forming the bit line structure to obtain a plurality of spaced-apart active region structures and a first groove.

[0111] Wherein, the bit line structures respectively intersect with the plurality of active region structures.

[0112] S205: Fill a second isolation layer in the first groove to obtain a first structure.

[0113] S206: Etch the first structure to form a plurality of word line grooves extending in a direction perpendicular to the first direction in the first structure.

[0114] S207: Sequentially form a third isolation layer, a word line conductive connection layer, and a second insulating layer in the plurality of word line grooves.

[0115] Based on the method for preparing a semiconductor structure provided in the embodiment of the present application, a bit line is obtained by depositing corresponding materials in the bit line groove, without the need to form the bit line through multiple etching steps. Furthermore, it is possible to avoid the situation where the bit line is narrow at the top and wide at the bottom caused by multiple etching steps in the related art, and the performance of the semiconductor structure can be improved.

[0116] Secondly, refer to Figure 1 , since the bit line obtained in the related art is a protruding part in the structure, during the etching process, it is easy for the protruding part to collapse, reducing the stability of the semiconductor structure. However, based on the method for preparing a semiconductor structure provided in the embodiment of the present application, a bit line is obtained by depositing corresponding materials in the bit line groove, and the obtained bit line is not a protruding part in the structure. Furthermore, the situation where the bit line collapses in the related art can be avoided, and the stability of the semiconductor structure can be improved.

[0117] For the above step S201, the support component with a semiconductor structure as the substrate is used to support other components disposed thereon. The substrate can be made of semiconductor materials. For example, the substrate can be silicon, germanium, silicon-germanium compound, or silicon-carbon compound, but is not limited thereto.

[0118] In one embodiment, the above step S202 may include:

[0119] Form a first mask layer on the substrate; etch the substrate covered by the first mask layer to form a plurality of bit line grooves extending in a first direction in the substrate.

[0120] Among them, the first mask layer includes a plurality of first mask strips extending in the first direction, and the plurality of first mask strips are parallel to each other.

[0121] Exemplarily, referring to Figure 3 , Figure 3 , in [reference figure], the first mask strip 11 is located above the substrate 10, and the first mask strip 11 can be a strip-shaped mask strip.

[0122] In one implementation manner, a mask material layer is formed above the substrate 10. The mask material layer can be a photoresist layer. After the photoresist layer is exposed or developed, a first mask layer including a plurality of first mask strips 11 is formed. Etch the part of the substrate 10 exposed by the first mask layer. Furthermore, a plurality of grooves (i.e., the bit line grooves in the embodiments of the present application, not marked in the figure) can be formed in the substrate 10. The shape of the projection of the bit line grooves on the upper surface of the substrate is the same as the shape of the projection of the opening between adjacent first mask strips 11 on the upper surface of the substrate.

[0123] In one implementation manner, before forming the bit line grooves based on the first mask strip 11, an isolation layer (which can be called the fourth isolation layer, not marked in the figure) can also be deposited on the substrate 10. For example, the material of the fourth isolation layer can be silicon nitride, or it can also be silicon oxide, or it can also be silicon oxynitride, but is not limited thereto. Furthermore, the substrate 10 is etched with the first mask strip 11 as a mask above the fourth isolation layer. Based on this, when etching the substrate 10, the top of the substrate 10 can be protected by the fourth isolation layer.

[0124] For the above step S203, the first isolation layer is used to isolate the bit line metal line layer from the substrate 10. The obtained plurality of bit line structures form bit lines. The material of the bit line conductive connection layer can be doped polysilicon, that is, obtained by doping conductive particles in polysilicon. For example, it can be polysilicon doped with boron particles, or it can also be polysilicon doped with phosphorus particles. The doping can be achieved by means such as diffusion and ion implantation.

[0125] The first insulating layer is used to protect the formed bit lines from oxidation. The material of the first insulating layer can be silicon nitride, or it can also be silicon oxide, or it can also be silicon oxynitride, but it is not limited thereto.

[0126] In addition, after sequentially forming a first isolation layer, a bit line metal layer, a bit line conductive connection layer, and a first insulating layer in the bit line grooves, the upper surface of the formed structure is planarized to obtain a bit line structure.

[0127] In one implementation, referring to Figure 4 , Figure 4 is a schematic diagram of a substrate for forming a bit line structure provided by an embodiment of the present application. The first isolation layer 12 includes a first sub-isolation layer 121 and a second sub-isolation layer 122.

[0128] Correspondingly, the above step S203 may include the following steps:

[0129] Step 1: Deposit the first sub-isolation layer 121 at the bottoms of a plurality of bit line grooves.

[0130] Step 2: Deposit the second sub-isolation layer 122 at the bottoms and sidewalls of the plurality of bit line grooves where the first sub-isolation layer 121 is formed.

[0131] Step 3: Deposit a barrier layer 13 at the bottoms and sidewalls of the plurality of bit line grooves where the second sub-isolation layer 122 is formed.

[0132] Step 4: Deposit a bit line metal layer material layer 14 in the plurality of bit line grooves where the barrier layer 13 is formed.

[0133] Step 5: Etch back the barrier layer 13 and the bit line metal layer material layer 14 to obtain a bit line metal layer.

[0134] Step 6: Deposit a bit line conductive connection layer 15 in the plurality of bit line grooves where the bit line metal layer is formed.

[0135] Step 7: Deposit a first insulating layer 16 in the plurality of bit line grooves where the bit line conductive connection layer 15 is formed to obtain a bit line structure.

[0136] In the embodiment of the present application, referring to Figure 4 , after forming the bit line grooves, deposit the first sub-isolation layer 121 at the bottoms of the plurality of bit line grooves. The material of the first sub-isolation layer 121 can be silicon nitride, or it can also be silicon oxide, or it can also be silicon oxynitride, but it is not limited thereto.

[0137] Furthermore, deposit the second sub-isolation layer 122 above and on the sidewalls of the first sub-isolation layer 121 in the bit line grooves. The material of the second sub-isolation layer 122 can be silicon nitride, or it can also be silicon oxide, or it can also be silicon oxynitride, but it is not limited thereto.

[0138] Then, a barrier layer 13 is deposited on the upper surface and sidewalls of the second sub-isolation layer 122 formed in the bit line groove. The material of the barrier layer 13 can be titanium nitride, or it can also be cobalt, but it is not limited thereto. The barrier layer 13 is used to isolate the bit line metal line material layer and prevent the bit line metal line material layer from contaminating the substrate.

[0139] Then, the remaining space in the bit line groove is filled with the bit line metal line material layer 14. The material of the bit line metal line material layer 14 can be tungsten, or it can also be cobalt silicide, or it can also be titanium, but it is not limited thereto.

[0140] In addition, after filling the bit line metal line material layer 14, the barrier layer 13 and the bit line metal line material layer 14 are subjected to row back-etching, that is, etched to a specified position. The etched barrier layer 13 and bit line metal line material layer 14 form the bit line metal line layer. Among them, the specified position can be determined by those skilled in the art according to the size of the semiconductor structure and actual manufacturing requirements. When performing back-etching on the barrier layer 13 and the bit line metal line material layer 14, the second sub-isolation layer 122 is also back-etched.

[0141] Furthermore, a bit line conductive connection layer 15 is deposited on the upper surface of the bit line metal line layer formed in the bit line groove, and then a first insulating layer 16 is deposited on the upper surface of the bit line conductive connection layer 15.

[0142] In one implementation, the above step S204 may include the following steps:

[0143] A second mask layer is formed on the substrate 10 for forming the bit line structure; the substrate 10 for forming the bit line structure covered by the second mask layer is etched to obtain a plurality of spaced-apart active region structures and a first groove.

[0144] Among them, the second mask layer includes a plurality of spaced-apart second mask strips, and the regions of each second mask strip respectively intersect with the region of a bit line structure.

[0145] See Figure 5 , Figure 5 which is a schematic diagram of a structure including an active region structure and a first groove provided by an embodiment of the present application.

[0146] Figure 5 The structure of Figure 5 includes a plurality of spaced-apart active region structures 17. In

[0147] In one implementation, based on the second mask strip, the regions other than the regions corresponding to the above-mentioned active region structure 17 and the bit line structure can be etched to obtain a first groove. Subsequently, an insulating material is filled in the first groove to form insulation between the active region structures 17 in the substrate 10. The active region structure 17 is used to arrange transistors or other components.

[0148] In one embodiment, before the above step S204, the method may further include the following steps:

[0149] Step 1: Provide a third mask layer.

[0150] The third mask layer includes a plurality of third mask strips extending along the second direction, and the plurality of third mask strips are parallel to each other.

[0151] Step 2: Cut each third mask strip into a plurality of second mask strips with a preset length.

[0152] In one embodiment, the included angle between the first direction and the second direction is 15° to 30°. Exemplarily, the included angle between the first direction and the second direction can be 21°.

[0153] In the embodiments of the present application, referring to Figure 6 , Figure 6 in, the third mask strip 18 can be a plurality of strip-shaped mask strips.

[0154] In one implementation, after obtaining the bit line structure and before forming the first groove, an isolation layer (which can be called the fifth isolation layer) is deposited on the bit line structure. For example, the material of the fifth isolation layer can be silicon nitride, or it can also be silicon oxide, or it can also be silicon oxynitride, but it is not limited thereto. Then, the regions other than the regions corresponding to the third mask strip 18 in the fifth isolation layer are etched to obtain Figure 6 the structure shown. Figure 6 The etched part of the fifth isolation layer in

[0155] can be called the first isolation structure 19.

[0156] Then, the plurality of third mask strips 18 are cut. That is, for each third mask strip 18, the third mask strip 18 is cut into a plurality of mask strips with a preset length (i.e., the second mask strips in the embodiments of the present application).

[0156] For example, referring to Figure 7 and Figure 8 , Figure 7 and Figure 8 are schematic diagrams of cutting the third mask strip 18 shown in Figure 6 .

[0157] In one implementation, based on Figure 7The method shown cuts the third mask bar 18 to obtain a plurality of mask bars. Figure 7 The white dots in Figure 8 indicate the cutting positions. Then, based on Figure 7 the method shown, the obtained mask bars are further cut. Figure 8 The gray dots in Figure 9 indicate the cutting positions. Based on the above processing, a plurality of mask bars with a preset length can be obtained. Refer to

[0158] Based on Figure 9 the second mask bar 20 in Figure 9 the first isolation structure 19 is etched until reaching the upper surface of the bit line structure, forming a second isolation structure 21, and obtaining Figure 9 the structure shown in

[0159] In the related art, before forming the bit line, the above small island-like structure is first formed. Further, a cavity is formed in the center of the small island-like structure, and doped polysilicon is deposited through the cavity to form BLC (Bit Line Coupling), resulting in a cumbersome preparation process; while based on the semiconductor preparation method provided in the embodiments of the present application, when forming the bit line, doped polysilicon is directly deposited first to form BLC, and there is no need to form a cavity in the above small island-like structure, which can simplify the operation.

[0160] The area of the substrate 10 other than the area of the second mask bar 20 is etched to form a first groove. And the upper small island-like structure is removed to obtain Figure 5 the structure shown in

[0161] Regarding step S205, in one embodiment, on the basis of Figure 9 , a second isolation layer 22 is filled in the first groove to obtain Figure 10 the structure shown (i.e., the first structure in the embodiments of the present application). The second isolation layer 22 can be silicon nitride, or it can also be silicon oxide, or it can also be silicon oxynitride, but it is not limited thereto.

[0162] Regarding step S206, the word line groove can include multiple parts, that is, the part corresponding to the active region structure 17 (i.e., the first word line groove), the part corresponding to the second isolation layer 22 (i.e., the second word line groove), and the part corresponding to the bit line structure (i.e., the third word line groove).

[0163] In one implementation, the bottom surface of the first word line groove is lower than the bottom surfaces of the second word line groove and the third word line groove. In this way, the depth of the word line groove in the active region structure 17 is deeper than that in the isolation region, which can reduce the cross-sectional area of the word lines in the non-active region, thereby reducing the parasitic capacitance between word lines and between word lines and bit lines, and effectively preventing RowHammer attacks.

[0164] Correspondingly, at least the following two different methods can be used to form the above-mentioned word line grooves:

[0165] Method 1: The above step S206 includes: etching the active region structure 17 to form the first word line groove; etching the second isolation layer 22 to form the second word line groove; etching the bit line structure to form the third word line groove.

[0166] That is, the corresponding parts of the active region structure 17, the second isolation layer 22, and the bit line structure are etched respectively, and etched to different positions, so that the bottom surface of the first word line groove is lower than the bottom surfaces of the second word line groove and the third word line groove.

[0167] Method 2: The above step S206 includes: etching the first structure to form a plurality of second grooves extending in the vertical direction along the first direction in the first structure, and the bottom surface of the second groove is flush with the bottom surface of the bit line conductive connection layer 15; etching the corresponding part of the active region structure 17 in the second groove to the first position to form a plurality of word line grooves in the first structure, and the bottom surface of the word line groove corresponding to the active region structure 17 is lower than the bottom surfaces of the word line grooves corresponding to the second isolation layer 22 and the bit line structure.

[0168] That is, the corresponding parts of the active region structure 17, the second isolation layer 22, and the bit line structure are etched simultaneously to the lower surface of the bit line conductive connection layer 15.

[0169] Then, for the corresponding part of the active region structure 17, continue to etch to the first position, so that the bottom surface of the word line groove corresponding to the active region structure 17 is lower than the bottom surfaces of the word line grooves corresponding to the second isolation layer 22 and the bit line structure.

[0170] In one embodiment, the bottom surface of the third word line groove is flush with or higher than the upper surface of the bit line metal layer. Furthermore, it can reduce the relative area between the bit line and the word line, avoid excessive parasitic capacitance, and ensure that the word line is continuous.

[0171] In one implementation, refer to Figure 11 , Figure 11 is the top view of the structure obtained by forming the fourth mask bar on the first structure shown in Figure 10 . Figure 11In [the figure], the fourth mask strip 23 is a strip-shaped mask strip, perpendicular to the first insulating layer 16, that is, perpendicular to the first direction.

[0172] Using the fourth mask strip 23 as a mask, etch the first structure below the fourth mask strip 23 to form a plurality of grooves (i.e., the word line grooves in the embodiments of the present application). The shape of the word line grooves is consistent with the shape of the fourth mask strip 23.

[0173] It can be seen from Figure 11 that the word line grooves include a groove portion formed by etching the active region structure 17, a groove portion formed by etching the second isolation layer 22, and a groove portion formed by etching the bit line structure. Figure 11 In [the figure], X, Y1, and Y2 represent three cross-sections.

[0174] For example, referring to Figure 12A , Figure 12A is a schematic diagram of the Y2 cross-section of the second structure obtained by etching the first structure shown in Figure 11 . Figure 12A In [the figure], a plurality of second grooves 24 are formed. The second grooves 24 include a groove portion formed by etching the active region structure 17, a groove portion formed by etching the second isolation layer 22, and a groove portion formed by etching the bit line structure.

[0175] Correspondingly, referring to Figure 12B , Figure 12B is a schematic diagram of the Y1 cross-section of the second structure obtained by etching the first structure shown in Figure 11 .

[0176] Referring to Figure 12C , Figure 12C is a schematic diagram of the X cross-section of the second structure obtained by etching the first structure shown in Figure 11 .

[0177] Then, determine the portion of the active region structure 17 corresponding to the plurality of second grooves 24, that is, determine the second grooves 24 formed by etching the active region structure 17. Furthermore, continue to etch the portion of the second grooves 24 corresponding to the active region structure 17 to the first position to obtain the structure for forming the word line grooves (which can be called the third structure). The first position is higher than the bottom of the substrate 10.

[0178] Referring to Figure 13A , Figure 13A is a schematic diagram of the Y2 cross-section of the third structure obtained by etching the first structure shown in Figure 11 . Figure 13A In [the figure], the depth of the word line groove 25 in the active region structure 17 is greater than the depth of the word line groove 25 in the second isolation layer 22.

[0179] Correspondingly, refer to Figure 13B , Figure 13B for a schematic diagram of the Y1 cross-section of the third structure obtained by etching the first structure shown in Figure 11 .

[0180] Refer to Figure 13C , Figure 13C for a schematic diagram of the X cross-section of the third structure obtained by etching the first structure shown in Figure 11 .

[0181] Based on the above processing, making the depth of the word line grooves in the active region structure deeper than that in the isolation region can reduce the cross-sectional area of the word lines in the non-active region, thereby reducing the parasitic capacitance between the word lines and between the word lines and the bit lines, and effectively preventing hammering attacks.

[0182] In one embodiment, the above step S207 may include the following steps:

[0183] Step 1: Deposit a third isolation layer 26 on the bottom and side walls of a plurality of word line grooves 25.

[0184] Step 2: Deposit a first sub-word line conductive connection layer 271 on the bottom and side walls of the plurality of word line grooves 25 where the third isolation layer 26 is formed.

[0185] Step 3: Deposit a second sub-word line conductive connection layer 272 in the plurality of word line grooves where the first sub-word line conductive connection layer 271 is formed.

[0186] Step 4: Etch back the first sub-word line conductive connection layer 271 and the second sub-word line conductive connection layer 272 to a second position above the bit line metal layer to form a word line conductive connection layer 27.

[0187] Step 5: Deposit a second insulating layer 28 in the plurality of word line grooves 25 where the word line conductive connection layer 27 is formed.

[0188] Among them, etching back the first sub-word line conductive connection layer 271 and the second sub-word line conductive connection layer 272 to a second position above the bit line metal layer to form a word line conductive connection layer 27, the obtained structure can be called a fourth structure. The structure obtained through the above steps can be called a target structure.

[0189] In the embodiment of the present application, refer to Figure 14 , Figure 14 for a top view of the third structure obtained based on the first structure shown in Figure 11 . Figure 14 In

[0190] Correspondingly, Figure 15A for Figure 14Schematic diagram of the Y2 cross-section of the fourth structure obtained from the third structure shown. Figure 15B is based on Figure 14 Schematic diagram of the Y1 cross-section of the fourth structure obtained from the third structure shown. Figure 15C is based on Figure 14 Schematic diagram of the X cross-section of the fourth structure obtained from the third structure shown.

[0191] After forming the word line grooves 25, a third isolation layer 26 is deposited on the bottom and side walls of the plurality of word line grooves 25 as the gate oxide layer of the word line. The material of the third isolation layer 26 can be silicon oxide, or it can also be silicon nitride, or it can also be silicon oxynitride, but it is not limited thereto.

[0192] Then, a first sub-word line conductive connection layer 271 is deposited above the formed third isolation layer 26. The material of the first sub-word line conductive connection layer 271 can be titanium nitride, or it can also be cobalt, but it is not limited thereto. Then, the remaining space in the word line grooves 25 is filled with a second sub-word line conductive connection layer 272. The material of the second sub-word line conductive connection layer 272 can be tungsten, or it can also be cobalt silicide, or it can also be titanium, but it is not limited thereto.

[0193] In addition, after filling the second sub-word line conductive connection layer 272, the first sub-word line conductive connection layer 271 and the second sub-word line conductive connection layer 272 are etched back, that is, etched to the second position. The etched first sub-word line conductive connection layer 271 and the second sub-word line conductive connection layer 272 constitute the word line conductive connection layer 27. Among them, the second position can be determined by those skilled in the art according to the size of the semiconductor structure and the actual preparation requirements. The second position can be lower than the top of the bit line conductive connection layer 15 and higher than the bottom of the bit line conductive connection layer 15.

[0194] In one embodiment, the second position can be close to the bottom of the bit line conductive connection layer 15. For example, the second position is lower than the midpoint of the bit line conductive connection layer 15 and higher than the bottom of the bit line conductive connection layer 15.

[0195] Furthermore, referring to Figure 16A 、 Figure 16B and Figure 16C , Figure 16A Schematic diagram of the Y2 cross-section of the target structure obtained from the fourth structure in FIG. 15. Figure 16B Schematic diagram of the Y1 cross-section of the target structure obtained from the fourth structure in FIG. 15. Figure 16C Schematic diagram of the X cross-section of the target structure obtained from the fourth structure in FIG. 15.

[0196] A second insulating layer 28 is deposited over the word line conductive connection layer 27 formed in the word line groove 25 to obtain a semiconductor structure. The second insulating layer 28 is used to protect the formed word lines from oxidation. The material of the second isolation layer 28 can be silicon nitride, or it can also be silicon oxide, or it can also be silicon oxynitride, but is not limited thereto.

[0197] Based on the preparation method of the above semiconductor structure, an embodiment of the present application further provides a semiconductor structure, which includes:

[0198] A substrate 10, the substrate includes a plurality of active region structures 17 arranged at intervals;

[0199] A plurality of bit line structures formed in the substrate 10 and extending in a first direction, each bit line structure includes a first isolation layer 12, a bit line metal wire layer, a bit line conductive connection layer 15, and a first insulating layer 16 distributed in sequence from bottom to top, and the bit line structures respectively intersect with the plurality of active region structures 17;

[0200] A second isolation layer 22 is provided between the bit line structures;

[0201] A plurality of word line structures formed in the substrate 10 and extending in a direction perpendicular to the first direction, each word line structure includes a third isolation layer 26, a word line conductive connection layer 27, and a second insulating layer 28 distributed in sequence from bottom to top.

[0202] In one embodiment, each word line structure includes: a first portion corresponding to the active region structure 17, a second portion corresponding to the second isolation layer 22, and a third portion corresponding to the bit line structure;

[0203] The lower surface of the first portion is lower than the lower surfaces of the second portion and the third portion.

[0204] In this way, the depth of the word line groove of the active region structure 17 is deeper than that of the isolation region, which can reduce the cross-sectional area of the word lines in the non-active region, thereby reducing the parasitic capacitance between the word lines and between the word lines and the bit lines, and effectively preventing hammer attacks.

[0205] In one embodiment, the lower surface of the third portion is flush with or higher than the upper surface of the bit line metal layer;

[0206] The upper surface of the word line conductive connection layer 27 is higher than the lower surfaces of the second portion and the third portion.

[0207] In this way, the relative area between the bit line and the word line can be reduced, avoiding excessive parasitic capacitance, and ensuring that the word lines are continuous.

[0208] In one embodiment, the upper surface of the word line conductive connection layer 27 is lower than the midpoint of the bit line conductive connection layer 15 and higher than the lower surface of the bit line conductive connection layer 15.

[0209] In one embodiment, the included angle between the bit line structure and the active region structure 17 is 15° to 30°.

[0210] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

[0211] Each embodiment in this specification is described in a related manner. The same or similar parts among the embodiments can be referred to each other, and the differences between each embodiment and other embodiments are emphasized.

[0212] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, the method comprises: providing a substrate; etching the substrate to form a plurality of bit line grooves extending in a first direction in the substrate; successively forming a first isolation layer, a bit line metal wire layer, a bit line conductive connection layer, and a first insulating layer in the plurality of bit line grooves to obtain a bit line structure; etching the substrate forming the bit line structure to obtain a plurality of spaced-apart active region structures and a first groove; wherein the bit line structures respectively intersect the plurality of active region structures; filling the second isolation layer in the first groove to obtain a first structure; etching the first structure to form a plurality of word line grooves extending in a direction perpendicular to the first direction in the first structure; successively forming a third isolation layer, a word line conductive connection layer, and a second insulating layer in the plurality of word line grooves.

2. The method according to claim 1, characterized in that, the first isolation layer comprises a first sub-isolation layer and a second sub-isolation layer; the successively forming a first isolation layer, a bit line metal wire layer, a bit line conductive connection layer, and a first insulating layer in the plurality of bit line grooves to obtain a bit line structure comprises: depositing a first sub-isolation layer at the bottom of the plurality of bit line grooves; depositing a second sub-isolation layer at the bottom and side walls of the plurality of bit line grooves forming the first sub-isolation layer; depositing a barrier layer at the bottom and side walls of the plurality of bit line grooves forming the second sub-isolation layer; depositing a bit line metal wire material layer in the plurality of bit line grooves forming the barrier layer; etching back the barrier layer and the bit line metal wire material layer to obtain a bit line metal wire layer; depositing a bit line conductive connection layer in the plurality of bit line grooves forming the bit line metal wire layer; depositing a first insulating layer in the plurality of bit line grooves forming the bit line conductive connection layer to obtain a bit line structure.

3. The method according to claim 1, characterized in that, the word line grooves comprise a first word line groove, a second word line groove, and a third word line groove; the etching the first structure to form a plurality of word line grooves extending in a direction perpendicular to the first direction in the first structure comprises: etching the active region structure to form a first word line groove; etching the second isolation layer to form a second word line groove; etching the bit line structure to form a third word line groove; the bottom surface of the first word line groove is lower than the bottom surfaces of the second word line groove and the third word line groove.

4. The method according to claim 3, characterized in that, the bottom surface of the third word line groove is flush with or higher than the upper surface of the bit line metal wire layer; the upper surface of the word line conductive connection layer is higher than the bottom surfaces of the second word line groove and the third word line groove.

5. The method according to claim 1, characterized in that, the etching the first structure to form a plurality of word line grooves extending in a direction perpendicular to the first direction in the first structure comprises: Etch the first structure to form a plurality of second grooves extending in the vertical direction along the first direction in the first structure, and the bottom surface of the second groove is flush with the lower surface of the bit line conductive connection layer; Etch the portion corresponding to the active region structure in the second groove to a first position to form a plurality of word line grooves in the first structure, and the bottom surface of the word line groove corresponding to the active region structure is lower than the bottom surface of the word line groove corresponding to the second isolation layer and the bit line structure.

6. The method according to claim 1, wherein, the etching of the substrate to form a plurality of bit line grooves extending in the first direction in the substrate includes: forming a first mask layer on the substrate; wherein, the first mask layer includes a plurality of first mask strips extending in the first direction, and the plurality of first mask strips are parallel to each other; etch the substrate covered by the first mask layer to form a plurality of bit line grooves extending in the first direction in the substrate.

7. The method according to claim 1, wherein, the etching of the substrate forming the bit line structure to obtain a plurality of spaced active region structures and first grooves includes: forming a second mask layer on the substrate forming the bit line structure; etch the substrate forming the bit line structure covered by the second mask layer to obtain a plurality of spaced active region structures and first grooves; wherein, the second mask layer includes a plurality of spaced second mask strips, and the regions of each second mask strip respectively intersect with the region of a bit line structure.

8. The method according to claim 7, wherein, before etching the substrate forming the bit line structure covered by the second mask layer to obtain a plurality of spaced active region structures and first grooves, the method further includes: providing a third mask layer, the third mask layer includes a plurality of third mask strips extending in the second direction, and the plurality of third mask strips are parallel to each other; cut each of the third mask strips into a plurality of second mask strips with a preset length.

9. The method according to claim 8, wherein, the included angle between the first direction and the second direction is 15° to 30°.

10. The method according to claim 1, wherein, the sequentially forming a third isolation layer, a word line conductive connection layer and a second insulating layer in the plurality of word line grooves includes: depositing a third isolation layer on the bottom and side walls of the plurality of word line grooves; depositing a first sub-word line conductive connection layer on the bottom and side walls of the plurality of word line grooves forming the third isolation layer; depositing a second sub-word line conductive connection layer in the plurality of word line grooves forming the first sub-word line conductive connection layer; etch back the first sub-word line conductive connection layer and the second sub-word line conductive connection layer to a second position above the bit line metal line layer to form a word line conductive connection layer; depositing a second insulating layer in the plurality of word line grooves forming the word line conductive connection layer.

11. The method according to claim 10, wherein, The second position is lower than the midpoint of the bit line conductive connection layer and higher than the lower surface of the bit line conductive connection layer.

12. A semiconductor structure, characterized in that, the semiconductor structure includes: a substrate, the substrate including a plurality of active region structures arranged at intervals; a plurality of bit line structures formed in the substrate and extending in a first direction, each bit line structure including a first isolation layer, a bit line metal wire layer, a bit line conductive connection layer, and a first insulating layer sequentially distributed from bottom to top, and the bit line structures respectively intersect with the plurality of active region structures; a second isolation layer is provided between the bit line structures; a plurality of word line structures formed in the substrate and extending in a direction perpendicular to the first direction, each word line structure including a third isolation layer, a word line conductive connection layer, and a second insulating layer sequentially distributed from bottom to top.

13. The semiconductor structure according to claim 12, characterized in that, each word line structure includes: a first part corresponding to the active region structure, a second part corresponding to the second isolation layer, and a third part corresponding to the bit line structure; the lower surface of the first part is lower than the lower surfaces of the second part and the third part.

14. The semiconductor structure according to claim 13, characterized in that, the lower surface of the third part is flush with the upper surface of the bit line metal wire layer or higher than the upper surface of the bit line metal wire layer; the upper surface of the word line conductive connection layer is higher than the lower surfaces of the second part and the third part.

15. The semiconductor structure according to claim 12, characterized in that, the upper surface of the word line conductive connection layer is lower than the midpoint of the bit line conductive connection layer and higher than the lower surface of the bit line conductive connection layer.

16. The semiconductor structure according to claim 12, characterized in that, the included angle between the bit line structure and the active region structure is 15° to 30°.

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