Semiconductor Structure and Method for Preparing the Same

Abstract

The present disclosure relates to a semiconductor structure and a method for manufacturing the same. The method for manufacturing the semiconductor structure includes: providing a substrate, on which a shallow trench isolation structure is formed; forming a plurality of transistor accommodation grooves in the active region, with a gap between the transistor accommodation grooves and the shallow trench isolation structure; forming a columnar structure in the transistor accommodation grooves, the columnar structure including a source electrode, a conductive channel, and a drain electrode sequentially arranged in a direction away from the substrate; etching and removing the active region located within the aforementioned gap and the active region between adjacent columnar structures within the same active region to form a bit line trench, the bit line trench surrounding the source electrode; forming a bit line surrounding and contacting the source electrode in the bit line trench. The manufacturing method can reduce the contact resistance between the transistor and the bit line, as well as between the transistor and the word line, thereby improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor integrated circuit manufacturing, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory in electronic devices such as computers. It is composed of multiple memory cells. Among them, the memory cell includes a storage capacitor and a transistor electrically connected to the storage capacitor. The transistor includes a gate, a source region, and a drain region. The gate of the transistor is used to be electrically connected to a word line. The source region of the transistor is used to form a bit line contact region to be electrically connected to a bit line through a bit line contact structure. The drain region of the transistor is used to form a storage node contact region to be electrically connected to the storage capacitor through a storage node contact structure.

[0003] However, as the size of DRAM becomes smaller and smaller, using a Vertical Gate All Around transistor (VGAA transistor) for the transistor can effectively reduce the size of DRAM. However, it is also easy to have an excessive contact resistance due to the Schottky barrier and Metal-Induced Gap States (MIGS) at the contact between the metal material and the semiconductor material when the line width size is continuously reduced, resulting in the output current of the transistor being difficult to meet the working requirements of DRAM and having an adverse impact on the electrical performance of DRAM. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can reduce the contact resistance between the transistor and the bit line, and between the transistor and the storage node contact structure, thereby improving the electrical performance of the semiconductor structure.

[0005] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, which includes the following steps.

[0006] Provide a substrate, on which a shallow trench isolation structure is formed. The shallow trench isolation structure isolates a plurality of spaced-apart active regions in the substrate. Form a plurality of transistor accommodation grooves in the active regions, with a gap between the transistor accommodation grooves and the shallow trench isolation structure. Form a columnar structure in the transistor accommodation grooves. The columnar structure includes a source electrode, a conductive channel, and a drain electrode arranged in sequence along a direction away from the substrate. Etch away the active regions located in the aforementioned gap and the active regions between adjacent columnar structures in the same active region to form a bit line trench. The bit line trench surrounds the source electrode. Form a bit line surrounding and contacting the source electrode in the bit line trench.

[0007] In some embodiments, forming a columnar structure in a transistor receiving groove includes the following steps.

[0008] Fill the transistor receiving groove with a semiconductor material to form a source electrode. Deposit a semiconductor material on the substrate to form a semiconductor thin film covering the source electrode. Pattern the semiconductor thin film to form a drain electrode and a conductive channel. The positive projection of the drain electrode on the substrate and the positive projection of the conductive channel on the substrate both overlap with the positive projection of the source electrode on the substrate.

[0009] In some embodiments, etching away the active regions within the spacer and the active regions between adjacent columnar structures within the same active region to form bit line trenches includes the following steps.

[0010] Form a first sacrificial layer covering the exposed surfaces of the columnar structure and the exposed surface of the substrate. Pattern the first sacrificial layer, and based on the pattern of the first sacrificial layer, etch away the active regions within the spacer and the active regions between adjacent columnar structures within the same active region. Remove the first sacrificial layer.

[0011] In some embodiments, before forming the bit line trenches, the method for preparing the semiconductor structure further includes: forming a contact plug on the drain electrode.

[0012] Correspondingly, after forming a bit line surrounding the contact source in the bit line trench, the method for preparing the semiconductor structure further includes the following steps.

[0013] Form a first dielectric material layer covering the bit line, the conductive channel, the drain electrode, and the contact plug. Form a surround gate word line corresponding to surround the conductive channel on the surface of the first dielectric material layer facing away from the conductive channel. There is an air gap between adjacent surround gate word lines. Form a second dielectric material layer covering the surround gate word line on the surface of the first dielectric material layer facing away from the contact plug. Etch the second dielectric material layer and the first dielectric material layer to obtain the first dielectric layer and the second dielectric layer. The first dielectric layer and the second dielectric layer expose the contact plug.

[0014] In some embodiments, forming a surround gate word line corresponding to surround the conductive channel on the surface of the first dielectric material layer facing away from the conductive channel includes the following steps.

[0015] Deposit a metal material on the first dielectric material layer. Etch the metal material until the upper surface of the metal material is flush with the upper surface of the columnar structure or the upper surface of the metal material is lower than the upper surface of the columnar structure to obtain a metal pattern layer. Form a second sacrificial layer covering the exposed surface of the first dielectric material layer and the metal pattern layer. Pattern the second sacrificial layer, and based on the pattern of the second sacrificial layer, etch the metal pattern layer to obtain a surround gate word line corresponding to surround the conductive channel. Remove the second sacrificial layer.

[0016] Optionally, the metal material includes tungsten metal.

[0017] In some embodiments, before etching the second dielectric material layer and the first dielectric material layer, the method for manufacturing a semiconductor structure further includes: forming a third dielectric material layer on the second dielectric material layer; and forming a plurality of contact windows in the third dielectric material layer to obtain a third dielectric layer.

[0018] Correspondingly, etching the second dielectric material layer and the first dielectric material layer to obtain a first dielectric layer and a second dielectric layer, where the first dielectric layer and the second dielectric layer expose the contact plugs, includes: etching the second dielectric material layer and the first dielectric material layer based on the contact windows to obtain a first dielectric layer and a second dielectric layer, where the first dielectric layer and the second dielectric layer expose the contact plugs.

[0019] After etching the second dielectric material layer and the first dielectric material layer to obtain a first dielectric layer and a second dielectric layer, where the first dielectric layer and the second dielectric layer expose the contact plugs, the method for manufacturing a semiconductor structure further includes: forming a contact pad in the contact window in contact with the contact plug.

[0020] In some embodiments, forming a contact pad in the contact window in contact with the contact plug includes the following steps.

[0021] Forming a pad material layer in the contact window and on the surface of the third dielectric layer. Removing the pad material layer located on the surface of the third dielectric layer by a chemical mechanical polishing process, and the pad material layer remaining in the contact window is the contact pad.

[0022] Optionally, the material of the bit line and / or the contact plug includes bismuth metal.

[0023] Optionally, the material of the columnar structure includes molybdenum disulfide.

[0024] Some embodiments of the present disclosure also provide a semiconductor structure, which is obtained by using the manufacturing method in the above - mentioned some embodiments. The semiconductor structure includes a substrate, a transistor accommodation groove, a columnar structure, and a bit line. A shallow trench isolation structure is formed on the substrate, and the shallow trench isolation structure isolates a plurality of spaced - apart active regions in the substrate. The transistor accommodation groove is located in the active region and has a gap with the shallow trench isolation structure. The columnar structure is located in the transistor accommodation groove, and the columnar structure includes: a source electrode, a conductive channel, and a drain electrode arranged in sequence along a direction away from the substrate. The bit line is located in the gap and surrounds the source electrode in contact.

[0025] In some embodiments, the material of the columnar structure includes molybdenum disulfide. And / or, the material of the bit line includes bismuth metal.

[0026] In some embodiments, the semiconductor structure further includes: a contact plug, a first dielectric layer, a surround gate word line, and a second dielectric layer. The contact plug is located on the surface of the drain facing away from the conductive channel. The first dielectric layer covers the bit line and is located on the sidewalls of the conductive channel, the drain, and the contact plug. The surround gate word line is located on the surface of the first dielectric layer facing away from the conductive channel and surrounds the conductive channel. The second dielectric layer is located on the surface of the first dielectric layer facing away from the contact plug and covers the surround gate word line. There is an air gap between adjacent surround gate word lines.

[0027] In some embodiments, the semiconductor structure further includes: a third dielectric layer and a contact pad. The third dielectric layer has a contact window and covers at least the second dielectric layer. The contact pad is located within the contact window and is in contact with the contact plug. Optionally, the material of the contact plug includes bismuth metal.

[0028] In the embodiments of the present disclosure, a transistor accommodation groove is provided in the active region isolated by the shallow trench isolation structure, and a gap is provided between the transistor accommodation groove and the shallow trench isolation structure. In this way, a columnar structure can be formed in the transistor accommodation groove first, and then the active region within the aforementioned gap and the active region between adjacent columnar structures in the same active region are removed to obtain a bit line trench. Based on this, after forming a bit line in the bit line trench, the bit line surrounds the contact source electrode, which can make the contact area between the bit line and the source electrode larger, thereby reducing the contact resistance between the bit line and the source electrode, that is, the contact resistance between the bit line and the transistor, so as to improve the electrical performance of the semiconductor structure. And, the preparation method in the embodiments of the present disclosure is easy to operate and is conducive to the large-scale production of semiconductor structures.

[0029] In addition, the material of the columnar structure includes molybdenum disulfide, the material of the bit line includes bismuth metal, and the material of the contact plug includes bismuth (Bi) metal. In this way, the two-dimensional crystal structure of the columnar structure is not easily damaged due to its contact with the bit line or the contact plug, which can further reduce the contact resistance between the bit line or the contact plug and the transistor, so as to ensure that the transistor has good low-power consumption performance and high-frequency performance, thereby further improving the electrical performance of the semiconductor structure. Description of the Drawings

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0031] Figure 1 It is a flowchart of a method for preparing a semiconductor structure provided in an embodiment;

[0032] Figure 2 Flow chart of another method for preparing a semiconductor structure provided in an embodiment;

[0033] Figure 3 Flow chart of yet another method for preparing a semiconductor structure provided in an embodiment;

[0034] Figure 4a Cross-sectional view of the structure obtained in step S100 along the first direction in an embodiment; wherein, the first direction is the extending direction of the wrap-around gate word line;

[0035] Figure 4b Cross-sectional view of the structure obtained in step S100 along the second direction in an embodiment; wherein, the second direction is the extending direction of the bit line;

[0036] Figure 5a Cross-sectional view of the structure obtained in step S200 along the first direction in an embodiment;

[0037] Figure 5b Cross-sectional view of the structure obtained in step S200 along the second direction in an embodiment;

[0038] Figure 6 Flow chart of step S300 provided in an embodiment;

[0039] Figure 7a Cross-sectional view of the structure obtained in step S301 along the first direction in an embodiment;

[0040] Figure 7b Cross-sectional view of the structure obtained in step S301 along the second direction in an embodiment;

[0041] Figure 8a Cross-sectional view of the structure obtained in step S302 along the first direction in an embodiment;

[0042] Figure 8b Cross-sectional view of the structure obtained in step S302 along the second direction in an embodiment;

[0043] Figure 9a Cross-sectional view of the structure obtained after forming the contact plug material layer along the first direction in an embodiment;

[0044] Figure 9b Cross-sectional view of the structure obtained after forming the contact plug material layer along the second direction in an embodiment;

[0045] Figure 10a Cross-sectional view of the structure obtained in step S303 along the first direction in an embodiment;

[0046] Figure 10b It is a schematic cross-sectional view of the structure obtained in step S303 provided in an embodiment along the second direction;

[0047] Figure 11 It is a flowchart of step S400 provided in an embodiment;

[0048] Figure 12a It is a schematic cross-sectional view of the structure obtained in step S401 provided in an embodiment along the first direction;

[0049] Figure 12b It is a schematic cross-sectional view of the structure obtained in step S401 provided in an embodiment along the second direction;

[0050] Figure 13a It is a schematic cross-sectional view of the structure obtained in step S402 provided in an embodiment along the first direction;

[0051] Figure 13b It is a schematic cross-sectional view of the structure obtained in step S402 provided in an embodiment along the second direction;

[0052] Figure 14a It is a schematic cross-sectional view of the structure obtained in step S501 provided in an embodiment along the first direction;

[0053] Figure 14b It is a schematic cross-sectional view of the structure obtained in step S501 provided in an embodiment along the second direction;

[0054] Figure 15a It is a schematic cross-sectional view of the structure obtained in step S502 provided in an embodiment along the first direction;

[0055] Figure 15b It is a schematic cross-sectional view of the structure obtained in step S502 provided in an embodiment along the second direction;

[0056] Figure 16a It is a schematic cross-sectional view of the structure obtained in step S403 provided in an embodiment along the first direction;

[0057] Figure 16b It is a schematic cross-sectional view of the structure obtained in step S403 provided in an embodiment along the second direction;

[0058] Figure 17a It is a schematic cross-sectional view of the structure obtained in step S600 provided in an embodiment along the first direction;

[0059] Figure 17b It is a schematic cross-sectional view of the structure obtained in step S600 provided in an embodiment along the second direction;

[0060] Figure 18 It is a flowchart of step S700 provided in an embodiment;

[0061] Figure 19a It is a schematic cross-sectional view of the structure obtained in step S701 along the first direction in an embodiment;

[0062] Figure 19b It is a schematic cross-sectional view of the structure obtained in step S701 along the second direction in an embodiment;

[0063] Figure 20a It is a schematic cross-sectional view of the structure obtained in step S702 along the first direction in an embodiment;

[0064] Figure 20b It is a schematic cross-sectional view of the structure obtained in step S702 along the second direction in an embodiment;

[0065] Figure 21a It is a schematic cross-sectional view of the structure obtained in step S703 along the first direction in an embodiment;

[0066] Figure 21b It is a schematic cross-sectional view of the structure obtained in step S703 along the second direction in an embodiment;

[0067] Figure 22a It is a schematic cross-sectional view of the structure obtained in step S704 along the first direction in an embodiment;

[0068] Figure 22b It is a schematic cross-sectional view of the structure obtained in step S704 along the second direction in an embodiment;

[0069] Figure 23a It is a schematic cross-sectional view of the structure obtained in step S705 along the first direction in an embodiment;

[0070] Figure 23b It is a schematic cross-sectional view of the structure obtained in step S705 along the second direction in an embodiment;

[0071] Figure 24a It is a schematic cross-sectional view of the structure obtained in step S800 along the first direction in an embodiment;

[0072] Figure 24b It is a schematic cross-sectional view of the structure obtained in step S800 along the second direction in an embodiment;

[0073] Figure 25a It is a schematic cross-sectional view of the structure obtained in step S850 along the first direction in an embodiment;

[0074] Figure 25bSchematic cross-sectional view along the second direction of the structure obtained in step S850 provided in an embodiment;

[0075] Figure 26a Schematic cross-sectional view along the first direction of the structure obtained in step S860 provided in an embodiment;

[0076] Figure 26b Schematic cross-sectional view along the second direction of the structure obtained in step S860 provided in an embodiment;

[0077] Figure 27a Schematic cross-sectional view along the first direction of the structure obtained in step S900 provided in an embodiment;

[0078] Figure 27b Schematic cross-sectional view along the second direction of the structure obtained in step S900 provided in an embodiment;

[0079] Figure 28 Flowchart of step S1000 provided in an embodiment;

[0080] Figure 29a Schematic cross-sectional view along the first direction of the structure obtained in step S1001 provided in an embodiment;

[0081] Figure 29b Schematic cross-sectional view along the second direction of the structure obtained in step S1001 provided in an embodiment;

[0082] Figure 30a Schematic cross-sectional view along the first direction of the structure obtained in step S1002 provided in an embodiment; and, Figure 30a Also schematic cross-sectional view along the first direction of a semiconductor structure provided in an embodiment;

[0083] Figure 30b Schematic cross-sectional view along the second direction of the structure obtained in step S1002 provided in an embodiment; and, Figure 30b Also schematic cross-sectional view along the second direction of a semiconductor structure provided in an embodiment;

[0084] Figure 31 Schematic cross-sectional view of a GAA provided in an embodiment.

[0085] Description of reference numerals:

[0086] 1 - Substrate, 11 - Shallow trench isolation structure, 12 - Transistor accommodation groove, L - Spacing, 2 - Columnar structure,

[0087] 21 - Source, 22 - Conductive channel, 23 - Drain, 20 - Semiconductor thin film, 30 - Contact plug material layer,

[0088] 3 - contact plug, 40 - first sacrificial layer, 41 - bit line trench, 5 - bit line, 50 - bit line material layer,

[0089] 610 - first dielectric material layer, 61 - first dielectric layer, 620 - second dielectric material layer,

[0090] 62 - second dielectric layer, 630 - third dielectric material layer, 63 - third dielectric layer, 70 - metal material,

[0091] 71 - metal pattern layer, 80 - second sacrificial layer, 7 - surround gate word line, G - air gap, K - contact window,

[0092] 90 - pad material layer, 9 - contact pad. Detailed implementation mode

[0093] For the convenience of understanding the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present disclosure is more thorough and comprehensive.

[0094] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this disclosure belongs. The terms used herein in the description of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0095] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0096] It should be understood that although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below may be denoted as the second element, component, region, layer or part.

[0097] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. can be used herein to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the attached drawings is flipped, an element or feature described as "under other elements" or "beneath them" or "under it" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both upper and lower orientations. In addition, the device may also have other orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0098] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / having" etc. specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0099] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention, and such can be expected to vary due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the invention should not be limited to the particular shapes of regions shown herein, but include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0100] The Gate All Around transistor (GAA transistor) has more advantages in terms of miniaturization, high performance, and low power consumption, and is considered to be the key core technology for the next generation of integrated circuits. Taking the vertical Gate All Around transistor as an example, this transistor has more integration degrees of freedom in the vertical direction, can effectively reduce the planar area it occupies, is also more conducive to realizing the vertical stacking between multi-layer devices, and further increasing the integration density through a new wiring method.

[0101] However, in the case of continuously shrinking line width dimensions, when setting GAA transistors in a semiconductor structure, it is easy for the contact between the metal material and the semiconductor material to have an excessive contact resistance due to the Schottky barrier and Metal-Induced Gap States (MIGS).

[0102] Based on this, please refer to Figure 1 , some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, which includes the following steps.

[0103] S100, provide a substrate, on which a shallow trench isolation structure is formed. The shallow trench isolation structure isolates a plurality of spaced-apart active regions within the substrate.

[0104] S200, form a plurality of transistor accommodation grooves within the active regions, with a gap between the transistor accommodation grooves and the shallow trench isolation structure.

[0105] S300, form a columnar structure within the transistor accommodation grooves. The columnar structure includes a source electrode, a conductive channel, and a drain electrode arranged in sequence along a direction away from the substrate.

[0106] S400, etch and remove the active regions located within the aforementioned gap and the active regions between adjacent columnar structures within the same active region to form bit line trenches. The bit line trenches surround the source electrode.

[0107] S500, form a bit line within the bit line trenches that surrounds and contacts the source electrode.

[0108] In the embodiments of the present disclosure, transistor accommodation grooves are provided within the active regions isolated by the shallow trench isolation structure, and a gap is provided between the transistor accommodation grooves and the shallow trench isolation structure. In this way, a columnar structure can be first formed within the transistor accommodation grooves, and then the active regions located within the aforementioned gap and the active regions between adjacent columnar structures within the same active region are removed to obtain bit line trenches. Based on this, after forming a bit line within the bit line trenches, the bit line surrounds and contacts the source electrode, which can make the contact area between the bit line and the source electrode larger, thereby reducing the contact resistance between the bit line and the source electrode, that is, the contact resistance between the bit line and the transistor, so as to improve the electrical performance of the semiconductor structure. Moreover, the manufacturing method in the embodiments of the present disclosure is easy to operate and is conducive to the large-scale production of semiconductor structures.

[0109] In some embodiments, the material of the columnar structure includes molybdenum disulfide (MoS 2 ), and the material of the bit line includes bismuth (Bi) metal. In this way, the two-dimensional crystal structure of the columnar structure is not easily damaged due to its contact with the bit line, which can further reduce the contact resistance between the bit line and the transistor, so as to ensure that the transistor has good low-power consumption performance and high-frequency performance, thereby further improving the electrical performance of the semiconductor structure.

[0110] Of course, the material of the columnar structure can also be other two-dimensional semiconductor materials, and the material of the bit line can also be other materials that are not prone to form alloys with two-dimensional semiconductor materials to destroy the two-dimensional crystal structure. For example, the material of the columnar structure is: molybdenum diselenide (MoSe2), tungsten disulfide (WS2), tungsten diselenide (WSe2), or bismuth selenide (Bi2Se3). The material of the bit line is: chromium (Cr), cadmium (Cd), iridium (Ir), niobium (Nb), tantalum (Ta), tellurium (Te), or tungsten (W).

[0111] Please refer to Figure 2 , in some embodiments, before performing S400, that is, forming the bit line trench, the method for preparing the semiconductor structure further includes: forming a contact plug on the drain.

[0112] Optionally, the contact plug, the conductive channel in the columnar structure, and the drain are formed by a single patterning process. That is, step S300 further includes: forming a contact plug on the columnar structure.

[0113] Optionally, the material of the contact plug includes bismuth (Bi) metal. Alternatively, the material of the contact plug can also be: chromium (Cr), cadmium (Cd), iridium (Ir), niobium (Nb), tantalum (Ta), tellurium (Te), or tungsten (W). This can ensure that there is also a low contact resistance between the contact plug and the transistor.

[0114] Based on this, after performing S500, that is, forming the bit line surrounding the contact source in the bit line trench, the method for preparing the semiconductor structure further includes the following steps.

[0115] S600, forming a first dielectric material layer covering the bit line, the conductive channel, the drain, and the contact plug.

[0116] S700, forming a surround gate word line corresponding to surround the conductive channel on the surface of the first dielectric material layer facing away from the conductive channel. There is an air gap between adjacent surround gate word lines.

[0117] S800, forming a second dielectric material layer covering the surround gate word line on the surface of the first dielectric material layer facing away from the contact plug.

[0118] S900, etching the second dielectric material layer and the first dielectric material layer to obtain the first dielectric layer and the second dielectric layer. The first dielectric layer and the second dielectric layer expose the contact plug.

[0119] In the embodiments of the present disclosure, an air gap is provided between adjacent surround gate word lines, which can effectively isolate the gate word lines by using the air gap to ensure the electrical performance of the semiconductor structure.

[0120] Please refer to Figure 3, in some embodiments, before performing step S900, i.e., etching the second dielectric material layer and the first dielectric material layer, the method for preparing a semiconductor structure further includes the following steps.

[0121] S850, form a third dielectric material layer on the second dielectric material layer.

[0122] S860, form a plurality of contact windows in the third dielectric material layer to obtain a third dielectric layer.

[0123] Based on this, in step S900, etching the second dielectric material layer and the first dielectric material layer to obtain a first dielectric layer and a second dielectric layer, with the first dielectric layer and the second dielectric layer exposing the contact plugs, includes: etching the second dielectric material layer and the first dielectric material layer based on the contact windows to obtain a first dielectric layer and a second dielectric layer, with the first dielectric layer and the second dielectric layer exposing the contact plugs.

[0124] After performing S900, i.e., etching the second dielectric material layer and the first dielectric material layer to obtain a first dielectric layer and a second dielectric layer, with the first dielectric layer and the second dielectric layer exposing the contact plugs, the method for preparing a semiconductor structure further includes the following steps.

[0125] S1000, form a contact pad in the contact window that contacts the contact plug. The structure of the contact pad can be selected and set according to actual needs. Optionally, the contact pad is a metal pad, such as a tungsten pad. Thereby, it can be ensured that the contact pad has a low resistance value and high stability.

[0126] In addition, in some embodiments, the contact plug and the contact pad can jointly form a storage node contact structure and are used to contact a storage capacitor to form a storage unit. The embodiments of the present disclosure do not limit this.

[0127] Some of the above embodiments exemplarily give some processes in the method for preparing a semiconductor structure, and their corresponding specific embodiments are described in detail in the following some embodiments. Please understand the following content in combination with the above some processes.

[0128] In step S100, please refer to Figures 1 to 3 S100 in Figure 4a 、 Figure 4b , provide a substrate 1, and a shallow trench isolation structure 11 is formed on the substrate 1. The shallow trench isolation structure 11 isolates a plurality of spaced-apart active regions in the substrate 1.

[0129] In one example, the substrate 1 includes but is not limited to a silicon substrate or a silicon-based substrate. Optionally, the substrate 1 is a sapphire substrate, a silicon substrate, or a silicon carbide substrate.

[0130] In one example, the material of the active region is, for example, polysilicon (poly). The shallow trench isolation structure 11 is, for example, a silicon dioxide (SiO2) isolation structure. In addition, the arrangement of the active regions can be understood according to related technologies, and the embodiments of the present application do not limit this.

[0131] In step S200, please refer to Figures 1 to 3 S200 in Figure 5a and Figure 5b , a plurality of transistor receiving grooves 12 are formed in the active region. There is a gap L between the transistor receiving grooves 12 and the shallow trench isolation structure 11.

[0132] Here, the shape and size of the transistor receiving grooves 12 and the size of the gap L can be selected and set according to actual requirements, and the embodiments of the present application do not limit this. In one example, the transistor receiving grooves 12 are, for example, columnar grooves.

[0133] In step S300, please refer to Figure 1 and Figure 2 and Figure 3 and Figure 6 , execute S300, that is, a columnar structure is formed in the transistor receiving groove, and the steps are as follows.

[0134] S301, filling a semiconductor material in the transistor receiving groove to form a source electrode.

[0135] S302, depositing a semiconductor material on the substrate to form a semiconductor thin film covering the source electrode.

[0136] S303, patterning the semiconductor thin film to form a drain electrode and a conductive channel. The orthographic projection of the drain electrode on the substrate and the orthographic projection of the conductive channel on the substrate both overlap with the orthographic projection of the source electrode on the substrate.

[0137] In step S301, please refer to S301 in Figure 4 and Figure 7a and Figure 7b , filling a semiconductor material in the transistor receiving groove 12 to form a source electrode 21.

[0138] In one example, the semiconductor material is a two-dimensional semiconductor material, for example, a transition metal disulfide. Optionally, the semiconductor material is molybdenum disulfide (MoS 2 ), molybdenum selenide (MoSe 2 ), tungsten disulfide (WS 2 ), tungsten diselenide (WSe 2 ) or bismuth selenide (Bi 2 Se 3 ).

[0139] In step S302, please refer to S302 in Figure 4 and Figure 8a andFigure 8b , a semiconductor material is deposited on the substrate 1 to form a semiconductor thin film 20 covering the source electrode 21.

[0140] Here, the semiconductor material used to form the semiconductor thin film 20 can be the same as the semiconductor material used to form the source electrode 21 in S301 to ensure that the semiconductor thin film 20 can be well bonded to the source electrode 21.

[0141] In addition, the thickness of the semiconductor thin film 20 can be determined according to the height of the columnar structure to be formed subsequently.

[0142] In one example, the deposition process of the semiconductor material includes but is not limited to Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD).

[0143] In some embodiments, please combine Figure 2 to understand that the contact plug and the conductive channel and drain in the columnar structure can be formed by a single patterning process. Based on this, please refer to Figure 9a and Figure 9b , after the semiconductor thin film 20 is formed, the manufacturing method of the semiconductor structure further includes: depositing a contact plug material layer 30 on the semiconductor thin film 20.

[0144] Optionally, the contact plug material layer 30 includes a bismuth metal layer. In addition, optionally, the material of the contact plug material layer 30 can also be chromium (Cr), cadmium (Cd), iridium (Ir), niobium (Nb), tantalum (Ta), tellurium (Te), or tungsten (W), etc.

[0145] In one example, the deposition process of the contact plug material layer 30 includes but is not limited to Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD).

[0146] In step S303, please refer to S303 in FIG. 4 and Figure 10a , Figure 10b , pattern the semiconductor thin film 20 to form a drain 23 and a conductive channel 22. The positive projection of the drain 23 on the substrate 1 and the positive projection of the conductive channel 22 on the substrate 1 both overlap with the positive projection of the source electrode 21 on the substrate 1. Thus, the drain 23, the conductive channel 22, and the source electrode 21 are arranged in a columnar shape to jointly form a columnar structure 2.

[0147] It is understandable that the source electrode 21 and the drain electrode 23 can be obtained by ion implantation of a semiconductor material, and the embodiments of the present disclosure do not elaborate on this specifically.

[0148] Based on the fact that the contact plug material layer 30 is formed on the semiconductor thin film 20, after patterning the semiconductor thin film 20, the contact plug material layer 30 can also be patterned synchronously to form the contact plug 3 located on the columnar structure 2, as Figure 10a and Figure 10b shown in.

[0149] In step S400, please refer to Figure 1 , Figure 2 , Figure 3 and Figure 11 , and execute S400, that is, etch away the active regions located within the spacings and the active regions between adjacent columnar structures within the same active region to form bit line trenches, including the following steps.

[0150] S401, form a first sacrificial layer covering the exposed surfaces of the columnar structure and the substrate.

[0151] S402, pattern the first sacrificial layer, and based on the pattern of the first sacrificial layer, etch away the active regions located within the spacings and the active regions between adjacent columnar structures within the same active region.

[0152] S403, remove the first sacrificial layer.

[0153] In step S401, please refer to Figure 11 S401 in Figure 12a , Figure 12b , and form a first sacrificial layer 40 covering the exposed surface of the columnar structure 2 and the exposed surface of the substrate 1.

[0154] In one example, the first sacrificial layer 40 is formed by a deposition process. The material of the first sacrificial layer 40 is, for example, silicon nitride.

[0155] In step S402, please refer to Figure 11 S402 in Figure 13a , Figure 13b , pattern the first sacrificial layer 40, and based on the pattern of the first sacrificial layer 40, etch away the active regions located within the spacing L and the active regions between adjacent columnar structures 2 within the same active region to form the bit line trench 41. The bit line trench 41 surrounds the source electrode 21.

[0156] In one example, the process of patterning the first sacrificial layer 40 is, for example, a wet etching process.

[0157] In one example, the etching of the active region to be removed can be achieved by using a Self-Aligned Double Patterning (SADP) process or a Self-Aligned Quadruple Patterning (SAQP) process based on the pattern of the first sacrificial layer 40.

[0158] It can be understood that in some embodiments, the execution of step S403 can be carried out after the execution of step S500. The embodiments of the present application are schematically illustrated by taking this as an example as follows.

[0159] In step S500, please refer to Figure 14a 、 Figure 14b 、 Figure 15a and Figure 15b As shown, forming a bit line 5 surrounding the contact source 21 in the bit line trench 41 includes the following steps.

[0160] S501, please refer to Figure 14a and Figure 14b , form a bit line material layer 50 that fills the bit line trench 41 and covers the exposed surface of the first sacrificial layer 40.

[0161] Optionally, the bit line material layer 50 includes a bismuth metal layer.

[0162] S502, please refer to Figure 15a and Figure 15b , pattern the bit line material layer 50 to form a bit line 5 located in the bit line trench 41 and surrounding the contact source 21.

[0163] In one example, the patterning of the bit line material layer 50 can be achieved by using a Self-Aligned Double Patterning (SADP) process or a Self-Aligned Quadruple Patterning (SAQP) process based on the pattern of the first sacrificial layer 40.

[0164] In step S403, please refer to Figure 11 S403 in Figure 16a 、 Figure 16b , remove the first sacrificial layer 40.

[0165] In step S600, please refer to Figure 2 、 Figure 3 and Figure 17a 、 Figure 17b , form a first dielectric material layer 610 covering the bit line 5, the conductive channel 22, the drain 23, and the contact plug 3.

[0166] In one example, the first dielectric material layer 610 includes an oxide layer with a high dielectric constant, such as a silicon oxide layer. The first dielectric material layer 610 can be formed by a deposition process.

[0167] In step S700, refer to Figure 2 、 Figure 3 and Figure 18 , perform S700, that is, form a surround gate word line corresponding to surround the conductive channel on the surface of the first dielectric material layer facing away from the conductive channel, including the following steps.

[0168] S701, deposit a metal material on the first dielectric material layer.

[0169] S702, etch the metal material until the upper surface of the metal material is flush with the upper surface of the columnar structure, or the upper surface of the metal material is lower than the upper surface of the columnar structure, to obtain a metal pattern layer.

[0170] S703, form a second sacrificial layer covering the exposed surface of the first dielectric material layer and the metal pattern layer.

[0171] S704, pattern the second sacrificial layer and etch the metal pattern layer based on the pattern of the second sacrificial layer to obtain a surround gate word line corresponding to surround the conductive channel.

[0172] S705, remove the second sacrificial layer.

[0173] In step S701, refer to Figure 18 S701 in Figure 19a 、 Figure 19b , deposit a metal material 70 on the first dielectric material layer 610.

[0174] Optionally, the metal material 70 includes tungsten metal. Alternatively, the metal material 70 is other metal materials with good electrical conductivity, such as molybdenum (Mo), aluminum (Al), or titanium (Ti), etc.

[0175] In step S702, refer to Figure 18 S702 in Figure 20a 、 Figure 20b , etch the metal material 70 until the upper surface of the metal material 70 is flush with the upper surface of the columnar structure 2, or the upper surface of the metal material 70 is lower than the upper surface of the columnar structure 2, to obtain a metal pattern layer 71.

[0176] In step S703, refer to Figure 18 S703 in Figure 21a 、 Figure 21b , form a second sacrificial layer 80 covering the exposed surface of the first dielectric material layer 610 and the metal pattern layer 71.

[0177] In one example, the second sacrificial layer 80 is formed by a spin coating process. The second sacrificial layer 80 is, for example, a photoresist layer.

[0178] In step S704, refer to Figure 18 S704 in Figure 22a , Figure 22b , pattern the second sacrificial layer 80, and etch the metal pattern layer 71 based on the pattern of the second sacrificial layer 80 to obtain the surround gate word line 7 surrounding the conductive channel 22. There is an air gap G between adjacent surround gate word lines 7.

[0179] In one example, the process of patterning the second sacrificial layer 80 is, for example, a wet etching process.

[0180] In step S705, refer to Figure 18 S705 in Figure 23a , Figure 23b , remove the second sacrificial layer 80.

[0181] In step S800, refer to Figure 2 , Figure 3 and Figure 24a , Figure 24b , form a second dielectric material layer 620 covering the surround gate word line 7 on the surface of the first dielectric material layer 610 facing away from the contact plug 3.

[0182] Here, the material of the second dielectric material layer 620 can be the same as the material of the first dielectric material layer 610, for example, both are silicon oxide. This facilitates subsequent etching through a single patterning process. In addition, the second dielectric material layer 620 can be formed by a deposition process.

[0183] In step S850, refer to Figure 3 and Figure 25a , Figure 25b , form a third dielectric material layer 630 on the second dielectric material layer 620.

[0184] Here, the material of the third dielectric material layer 630 can be different from the material of the second dielectric material layer 620. For example, the material of the third dielectric material layer 630 is silicon nitride. In addition, the third dielectric material layer 630 can be formed by a deposition process, and the deposition thickness of the third dielectric material layer 630 can be selected and set according to the height dimension of the contact pad to be formed subsequently.

[0185] In step S860, refer to Figure 3 and Figure 26a , Figure 26b , form a plurality of contact windows K in the third dielectric material layer 630 to obtain the third dielectric layer 63.

[0186] Here, the contact window K is used to accommodate the contact pad, and the shape and distribution of the contact window K can be determined according to the shape and distribution of the contact pad to be formed subsequently.

[0187] In step S900, please refer to Figure 3 and Figure 27a , Figure 27b , etch the second dielectric material layer 620 and the first dielectric material layer 610 based on the contact window K to obtain the first dielectric layer 61 and the second dielectric layer 62. The first dielectric layer 61 and the second dielectric layer 62 expose the contact plug 3.

[0188] In step S1000, please refer to Figure 3 and Figure 28 , execute S1000, that is, forming a contact pad in contact with the contact plug in the contact window includes the following steps.

[0189] S1001, form a pad material layer in the contact window and on the surface of the third dielectric layer.

[0190] S1002, use a chemical mechanical polishing process to remove the pad material layer located on the surface of the third dielectric layer, and the pad material layer remaining in the contact window is the contact pad.

[0191] In step S1001, please refer to Figure 28 S1001 in Figure 29a , Figure 29b , form a pad material layer 90 in the contact window K and on the surface of the third dielectric layer 63. Optionally, the pad material layer 90 is a tungsten metal layer.

[0192] In step S1002, please refer to Figure 28 S1002 in Figure 30a , Figure 30b , use a chemical mechanical polishing process to remove the pad material layer 90 located on the surface of the third dielectric layer 63, and the pad material layer remaining in the contact window K is the contact pad 9.

[0193] In the embodiments of the present disclosure, using a chemical mechanical polishing process to form the contact pad 9 can ensure the flat surface of the contact pad 9, so as to facilitate the subsequent formation of other electrical devices such as a storage capacitor on the surface of the contact pad 9, and ensure that the contact pad 9 can be in good contact with the electrical device, thereby ensuring the electrical contact performance of the contact pad 9.

[0194] Some embodiments of the present disclosure also provide a semiconductor structure, which is prepared by using the preparation method in the above-mentioned some embodiments.

[0195] Please refer to Figure 30a , Figure 30b and Figure 31, the semiconductor structure includes a substrate 1, a transistor accommodating groove 12, a columnar structure 2, and a bit line 5. A shallow trench isolation structure 11 is formed on the substrate 1, and the shallow trench isolation structure 11 isolates a plurality of spaced-apart active regions within the substrate 1. The transistor accommodating groove 12 is located within the active region and has a gap from the shallow trench isolation structure 11. The columnar structure 2 is located within the transistor accommodating groove 12, and the columnar structure 2 includes: a source electrode 21, a conductive channel 22, and a drain electrode 23 arranged in sequence along a direction away from the substrate 1. The bit line 5 is located within the interval L and surrounds and contacts the source electrode 21.

[0196] In one example, the substrate 1 includes but is not limited to a silicon substrate or a silicon-based substrate. Optionally, the substrate 1 is a sapphire substrate, a silicon substrate, or a silicon carbide substrate.

[0197] In one example, the material of the active region is, for example, polysilicon (poly). The shallow trench isolation structure 11 is, for example, a silicon oxide (SiO2) isolation structure.

[0198] In some embodiments, the material of the columnar structure 2 includes molybdenum disulfide. And / or, the material of the bit line 5 includes bismuth metal. Of course, the material of the columnar structure can also be other two-dimensional semiconductor materials, and the material of the bit line can also be other materials that are not prone to form alloys with two-dimensional semiconductor materials to destroy the two-dimensional crystal structure. For example, the material of the columnar structure is: molybdenum selenide (MoSe2), tungsten disulfide (WS2), tungsten diselenide (WSe2), or bismuth selenide (Bi2Se3). The material of the bit line is: chromium (Cr), cadmium (Cd), iridium (Ir), niobium (Nb), tantalum (Ta), tellurium (Te), or tungsten (W).

[0199] In the embodiments of the present disclosure, the bit line 5 surrounds and contacts the source electrode 21, which can make the contact area between the bit line 5 and the source electrode 21 larger, thereby reducing the contact resistance between the bit line 5 and the source electrode 21, that is, the contact resistance between the bit line 5 and the GAA transistor, to improve the electrical performance of the semiconductor structure.

[0200] In some embodiments, the material of the columnar structure 2 includes molybdenum disulfide (MoS2), and the material of the bit line 5 includes bismuth (Bi) metal. In this way, the two-dimensional crystal structure of the columnar structure 2 is not easily damaged due to its contact with the bit line 5, which can further reduce the contact resistance between the bit line 5 and the GAA transistor to ensure that the GAA transistor has good low-power consumption performance and high-frequency performance, thereby further improving the electrical performance of the semiconductor structure.

[0201] In some embodiments, the semiconductor structure further includes: a contact plug 3, a first dielectric layer 61, a surround gate word line 7, and a second dielectric layer 62. The contact plug 3 is located on the surface of the drain 23 facing away from the conductive channel 22. The first dielectric layer 61 covers the bit line 5 and is located on the sidewalls of the conductive channel 22, the drain 23, and the contact plug 3. The surround gate word line 7 is located on the surface of the first dielectric layer 61 facing away from the conductive channel 22 and surrounds the conductive channel 22. The second dielectric layer 62 is located on the surface of the first dielectric layer 61 facing away from the contact plug 3 and covers the surround gate word line 7. There is an air gap G between adjacent surround gate word lines 7.

[0202] Optionally, the material of the contact plug 3 includes bismuth (Bi) metal. Alternatively, the material of the contact plug 3 can also be: chromium (Cr), cadmium (Cd), iridium (Ir), niobium (Nb), tantalum (Ta), tellurium (Te), or tungsten (W). This can ensure that there is also a low contact resistance between the contact plug and the transistor.

[0203] Optionally, the first dielectric layer 61 is a high-k oxide layer, such as a silicon oxide layer. The material of the second dielectric layer 62 can be the same as that of the first dielectric layer 61.

[0204] Optionally, the material of the surround gate word line 7 is tungsten (W), molybdenum (Mo), aluminum (Al), titanium (Ti), etc.

[0205] In some embodiments, the semiconductor structure further includes: a third dielectric layer 63 and a contact pad 9. The third dielectric layer 63 has a contact window K and covers at least the second dielectric layer 62. The contact pad 9 is located within the contact window K and is in contact with the contact plug 3.

[0206] Optionally, the material of the third dielectric layer 63 can be different from that of the second dielectric layer 62. For example, the material of the third dielectric layer 63 is silicon nitride.

[0207] Optionally, the contact pad 9 is a tungsten pad.

[0208] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0209] The above-described embodiments merely represent several implementation manners of the present disclosure. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure patent should be subject to the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, comprising: providing a substrate, on which a shallow trench isolation structure is formed, and the shallow trench isolation structure isolates a plurality of spaced-apart active regions within the substrate; forming a plurality of transistor accommodation grooves within the active regions, with a gap between the transistor accommodation grooves and the shallow trench isolation structure; forming a columnar structure within the transistor accommodation grooves, and the columnar structure includes a source electrode, a conductive channel, and a drain electrode sequentially arranged in a direction away from the substrate; etching and removing the active regions within the gaps and the active regions between adjacent columnar structures within the same active region to form bit line trenches, and the bit line trenches surround the source electrode; forming a bit line within the bit line trenches that surrounds and contacts the source electrode.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, the forming a columnar structure within the transistor accommodation grooves includes: filling a semiconductor material within the transistor accommodation grooves to form the source electrode; depositing the semiconductor material on the substrate to form a semiconductor thin film covering the source electrode; patterning the semiconductor thin film to form the drain electrode and the conductive channel; the orthographic projection of the drain electrode on the substrate and the orthographic projection of the conductive channel on the substrate both overlap with the orthographic projection of the source electrode on the substrate.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, the etching and removing the active regions within the gaps and the active regions between adjacent columnar structures within the same active region to form bit line trenches includes: forming a first sacrificial layer covering the exposed surfaces of the columnar structures and the exposed surface of the substrate; patterning the first sacrificial layer and etching and removing the active regions within the gaps and the active regions between adjacent columnar structures within the same active region based on the pattern of the first sacrificial layer; removing the first sacrificial layer.

4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, before forming the bit line trenches, further comprising: forming a contact plug on the drain electrode; after forming a bit line within the bit line trenches that surrounds and contacts the source electrode, further comprising: forming a first dielectric material layer covering the bit line, the conductive channel, the drain electrode, and the contact plug; forming a surround gate word line corresponding to surround the conductive channel on a surface of the first dielectric material layer facing away from the conductive channel; there is an air gap between adjacent surround gate word lines; forming a second dielectric material layer covering the surround gate word line on a surface of the first dielectric material layer facing away from the contact plug; etching the second dielectric material layer and the first dielectric material layer to obtain a first dielectric layer and a second dielectric layer, and the first dielectric layer and the second dielectric layer expose the contact plug.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, Forming a surround gate word line corresponding to surround the conductive channel on a surface of the first dielectric material layer facing away from the conductive channel includes: Depositing a metal material on the first dielectric material layer; Etching the metal material until an upper surface of the metal material is flush with an upper surface of the columnar structure or the upper surface of the metal material is lower than the upper surface of the columnar structure, to obtain a metal pattern layer; Forming a second sacrificial layer covering an exposed surface of the first dielectric material layer and the metal pattern layer; Patterning the second sacrificial layer, and etching the metal pattern layer based on a pattern of the second sacrificial layer, to obtain a surround gate word line corresponding to surround the conductive channel; Removing the second sacrificial layer.

6. The method for manufacturing a semiconductor structure according to claim 5, wherein, the metal material includes tungsten metal.

7. The method for manufacturing a semiconductor structure according to claim 4, wherein, before etching the second dielectric material layer and the first dielectric material layer, further includes: forming a third dielectric material layer on the second dielectric material layer; and forming a plurality of contact windows in the third dielectric material layer to obtain a third dielectric layer; etching the second dielectric material layer and the first dielectric material layer to obtain a first dielectric layer and a second dielectric layer, where the first dielectric layer and the second dielectric layer expose the contact plug includes: etching the second dielectric material layer and the first dielectric material layer based on the contact windows to obtain the first dielectric layer and the second dielectric layer, where the first dielectric layer and the second dielectric layer expose the contact plug; after etching the second dielectric material layer and the first dielectric material layer to obtain a first dielectric layer and a second dielectric layer, where the first dielectric layer and the second dielectric layer expose the contact plug, further includes: forming a contact pad in the contact window in contact with the contact plug.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein, forming a contact pad in the contact window in contact with the contact plug includes: forming a pad material layer in the contact window and on a surface of the third dielectric layer; using a chemical mechanical polishing process to remove the pad material layer located on the surface of the third dielectric layer, and the pad material layer remaining in the contact window is the contact pad.

9. The method for manufacturing a semiconductor structure according to claim 4, wherein, the material of the bit line and / or the contact plug includes bismuth metal.

10. The method for manufacturing a semiconductor structure according to any one of claims 1 to 9, wherein, the material of the columnar structure includes molybdenum disulfide.

11. A semiconductor structure, wherein, includes: a substrate, on which a shallow trench isolation structure is formed, and the shallow trench isolation structure isolates a plurality of spaced active regions in the substrate; a transistor accommodation groove, located in the active region and having a space from the shallow trench isolation structure; A columnar structure, located within the transistor accommodation groove, comprising: a source electrode, a conductive channel, and a drain electrode sequentially arranged in a direction away from the substrate; And a bit line, located within the interval and surrounding and contacting the source electrode.

12. The semiconductor structure according to claim 11, Characterized in that, The material of the columnar structure includes molybdenum disulfide; And / or, the material of the bit line includes bismuth metal.

13. The semiconductor structure according to claim 11, Characterized in that, The semiconductor structure further includes: A contact plug, located on the surface of the drain electrode facing away from the conductive channel; A first dielectric layer, covering the bit line and located on the sidewalls of the conductive channel, the drain electrode, and the contact plug; A surround gate word line, located on the surface of the first dielectric layer facing away from the conductive channel and surrounding the conductive channel; A second dielectric layer, located on the surface of the first dielectric layer facing away from the contact plug and covering the surround gate word line; Wherein, there is an air gap between adjacent surround gate word lines.

14. The semiconductor structure according to claim 13, Characterized in that, The semiconductor structure further includes: A third dielectric layer, having a contact window and at least covering the second dielectric layer; A contact pad, located within the contact window and in contact with the contact plug.

15. The semiconductor structure according to claim 13, Characterized in that, The material of the contact plug includes bismuth metal.

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