Semiconductor Structure and Method of Manufacturing the Same

Abstract

An embodiment of the present application provides a method for manufacturing a semiconductor structure, the method comprising: forming a first trench in a semiconductor substrate; wherein the first trench penetrates through the conductive channels of at least two transistors; at least part of the conductive channels are located at the bottom of the first trench; an oxide layer is provided between adjacent conductive channels; the conductive channels have a raised structure relative to the oxide layer within the first trench; by etching at the bottom of the first trench, the shape of the raised structure of each conductive channel at the bottom of the first trench is adjusted such that the raised structure has at least two protruding portions; and forming a gate structure within the first trench.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and relates to, but is not limited to, a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Transistors are widely used as switching devices or driving devices in electronic devices. For example, transistors can be used in a Dynamic Random Access Memory (DRAM) to control the capacitors in each memory cell, and a transistor array composed of multiple transistors can be used in a semiconductor memory device.

[0003] In the related art, when the word line (WL) of a transistor is powered on, it can make the two ends of the transistor conductive. The speed at which the word line turns on affects the working efficiency of the transistor, thereby further affecting the working efficiency of the semiconductor memory device. Summary of the Invention

[0004] In view of this, embodiments of this application provide a semiconductor structure and a manufacturing method thereof.

[0005] In a first aspect, embodiments of this application provide a manufacturing method of a semiconductor structure, and the method includes:

[0006] Form a first trench on a semiconductor substrate; wherein, the first trench penetrates through the conductive channels of at least two transistors; at least part of the conductive channels is located at the bottom of the first trench; there is an oxide layer between adjacent conductive channels; the conductive channels have a convex structure relative to the oxide layer within the first trench;

[0007] By etching at the bottom of the first trench, adjust the shape of the convex structure of each conductive channel at the bottom of the first trench so that the convex structure has at least two protruding parts;

[0008] Form a gate structure within the first trench.

[0009] In some embodiments, the step of by etching at the bottom of the first trench, adjust the shape of the convex structure of each conductive channel at the bottom of the first trench so that the convex structure has at least two protruding parts includes:

[0010] Form a first insulating layer at the bottom of the first trench; wherein, the thickness of the first insulating layer is less than or equal to the height of the convex structure protruding relative to the oxide layer;

[0011] Etch the convex structure and the first insulating layer to form a concave region at the center of the convex structure;

[0012] Etch the raised structure and the oxide layer having the recessed area to form two of the protruding portions.

[0013] In some embodiments, forming the first insulating layer at the bottom of the first trench includes:

[0014] Fill the first trench with an insulating material;

[0015] Perform a planarization process on the insulating material to form the first insulating layer.

[0016] In some embodiments, etching the raised structure and the first insulating layer to form a recessed area at the center of the raised structure includes:

[0017] Etch from the top of the raised structure to form the recessed area that is lower than the surface of the first insulating layer;

[0018] The method further includes: removing the first insulating layer.

[0019] In some embodiments, etching the recessed structure and the oxide layer to form two of the protruding portions includes:

[0020] At a predetermined etching rate, synchronously etch the recessed area and the oxide layer to form two of the protruding portions on two sides of the raised structure adjacent to the oxide layer.

[0021] In some embodiments, the gate structure includes: a gate oxide layer and a gate conductive layer; forming the gate structure in the first trench includes:

[0022] Form the gate oxide layer covering the raised structure in the first trench;

[0023] In the first trench covered with the gate oxide layer, form the gate conductive layer.

[0024] In some embodiments, the gate conductive layer includes: a first conductive layer and a second conductive layer; forming the gate conductive layer in the first trench covered with the gate oxide layer includes:

[0025] Cover the bottom of the first trench covered with the gate oxide layer with a first conductive material to form the first conductive layer;

[0026] Fill the first trench covered with the first conductive material with a second conductive material to form the second conductive layer.

[0027] In some embodiments, the thickness of the gate structure is less than the depth of the first trench; after forming the gate structure in the first trench, the method further includes:

[0028] Fill the first trench covered with the second conductive material with a dielectric material to form an isolation layer.

[0029] In some embodiments, before forming the first trench in the semiconductor substrate, the method further includes:

[0030] Form a second trench in the semiconductor substrate;

[0031] Fill the second trench with an oxide to form the oxide layer between the adjacent conductive channels.

[0032] In some embodiments, forming the second trench in the semiconductor substrate includes:

[0033] Place a mask on the conductive channel region of the transistor;

[0034] Etch the semiconductor substrate outside the mask region to form the second trench.

[0035] On the other hand, an embodiment of the present application provides a semiconductor structure, including:

[0036] A semiconductor substrate; wherein, the semiconductor substrate has a first trench penetrating through the conductive channels of at least two transistors; a gate structure is disposed in the first trench;

[0037] The conductive channels of at least two transistors; at least a part of the conductive channels is located at the bottom of the first trench; an oxide layer is disposed between the adjacent conductive channels; the conductive channels have a raised structure relative to the oxide layer in the first trench; wherein, the raised structure has at least two protruding portions.

[0038] In some embodiments, at least two of the protruding portions are located on two sides of the raised structure adjacent to the oxide layer.

[0039] In some embodiments, the gate structure includes:

[0040] A gate oxide layer, disposed in the first trench, covering the raised structure;

[0041] A gate conductive layer, disposed in the first trench, covering the gate oxide layer.

[0042] In some embodiments, the gate conductive layer includes:

[0043] A first conductive layer, disposed in the first trench covering the gate oxide layer, covering the bottom of the first trench;

[0044] A second conductive layer, disposed in the first trench, covering the first conductive layer.

[0045] In some embodiments, the thickness of the gate structure is less than the depth of the first trench; the semiconductor structure further includes: an isolation layer located in the first trench and covering the second conductive layer.

[0046] Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof. The method etches a convex structure at the bottom of the first trench to make the convex structure have at least two protruding portions, and covers a gate structure on the convex structure. This can increase the contact area between the conductive channel and the gate structure, thereby increasing the current flow area, improving the conductivity of the transistor, and enhancing the working efficiency of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 is a flowchart of a manufacturing method of a semiconductor structure provided by an embodiment of the present application;

[0048] Figures 2A to 2C is a schematic diagram and a partial cross-sectional view of forming a first trench in the manufacturing method provided by an embodiment of the present application;

[0049] Figure 3 is a schematic structural diagram of forming a first insulating layer in the manufacturing method provided by an embodiment of the present application;

[0050] Figure 4 is a schematic structural diagram of filling an insulating material in the manufacturing method provided by an embodiment of the present application;

[0051] Figure 5 is a schematic structural diagram of forming a recessed area in the manufacturing method provided by an embodiment of the present application;

[0052] Figure 6 is a schematic structural diagram of removing the first insulating layer in the manufacturing method provided by an embodiment of the present application;

[0053] Figure 7 is a schematic structural diagram of forming a protruding portion in the manufacturing method provided by an embodiment of the present application;

[0054] Figure 8 is a schematic structural diagram of forming a gate structure in the manufacturing method provided by an embodiment of the present application;

[0055] Figure 9 is a schematic structural diagram of forming an isolation layer in the manufacturing method provided by an embodiment of the present application;

[0056] Figure 10A and Figure 10B is a schematic diagram of a semiconductor structure provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0057] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0059] In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, as Figure 1 shown, the method comprising:

[0060] Step S101, forming a first trench on a semiconductor substrate; wherein, the first trench penetrates through the conductive channels of at least two transistors; at least part of the conductive channels is located at the bottom of the first trench; an oxide layer is provided between adjacent conductive channels; the conductive channels have a protruding structure relative to the oxide layer within the first trench;

[0061] Step S102, by etching at the bottom of the first trench, adjusting the shape of the protruding structure of each conductive channel at the bottom of the first trench so that the protruding structure has at least two protruding portions;

[0062] Step S103, forming a gate structure within the first trench.

[0063] In the embodiment of the present application, the first trench can be formed on the substrate surface by a patterning etching method. The first trench is used to form a gate structure, and the gate structure can penetrate the entire semiconductor structure, so it can be used as a word line in the semiconductor structure. Since the gate structure is buried within the first trench rather than covering the substrate surface, this structure is also called a buried word line (BWL, Buried Word Line). Here, there can be multiple first trenches, and they are distributed in parallel on the substrate. Exemplarily, the multiple first trenches can be parallel to each other and have equal spacing, depth, and width. Therefore, multiple first trenches can be formed synchronously by etching. Of course, the above first trench can be formed by one etching or by multiple etchings using multiple exposure techniques.

[0064] As Figures 2A to 2C shown, wherein, Figure 2B is Figure 2ACross-sectional view on the aa' section Figure 2C is Figure 2A Cross-sectional view on the bb' section in [the relevant context]. A first trench 110 is formed in the substrate 100. The bottom of the first trench 110 has conductive channels 120 of at least two transistors. In addition, a raised structure 121 is provided at the top of the conductive channel 120. The raised structure can be an ellipsoidal protrusion, a spherical protrusion, a columnar protrusion, etc. And an oxide layer 130 is provided between the conductive channels 120. The material of the oxide layer 130 can be silicon dioxide (SiO2), aluminum oxide (Al2O3), or other oxide materials, etc. Two adjacent conductive channels 120 are separated by the oxide layer 130, and the height of the conductive channel 120 is more than the height of a raised structure 121 with respect to the thickness of the oxide layer 130.

[0065] It should be noted that each first trench 110 penetrates through the conductive channels 120 of at least two transistors. That is to say, the raised structures 121 at the tops of multiple conductive channels 120 are located at the bottom of the first trench 110. In addition, the top of the above-mentioned oxide layer 130 is also exposed at the bottom of the first trench 110.

[0066] After forming the first trench, an etching process can be performed at the bottom of the first trench to adjust the above-mentioned raised structure, including but not limited to plasma etching, wet etching, photolithography, etc. Exemplarily, multiple raised structures can be adjusted synchronously. Here, the adjustment refers to controlling parameters such as the etching rate and the etching angle, so that a raised structure with an integral shape forms at least two separate-shaped protrusions. It should be noted that the shape of each protrusion can be the same as or different from the raised structure, and the shapes of the two protrusions can also be the same as or different from each other.

[0067] Finally, in the embodiments of the present application, a gate structure can be formed inside the first trench by deposition to cover the raised structure of the above-mentioned conductive channel. For example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc.

[0068] Through the above method of the embodiments of the present application, the raised structure is adjusted by etching to form at least two protrusions. When the gate structure is covered on the protrusions, the contact area between the gate and the conductive channel can be made larger, so that the current flow area can be increased during conduction, improving the conductivity of the transistor and enhancing the working efficiency of the semiconductor structure.

[0069] In some embodiments, by etching at the bottom of the first trench, the shape of the raised structure of each conductive channel at the bottom of the first trench is adjusted so that the raised structure has at least two protruding portions, including:

[0070] Form a first insulating layer at the bottom of the first trench; wherein, the thickness of the first insulating layer is less than or equal to the height of the raised structure relative to the raised oxide layer;

[0071] Etch the raised structure and the first insulating layer to form a concave region at the center of the raised structure;

[0072] Etch the raised structure with the concave region and the oxide layer to form two of the protruding portions.

[0073] As Figure 3 shown, it is a cross-sectional view of the structure in Figure 2B after the first insulating layer is formed. In the embodiments of the present application, the first insulating layer 140 can be formed at the bottom of the first trench 110 by deposition, including but not limited to CVD, ALD, or PVD, etc. It should be noted that the height of the raised structure 121 relative to the oxide layer 130 is the height of the raised structure 121 at the bottom of the first trench 110. Therefore, the first insulating layer 140 here is used to cover the oxide layer 130 and space apart the raised structures 121 at the bottom of the first trench 110 from each other. Exemplarily, when the thickness of the first insulating layer is less than the height of the raised structure at the bottom of the first trench, the top of the raised structure is still partially exposed at the bottom of the first trench; when the thickness of the first insulating layer is equal to the height of the raised structure at the bottom of the first trench, the adjacent raised structures are exactly completely spaced apart by the above-mentioned first insulating layer.

[0074] After the first insulating layer is formed, in the embodiments of the present application, one or more of processes such as plasma etching, wet etching, or photolithography can be used to etch the above-mentioned first insulating layer and the raised structure to form a concave region at the center of the raised structure. For example, a spherical or ellipsoidal region with a smaller volume depression is formed at the center of an ellipsoidal or spherical raised structure, so that the peripheral region of the raised structure forms a protruding tip, thereby adjusting the shape of the raised structure.

[0075] Then, the adjusted raised structure and the oxide layer can be selectively etched by etching, so that the tip on the raised structure can be further adjusted to form the shape of the required protruding portion.

[0076] In the embodiments of the present application, the processes of forming the first insulating layer and etching can be carried out uniformly, which can reduce the process steps and improve the product yield.

[0077] In some embodiments, forming the first insulating layer at the bottom of the first trench includes:

[0078] Filling the first trench with an insulating material;

[0079] Performing a planarization process on the insulating material to form the first insulating layer.

[0080] The insulating material involved in the embodiments of the present application may be silicon nitride (SiN), silicon oxide, or other insulating materials, etc. As Figure 4 shown, it is a cross-sectional view of the structure in Figure 2B after filling the insulating material. The above insulating material 141 can be filled in the first trench 110 by methods such as CVD, ALD, or PVD. Here, the first insulating material 141 completely covers the top of the oxide layer 130 and the protruding structure 121.

[0081] After filling the insulating material, the above insulating material can be planarized by Chemical Mechanical Polishing (CMP) to form the first insulating layer. Exemplarily, first, the first insulating material reacts with the oxidant, catalyst, etc. in the polishing liquid to generate a soft layer that is relatively easy to remove. Then, the soft layer is removed under the mechanical action of the abrasive in the polishing liquid and the polishing pad, so that the polished first insulating material is exposed again. Repeat the above steps until a predetermined thickness of the first insulating material is removed to form the above first insulating layer.

[0082] In some embodiments, etching the protruding structure and the first insulating layer to form a concave region at the center of the protruding structure includes:

[0083] Etching from the top of the protruding structure to form the concave region that is lower than the surface of the first insulating layer;

[0084] The method further includes: removing the first insulating layer.

[0085] As Figure 5 shown, it is a cross-sectional view of the structure in Figure 4 after forming the concave region. The concave region 122 with a specific shape can be formed by selectively etching from the top of the protruding structure 121, and by controlling the etching rate, at least two protruding tips 123 are formed on both sides of the concave region 122. Since the protruding structure is selectively etched, the formed concave is lower than the surface of the first insulating layer.

[0086] Next, as Figure 6 shown, it is for Figure 5Cross-sectional view of the structure after removing the first insulating layer. Then, the first insulating layer 140 is removed by a selective etching method to form a raised structure 120 with a recessed area 122, and at the same time, the oxide layer 130 is exposed at the bottom of the first trench 110. It should be noted that the raised structure 120 here has formed two protruding tips 123 after the previous etching step.

[0087] In some embodiments, etching the recessed structure and the oxide layer to form the two protruding portions includes:

[0088] Etching the recessed area and the oxide layer synchronously at a predetermined etching rate to form the two protruding portions on two sides of the raised structure adjacent to the oxide layer.

[0089] Due to multiple previous etching processes, the raised structure of the conductive channel may have losses, resulting in a decrease in height. Therefore, as Figure 7 shown, for Figure 6 the cross-sectional view of the structure after forming the protruding portions. A predetermined etching rate can be set to first etch the oxide layer 130 synchronously, exposing a part of the height of the raised structure 120; then, by controlling the etching rate and etching angle, the two protruding tips 123 are rounded to form the two above-mentioned protruding portions 124. Here, the protruding portions 124 are located on one side of the raised structure 120 adjacent to the oxide layer 130.

[0090] Embodiments of the present application can form the protruding portions by adjusting the etching rate. The process steps are simple and easy to operate. After the rounding process, protruding portions with a larger surface area can be formed, which can increase the contact area with the gate structure in subsequent processes.

[0091] In some embodiments, the gate structure includes: a gate oxide layer and a gate conductive layer; forming the gate structure in the first trench includes:

[0092] Forming the gate oxide layer covering the raised structure in the first trench;

[0093] Forming the gate conductive layer in the first trench covered with the gate oxide layer.

[0094] The gate oxide layer in the embodiments of the present application can be formed by oxidizing the surface of the above-mentioned raised structure. The gate oxide layer covers the outer surface of the raised structure and is connected to the oxide layers on both sides of the raised structure, and is used to electrically isolate the conductive channel from the subsequently formed gate conductive layer.

[0095] After forming the gate oxide layer, a gate conductive layer can be formed on the gate oxide layer in the first trench by deposition methods such as CVD, ALD, or PVD. The material of the gate conductive layer can be a metal, a semiconductor, or other conductive materials, etc. Exemplarily, the gate conductive layer can be formed synchronously and can have equal depth and width in the first trench.

[0096] In the embodiment of the present application, the gate structure is buried in the first trench and covers at least two protrusions on the protrusion structure, increasing the contact area between the conductive channel and the gate structure, and improving the conductivity of the semiconductor structure.

[0097] In some embodiments, the gate conductive layer includes: a first conductive layer and a second conductive layer; forming the gate conductive layer in the first trench covered with the gate oxide layer includes:

[0098] Covering the bottom of the first trench covered with the gate oxide layer with a first conductive material to form the first conductive layer;

[0099] Filling the first trench covered with the first conductive material with a second conductive material to form the second conductive layer.

[0100] In the embodiment of the present application, as Figure 8 shown, it is a cross-sectional view of the structure after forming the gate structure in Figure 7 . The gate structure 150 can be divided into a gate oxide layer 151 and a gate conductive layer 152, and the gate conductive layer 152 can be further divided into a first conductive layer 152a and a second conductive layer 152b. Among them, the first conductive layer 152a covers the gate oxide layer 151, the second conductive layer 152b covers the first conductive layer 152a, and the thickness of the second conductive layer 152b can be greater than the thickness of the first conductive layer 152a.

[0101] Exemplarily, a first conductive material can be covered on the bottom of the first trench covering the gate oxide layer by a deposition method. The first conductive material here can be a stable and conductive compound, such as titanium nitride (TiN). Titanium nitride has good chemical stability and high thermal shock resistance and conductivity. Then, a second conductive material can be filled in the first trench covering the first conductive material by a deposition method. The second conductive material here can be a metal, such as tungsten (W), nickel (Ni), or molybdenum (Mo), etc.

[0102] In the embodiment of the present application, a compound with better chemical stability and higher conductivity is covered on the gate oxide layer to form the first conductive layer, and a metal is covered on the first conductive layer to form the second conductive layer. The gate conductive layer is constituted by the first conductive layer and the second conductive layer. In this way, the conductivity of the semiconductor structure can be improved, the loss of the conductive channel can be reduced, and the yield of the product can be increased.

[0103] In some embodiments, the thickness of the gate structure is less than the depth of the first trench; after forming the gate structure in the first trench, the method further includes:

[0104] Filling a dielectric material in the first trench covered with the second conductive material to form an isolation layer.

[0105] As Figure 9 shown, it is a cross-sectional view of the structure in Figure 8 after forming the isolation layer. After the gate structure 150 is formed, if the thickness of the gate structure 150 is less than the depth of the first trench 110, the first trench 110 can be filled by depositing a dielectric material, thereby forming the isolation layer 160. The dielectric material here may include but is not limited to silicon nitride, silicon oxynitride (SiON), or other dielectric materials, etc. Exemplarily, the first isolation layer 160 can be formed synchronously in multiple first trenches 110 and have equal depth and width.

[0106] In some embodiments, before forming the first trench in the semiconductor substrate, the method further includes:

[0107] Forming a second trench in the semiconductor substrate;

[0108] Filling an oxide in the second trench to form the oxide layer between adjacent conductive channels.

[0109] In the embodiments of the present application, a second trench can be first formed on the substrate surface by a patterning etching method, and the oxide layer is formed in the second trench. Here, the conductive channels of the semiconductor structure are formed between two adjacent second trenches. Exemplarily, there may be multiple second trenches, and they are parallelly distributed on the substrate. The multiple second trenches can be parallel to each other and have equal spacing, depth, and width. Therefore, multiple second trenches can be formed synchronously by etching. Of course, the above-mentioned second trenches can be formed by one etching, or can be formed by multiple etching using multiple exposure techniques.

[0110] After forming the second trench, an oxide such as silicon oxide, aluminum oxide, or other oxide materials can be filled in the second trench by methods such as CVD, ALD, or PVD. The thickness of the oxide layer formed after filling the oxide is less than the height of the conductive channel, and the conductive channel has a convex structure relative to the oxide layer. Here, the oxide layer electrically isolates two adjacent conductive channels.

[0111] In some embodiments, forming the second trench in the semiconductor substrate includes:

[0112] Placing a mask on the conductive channel region of the transistor;

[0113] Etch the semiconductor substrate outside the mask region to form the second trench.

[0114] In the embodiments of the present application, a patterned buried layer may be placed on the region where the conductive channel of the transistor needs to be formed. This mask is used to protect the semiconductor substrate within the buried region from being etched during subsequent etching processes. Then, an etching operation is performed on the semiconductor substrate outside the mask region, such as plasma etching, wet etching, or photolithography. This etching process can be carried out uniformly, and the depth of the second trench can be controlled by controlling the etching time. Finally, multiple second trenches can be formed on the semiconductor substrate.

[0115] As Figure 10A and Figure 10B shown, where Figure 10B is Figure 10A a schematic diagram of the cross-section along aa' in

[0116] The embodiments of the present application also provide a semiconductor structure 1000, including:

[0117] A semiconductor substrate 1100; wherein, a first trench 1300 penetrating through the conductive channels 1200 of at least two transistors is formed on the semiconductor substrate 1100; a gate structure 1400 is disposed within the first trench 1300;

[0118] The conductive channels 1200 of at least two transistors; at least a part of the conductive channels 1200 is located at the bottom of the first trench 1300; an oxide layer 1500 is provided between adjacent conductive channels 1200; the conductive channels 1200 have a raised structure 1210 relative to the oxide layer 1500 within the first trench 1300; wherein, the raised structure 1210 has at least two protruding portions 1211 and 1212.

[0119] In the embodiments of the present application, the semiconductor substrate may be a silicon substrate. The conductive channels and the oxide layer on the semiconductor substrate are distributed at intervals, and adjacent two conductive channels are electrically isolated by the oxide layer. Among them, the height of the conductive channel is greater than the thickness of the oxide layer. Therefore, the conductive channel has a raised structure relative to the oxide layer. In addition, the first trench is located above the conductive channel and the oxide layer, the above-mentioned raised structure is located at the bottom of the conductive channel, the top of the above-mentioned oxide layer is exposed within the first trench, and the gate structure within the first trench covers the raised structure and the oxide layer.

[0120] The protruding structure in the embodiment of the present application further includes at least two protruding portions, and the contact area of these two protruding portions with the above-mentioned gate structure is larger than the contact area of a single protruding structure of the same shape with the gate structure. Therefore, the current can flow through the above two protruding portions, and the flow area is increased, thereby improving the conductivity of the transistor and enhancing the working efficiency of the semiconductor structure.

[0121] In some embodiments, at least two of the protruding portions are located on two sides of the protruding structure adjacent to the oxide layer.

[0122] At least two protruding portions in the embodiment of the present application can be formed integrally and have the same height, width or shape. Therefore, at least two protruding portions on the same protruding structure can be connected to each other and are located on two sides of the protruding structure adjacent to the oxide layer. Exemplarily, there can be two ellipsoidal protruding portions on the protruding structure, and there is a "valley" connecting the two protruding portions, and the two sides of the two protruding portions opposite to the "valley" are connected to the oxide layers on both sides of the conductive channel.

[0123] In some embodiments, the gate structure includes:

[0124] A gate oxide layer, located in the first trench and covering the protruding structure;

[0125] A gate conductive layer, located in the first trench and covering the gate oxide layer.

[0126] In the embodiment of the present application, the gate oxide layer can be composed of an oxide, such as silicon oxide, aluminum oxide or other oxidation materials, and the gate oxide layer is located at the bottom of the first trench, covers the protruding structure and is connected to the above-mentioned oxide layer, and is used to electrically isolate the protruding structure from the gate conductive layer. The gate conductive layer can be composed of a conductive material, such as a metal, a semiconductor or other conductive materials, and the gate conductive layer can be used to provide a word line voltage to turn the word line on or off.

[0127] In some embodiments, the gate conductive layer includes:

[0128] A first conductive layer, located in the first trench covering the gate oxide layer and covering the bottom of the first trench;

[0129] A second conductive layer, located in the first trench and covering the first conductive layer.

[0130] The gate conductive layer in the embodiments of the present application can be composed of two different conductive materials. Among them, the first conductive layer can be composed of a conductive compound, such as titanium nitride, which has good chemical stability and high conductivity; the second conductive layer can be composed of a metal material, such as tungsten, nickel or molybdenum, etc., which are common materials for forming word lines, with low cost and good conductivity. Here, the first conductive layer covers the gate oxide layer and the oxide layer, the second conductive layer covers the first conductive layer, and the thickness of the first conductive layer can be less than the thickness of the second conductive layer.

[0131] In some embodiments, the thickness of the gate structure is less than the depth of the first trench; the semiconductor structure further includes: an isolation layer located in the first trench and covering the second conductive layer.

[0132] In the embodiments of the present application, the isolation layer can be composed of a dielectric material, such as silicon nitride, silicon oxynitride or other dielectric materials, etc. The isolation layer is located on the gate structure in the first trench, specifically, covering the second conductive layer of the gate structure.

[0133] It should be noted that the features disclosed in several method or device embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0134] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A manufacturing method of a semiconductor structure, characterized in that, The method includes: forming a first trench in a semiconductor substrate; wherein, the first trench penetrates through the conductive channels of at least two transistors; at least part of the conductive channels are located at the bottom of the first trench; an oxide layer is provided between adjacent conductive channels; the conductive channels have a convex structure relative to the oxide layer within the first trench; by etching at the bottom of the first trench, adjusting the shape of the convex structure of each conductive channel at the bottom of the first trench such that the convex structure has at least two protruding portions; forming a gate structure within the first trench.

2. The method according to claim 1, characterized in that The step of by etching at the bottom of the first trench, adjusting the shape of the convex structure of each conductive channel at the bottom of the first trench such that the convex structure has at least two protruding portions includes: forming a first insulating layer at the bottom of the first trench; wherein, the thickness of the first insulating layer is less than or equal to the height by which the convex structure protrudes relative to the oxide layer; etching the convex structure and the first insulating layer to form a concave region at the center of the convex structure; etching the convex structure having the concave region and the oxide layer to form two protruding portions.

3. The method according to claim 2, characterized in that The step of forming a first insulating layer at the bottom of the first trench includes: filling the first trench with an insulating material; performing a planarization process on the insulating material to form the first insulating layer.

4. The method according to claim 2, wherein The step of etching the convex structure and the first insulating layer to form a concave region at the center of the convex structure includes: etching from the top of the convex structure to form the concave region that is lower than the surface of the first insulating layer; The method further includes: removing the first insulating layer.

5. The method according to claim 2, characterized in that, The step of etching the concave region and the oxide layer to form two protruding portions includes: etching the concave region and the oxide layer synchronously at a predetermined etching rate to form two protruding portions on two sides of the convex structure adjacent to the oxide layer.

6. The method according to claim 1, wherein The gate structure includes: a gate oxide layer and a gate conductive layer; the step of forming a gate structure within the first trench includes: forming the gate oxide layer covering the convex structure within the first trench; forming the gate conductive layer within the first trench covered with the gate oxide layer.

7. The method according to claim 6, characterized in that, The gate conductive layer includes: a first conductive layer and a second conductive layer; the step of forming the gate conductive layer within the first trench covered with the gate oxide layer includes: covering a first conductive material at the bottom of the first trench covered with the gate oxide layer to form the first conductive layer; filling a second conductive material within the first trench covered with the first conductive material to form the second conductive layer.

8. The method according to claim 7, characterized in that The thickness of the gate structure is less than the depth of the first trench; after forming the gate structure within the first trench, the method further includes: filling a dielectric material within the first trench covered with the second conductive material to form an isolation layer.

9. The method according to claim 1, wherein Before forming the first trench in the semiconductor substrate, the method further includes: forming a second trench in the semiconductor substrate; Fill the second trench with an oxide to form the oxide layer between the adjacent conductive channels.

10. The method according to claim 9, characterized in that, Forming the second trench on the semiconductor substrate includes: Placing a mask on the conductive channel region of the transistor; Etching the semiconductor substrate outside the mask region to form the second trench.

11. A semiconductor structure formed by the method according to any one of claims 1-10, characterized in that, Comprising: A semiconductor substrate; wherein, the semiconductor substrate has a first trench penetrating through the conductive channels of at least two transistors; a gate structure is disposed in the first trench; The conductive channels of at least two transistors; at least a part of the conductive channels is located at the bottom of the first trench; an oxide layer is provided between the adjacent conductive channels; the conductive channels have a raised structure relative to the oxide layer in the first trench; wherein, the raised structure has at least two protruding portions.

12. The semiconductor structure according to claim 11, wherein At least two of the protruding portions are located on two sides of the raised structure adjacent to the oxide layer.

13. The semiconductor structure according to claim 11, wherein, The gate structure includes: A gate oxide layer, disposed in the first trench and covering the raised structure; A gate conductive layer, disposed in the first trench and covering the gate oxide layer.

14. The semiconductor structure according to claim 13, wherein The gate conductive layer includes: A first conductive layer, disposed in the first trench covered with the gate oxide layer and covering the bottom of the first trench; A second conductive layer, disposed in the first trench and covering the first conductive layer.

15. The semiconductor structure according to claim 14, wherein, The thickness of the gate structure is less than the depth of the first trench; the semiconductor structure further includes: an isolation layer, disposed in the first trench and covering the second conductive layer.

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