Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing an initial structure, the initial structure including a substrate and an initial word line structure, and the initial word line structure including an initial conductive structure; forming isolation trenches, and the remaining part of the substrate is isolated by the isolation trenches to form a plurality of mutually independent active region structures, the active region structures covering a first part of the initial word line structure, and the isolation trenches exposing a second part of the initial word line structure; removing a part of the second part of the initial word line structure, and the bottom surface of the initial conductive structure covered by the active region structure is lower than the bottom surface of the initial conductive structure of the remaining second part of the initial word line structure. In the present disclosure, by removing a part of the initial conductive structure located in the isolation trenches, the adjacent interference between the initial conductive structures in the active region structure is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] When a word line in a memory matrix is activated and repeatedly refreshed, it will generate noise or interference to adjacent word lines. Before the memory cells located in adjacent word lines are activated or refreshed, if the activation frequency of the word line is too high, it will cause problems such as charge loss or leakage in adjacent memory cells. Furthermore, it will cause data errors in one or more memory cells located in adjacent word lines. This phenomenon is called the RowHammer Effect. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in the present disclosure. This overview is not intended to limit the scope of protection of the claims.

[0004] The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure.

[0005] A first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the method for manufacturing the semiconductor structure comprising:

[0006] Providing an initial structure, the initial structure comprising a substrate and a plurality of mutually parallel initial word line structures buried in the substrate, the initial word line structures comprising initial conductive structures;

[0007] Removing a part of the substrate and a part of the initial word line structures to form isolation trenches, and the remaining part of the substrate is isolated by the isolation trenches to form a plurality of mutually independent active region structures, the active region structures covering a first part of the initial word line structures, and the isolation trenches exposing a second part of the initial word line structures;

[0008] Removing a part of the initial conductive structures in the second part of the initial word line structures, and the bottom surface of the initial conductive structures covered by the active region structures is lower than the bottom surface of the initial conductive structures of the remaining second part of the initial word line structures.

[0009] According to some embodiments of the present disclosure, the removing a part of the substrate and a part of the initial word line structures comprises:

[0010] Remove partial structures of the first intermediate portion of the substrate and partial portions of the initial word line structure to form an intermediate trench, the intermediate trench exposing a first predetermined portion of the initial conductive structure, and the remaining first intermediate portion of the substrate forming a plurality of independent intermediate structures;

[0011] Remove partial structures of the second intermediate portion of the substrate to form a third trench, the third trench exposing a second predetermined portion of the initial conductive structure, and the remaining second intermediate portion of the substrate and the intermediate structures together constituting a plurality of independent active region structures, and the intermediate trench and the third trench together constituting the isolation trench.

[0012] According to some embodiments of the present disclosure, the initial word line structure further includes an initial barrier structure formed between the substrate and the initial conductive structure;

[0013] The removing partial structures of the first intermediate portion of the substrate and partial portions of the initial word line structure to form an intermediate trench includes:

[0014] Remove the partial structure of the substrate located above the top surface of the initial word line structure to form a first trench, the first trench exposing the top surface of the second portion of the initial word line structure;

[0015] Remove the substrate covering the first predetermined portion of the initial conductive structure and remove the initial barrier structure covering the first predetermined portion of the initial conductive structure to form a second trench, the second trench exposing the first predetermined portion of the initial conductive structure, and the first trench and the second trench together constituting the intermediate trench.

[0016] According to some embodiments of the present disclosure, the remaining substrate above the top surface of the initial word line structure forms a plurality of independently arranged island structures; the removing the substrate covering the first predetermined portion of the initial conductive structure includes:

[0017] Using the island structures and the top surface of the second portion of the initial word line structure as a mask, remove the substrate covering the first predetermined portion of the initial conductive structure.

[0018] According to some embodiments of the present disclosure, the removing partial structures of the second intermediate portion of the substrate includes:

[0019] Using the intermediate structures and the initial word line structure as a mask, partially remove the second intermediate portion of the substrate by a vertical etching process to expose the second predetermined portion of the initial conductive structure.

[0020] According to some embodiments of the present disclosure, the removing partial structures of the second intermediate portion of the substrate further includes:

[0021] Using a lateral etching process, remove a second intermediate portion of the substrate covered by the second portion of the initial word line structure.

[0022] According to some embodiments of the present disclosure, removing a portion of the initial conductive structure in the second portion of the initial word line structure includes:

[0023] Form a first dielectric layer filling the isolation trench, the top surface of the first dielectric layer being flush with the lower surface of the initial word line structure;

[0024] Remove the initial barrier structure covering a second preset portion of the initial conductive structure and the second preset portion of the initial conductive structure in the second portion of the initial word line structure.

[0025] According to some embodiments of the present disclosure, after removing a portion of the initial conductive structure in the second portion of the initial word line structure, it includes:

[0026] Form a second dielectric layer, the second dielectric layer filling the isolation trench, the top surface of the second dielectric layer being flush with the top surface of the active region structure, and the first dielectric layer and the second dielectric layer together form an isolation structure.

[0027] According to some embodiments of the present disclosure, before removing a portion of the first intermediate portion of the substrate and a portion of the initial word line structure and before removing a partial structure of the second intermediate portion of the substrate, it includes:

[0028] Form a protective layer, the protective layer covering at least a first preset portion of the initial conductive structure.

[0029] According to some embodiments of the present disclosure, before removing a portion of the first intermediate portion of the substrate and a portion of the initial word line structure, it includes:

[0030] Form a mask layer, the mask layer covering a portion of the top surface of the initial structure, and the projection of the mask layer on the initial structure is a plurality of island-shaped patterns arranged in a parallel array.

[0031] According to some embodiments of the present disclosure, providing the initial structure includes:

[0032] Provide an initial substrate;

[0033] Remove a portion of the initial substrate to form a word line trench;

[0034] Form an initial gate oxide layer, the initial gate oxide layer covering the word line trench;

[0035] Form an initial blocking structure that covers the initial gate oxide layer;

[0036] Form an initial conductive structure that fills the inside of the initial blocking structure, and the top surface of the initial conductive structure is lower than the top surface of the initial substrate;

[0037] Form an initial insulating structure that covers the top surface of the initial conductive structure, and the top surface of the insulating structure is flush with the top surface of the initial substrate;

[0038] The initial gate oxide layer, the initial blocking structure, the initial conductive structure, and the initial insulating structure form the initial word line structure.

[0039] A second aspect of the present disclosure provides a semiconductor structure, the semiconductor structure includes:

[0040] A substrate, on which a plurality of independently arranged active region structures are provided;

[0041] An isolation structure located between the plurality of active region structures;

[0042] A word line structure, the word line structure includes a conductive structure, the conductive structure includes a contact portion provided in the active region structure and a connection portion provided in the isolation structure, and the bottom surface of the contact portion of the conductive structure is lower than the bottom surface of the connection portion of the conductive structure.

[0043] According to some embodiments of the present disclosure, the word line structure further includes a first blocking structure provided between the contact portion of the conductive structure and the active region structure.

[0044] According to some embodiments of the present disclosure, the word line structure includes an insulating structure that covers the top surface of the contact portion of the conductive structure, and the top surface of the insulating structure is flush with the top surface of the active region structure.

[0045] According to some embodiments of the present disclosure, the word line structure further includes a second blocking structure that at least covers the top surface and side walls of the connection portion of the conductive structure.

[0046] According to some embodiments of the present disclosure, the word line structure further includes a gate oxide layer that covers the side walls and bottom surface of the contact portion of the conductive structure, and the gate oxide layer is provided between the contact portion of the conductive structure and the active region structure.

[0047] In the method for manufacturing a semiconductor structure and the semiconductor structure provided by the embodiments of the present disclosure, removing a part of the initial conductive structure located in the isolation trench reduces the adjacent interference between the initial conductive structures in the active region structure.

[0048] Other aspects will be apparent after reading and understanding the accompanying drawings and the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The drawings incorporated in and constituting a part of this specification illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure. In these drawings, like reference numerals are used to represent like elements. The drawings in the following description are some embodiments of the present disclosure, not all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.

[0050] Figure 1 is a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0051] Figure 2 is a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0052] Figure 3 is a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0053] Figure 4 is a schematic diagram of forming a word line mask on an initial substrate in a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0054] Figure 5 is a schematic diagram of forming a word line trench in an initial substrate in a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0055] Figure 6 is a schematic diagram of an initial structure provided in a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0056] Figure 7 is Figure 6 a cross-sectional view taken along line A-A of

[0057] Figure 8 is Figure 6 a cross-sectional view taken along line B-B of

[0058] Figure 9 is a schematic diagram of forming a mask layer on the top surface of an initial structure in a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0059] Figure 10 is Figure 9 a cross-sectional view of the A-A section of

[0060] Figure 11 is Figure 9 a cross-sectional view of the B-B section of

[0061] Figure 12 a schematic diagram showing the formation of the first trench in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0062] Figure 13 is Figure 12 a cross-sectional view of the A-A section of

[0063] Figure 14 is Figure 12 a cross-sectional view of the B-B section of

[0064] Figure 15 a cross-sectional view of the A-A section of the formation of an intermediate trench in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0065] Figure 16 a cross-sectional view of the B-B section of the formation of an intermediate trench in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0066] Figure 17 a schematic diagram showing the formation of a protective layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0067] Figure 18 is Figure 17 a cross-sectional view of the A-A section of

[0068] Figure 19 is Figure 17 a cross-sectional view of the B-B section of

[0069] Figure 20 a schematic diagram showing the formation of isolation trenches in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0070] Figure 21 is Figure 20 a cross-sectional view of the A-A section of

[0071] Figure 22 is Figure 20 a cross-sectional view of the B-B section of

[0072] Figure 23 a schematic diagram showing the formation of the first dielectric layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0073] Figure 24 isFigure 23 Cross-sectional view of the A-A section.

[0074] Figure 25 is Figure 23 Cross-sectional view of the B-B section.

[0075] Figure 26 Schematic diagram showing the removal of a part of the second part of the initial word line structure in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0076] Figure 27 is Figure 26 Cross-sectional view of the A-A section.

[0077] Figure 28 is Figure 26 Cross-sectional view of the B-B section.

[0078] Figure 29 Cross-sectional view of the A-A section of filling an isolation trench in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0079] Figure 30 Cross-sectional view of the B-B section of filling an isolation trench in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0080] Figure 31 Schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0081] Figure 32 is Figure 31 Cross-sectional view of the A-A section.

[0082] Figure 33 is Figure 31 Cross-sectional view of the B-B section.

[0083] Reference numerals:

[0084] 100, initial structure; 101, initial substrate; 102, word line mask; 102a, word line pattern; 103, word line trench; 110, substrate; 111, first intermediate part of the substrate; 112, second intermediate part of the substrate; 130, isolation trench; 131, first trench; 132, second trench; 133, third trench; 135, intermediate trench;

[0085] 200, initial word line structure; 201, first part of the initial word line structure; 202, second part of the initial word line structure; 210, initial gate oxide layer; 220, initial barrier structure; 230, initial conductive structure; 240, initial insulating structure; 231, first preset part of the initial conductive structure; 232, second preset part of the initial conductive structure; 270, protective layer;

[0086] 300. Isolation structure; 310. First dielectric layer; 320. Second dielectric layer;

[0087] 400. Mask layer; 410. Island-shaped sub-mask;

[0088] 500. Substrate;

[0089] 600. Active region structure;

[0090] 700. Intermediate structure;

[0091] 800. Word line structure; 810. Conductive structure; 811. Contact portion of the conductive structure; 812. Connection portion of the conductive structure; 820. First blocking structure; 830. Gate oxide layer; 840. Insulating structure; 850. Second blocking structure. Detailed implementation manners

[0092] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present disclosure. It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments may be combined with each other arbitrarily.

[0093] In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided. As Figure 1 shown, Figure 1 FIG. shows a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure, Figures 5 - 33 and FIG. is a schematic diagram of each stage of the method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure will be introduced below with reference to Figures 5 - 33 .

[0094] It should be noted that, in the exemplary embodiment of the present disclosure, the A-A direction is the extension direction of the initial word line structure, and the B-B direction is the extension direction of the active region structure.

[0095] In some embodiments, there is no limitation on the semiconductor structure. The semiconductor structure will be introduced below by taking a dynamic random access memory (DRAM) as an example, but some embodiments are not limited thereto. The semiconductor structure in some embodiments may also be other structures.

[0096] As Figure 1 shown, a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure includes the following steps:

[0097] Step S110: Provide an initial structure, which includes a substrate and a plurality of mutually parallel initial word line structures buried in the substrate. The initial word line structures include initial conductive structures.

[0098] As Figure 6 、 Figure 7 、 Figure 8 shown, the substrate 110 may include a semiconductor material, where the semiconductor material may be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds. The plurality of initial word line structures 200 are mutually parallel and are spaced apart from each other in the substrate 110.

[0099] Step S120: Remove a part of the substrate and a part of the initial word line structures to form isolation trenches. The remaining part of the substrate is isolated by the isolation trenches to form a plurality of mutually independent active region structures, and the active region structures cover the first part of the initial word line structures, and the isolation trenches expose the second part of the initial word line structures.

[0100] As Figure 20 、 Figure 21 、 Figure 22 shown, dry etching or wet etching may be used to remove a part of the substrate 110 and a part of the initial word line structures 200 to form isolation trenches 130 in the initial structure 100. The remaining part of the substrate 110 forms a plurality of active region structures 600, and the plurality of active region structures 600 are separated by the isolation trenches 130 and are independently arranged.

[0101] As Figure 20 、 Figure 21 shown, two initial word line structures 200 are disposed in each active region structure 600, and both ends of the active region structure 600 intersect with one initial word line structure 200 respectively. That is, the first part 201 of the initial word line structure 200 is disposed in the active region structure 600 and is covered by the active region structure 600, and the second part 202 of the initial word line structure 200 is exposed in the isolation trench 130. As Figure 20 、 Figure 22 shown, the first parts 201 of the same initial word line structure 200 located in different active region structures 600 are connected together through the second part 202 of the initial word line structure 200.

[0102] Step S130: Remove a part of the initial conductive structures in the second part of the initial word line structures, and the bottom surface of the initial conductive structures covered by the active region structures is lower than the bottom surface of the initial conductive structures of the remaining second part of the initial word line structures.

[0103] As Figure 26 、 Figure 27 、 Figure 28 shown, referring to Figure 20 、Figure 21 , Figure 22 , by dry etching or wet etching the second part 202 of the initial word line structure 200, a part of the initial conductive structure 230 of the second part 202 of the initial word line structure 200 is removed, so that the bottom surface of the first part 201 of the initial word line structure 200 is lower than the bottom surface of the remaining second part 202 of the initial word line structure 200.

[0104] In some embodiments, a semiconductor structure is formed. First, an initial word line structure is formed, and then the initial structure is etched to form an active region structure, adjusting the process sequence of forming the active region structure and the initial word line structure in the semiconductor device. During the process of forming the active region structure, the isolation trenches formed expose the second part of the initial word line structure, providing a process window for removing a part of the second part of the initial word line structure. The second part of the initial word line structure can be etched through the process window to remove a part of the initial conductive structure, so that the bottom surface of the initial conductive structure covered by the active region structure is lower than the initial conductive structure located in the isolation trenches, reducing the volume of the initial conductive structure in the isolation trenches, avoiding the movement of charges in the initial conductive structure covered by the active region structure to the initial conductive structure located in the isolation trenches when the word line structure is in the cut-off state, and reducing the occurrence of the row hammer effect.

[0105] In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided. As Figure 2 shown, a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present disclosure includes the following steps:

[0106] Step S210: Provide an initial structure, where the initial structure includes a substrate and a plurality of mutually parallel initial word line structures buried in the substrate, and the initial word line structures include initial conductive structures.

[0107] The implementation manner of step S210 in some embodiments is the same as that of step S110 in the above embodiments, and will not be elaborated here.

[0108] Step S220: Remove a part of the structure of the first intermediate part of the substrate and a part of the initial word line structure to form an intermediate trench, where the intermediate trench exposes a first preset part of a part of the initial conductive structure, and the remaining first intermediate part of the substrate forms a plurality of independent intermediate structures.

[0109] As Figure 16 , Figure 17 , Figure 18 shown, referring to Figure 6, a dry etching or wet etching process can be used to remove part of the structure of the first intermediate portion 111 of the substrate 110 and part of the initial word line structure 200, forming an intermediate trench 135. The intermediate trench 135 exposes a first preset portion 231 of the initial conductive structure 230. And, in some embodiments, the intermediate trench 135 divides the intermediate structure 700 into a plurality of independently arranged island structures.

[0110] According to an exemplary embodiment of the present disclosure, some embodiments further illustrate step S220 in the above embodiments.

[0111] In some embodiments, the initial word line structure at least includes an initial conductive structure 230 and an initial barrier structure 220 formed between the substrate 110 and the initial conductive structure 230. In some embodiments, the top surface of the initial conductive structure 230 is lower than the top surface of the substrate 110.

[0112] Removing part of the structure of the first intermediate portion of the substrate and part of the initial word line structure to form an intermediate trench includes:

[0113] Step S221: Remove the part of the substrate located above the top surface of the initial conductive structure to form a first trench. The first trench exposes the top surface of the second part of the initial word line structure.

[0114] As Figure 12 、 Figure 13 、 Figure 14 shown, referring to Figure 6 , through a dry etching or wet etching process, remove the part of the substrate 110 located above the top surface of the initial conductive structure 230 to form a first trench 131. The first trench 131 divides the substrate 110 located above the top surface of the initial conductive structure 230 into a plurality of independently arranged island structures. The first trench 131 exposes the top surface of the initial conductive structure 230 of the second part 202 of the initial word line structure 200.

[0115] Step S222: Remove the part of the substrate covering the first preset portion of the initial conductive structure and remove the initial barrier structure covering the first preset portion of the initial conductive structure to form a second trench. The second trench exposes part of the first preset portion of the initial conductive structure. The first trench and the second trench together constitute the intermediate trench.

[0116] As Figure 15 、 Figure 16 shown, referring to Figure 12, using the island structure and the second part 202 of the initial word line structure 200 as a mask, removing part of the substrate 110 and the initial barrier structure 220 covering the first preset part 231 of the initial conductive structure 230 by dry or wet etching, exposing the first preset part 231 of the initial conductive structure 230, and forming a second trench 132. The first trench 131 and the second trench 132 together constitute the intermediate trench 135.

[0117] The height of the first preset part 231 of the initial conductive structure 230 is greater than two-thirds of the height of the second part 202 of the initial word line structure 200. While reducing the adjacent interference of the first part 201 of the initial word line structure 200, the contact resistance between the first preset part 231 of the initial conductive structure 230 and the initial conductive structure 230 covered by the active region structure 600 is taken into account to ensure that the semiconductor structure has good electrical performance.

[0118] Step S230: Form a protective layer that covers at least the first preset part of the initial conductive structure.

[0119] As Figure 17 、 Figure 18 、 Figure 19 shown, referring to Figure 15 、 Figure 16 , the semiconductor structure can be placed in a nitrogen-containing plasma environment to form a protective layer 270 on the surface of the first preset part 231 of the initial conductive structure 230 exposed by the semiconductor structure. In some embodiments, the protective layer 270 also covers the intermediate structure 700.

[0120] In some embodiments, the semiconductor structure is placed in an ion emission environment with a temperature of 600°C to 800°C and a pressure of 1 Pa to 10 Pa, using nitrogen (Nitrogen, N2) or ammonia (Ammonia, NH3) as the nitriding gas, emitting plasma to the semiconductor structure, and the intensity of the plasma is 600 W to 2000 W to form the protective layer 270.

[0121] As Figure 17 、 Figure 18 、 Figure 19 shown, referring to Figure 15 、 Figure 16 , the protective layer 270 covers the surface of the first preset part 231 of the initial conductive structure 230 and the intermediate structure 700 to prevent the first preset part 231 of the initial conductive structure 230 and the intermediate structure 700 from being damaged in subsequent processes, ensuring the integrity of the first preset part 231 of the initial conductive structure 230 and the intermediate structure 700, and improving the yield of the finally formed semiconductor structure.

[0122] Step S240: Remove partial structures of the second intermediate portion of the substrate to form a third trench. The third trench exposes a second preset portion of the initial conductive structure. The remaining second intermediate portion of the substrate and the intermediate structure together constitute a plurality of independent active region structures. The intermediate trench and the third trench together constitute isolation trenches.

[0123] As Figure 20 、 Figure 21 、 Figure 22 shown, referring to Figure 6 、 Figure 17 , continue to use dry etching or wet etching to remove partial structures of the second intermediate portion 112 of the substrate 110 to form a third trench 133. The bottom surface of the third trench 133 is lower than the bottom surface of the initial word line structure 200. The third trench 133 exposes a second preset portion 232 of the initial conductive structure 230.

[0124] Exemplarily, removing partial structures of the second intermediate portion of the substrate to form a third trench includes:

[0125] Step S241: Using the intermediate structure and the initial word line structure as masks, partially remove the second intermediate portion of the substrate by a vertical etching process to expose the second preset portion of the initial conductive structure.

[0126] Referring to Figure 17 , using the intermediate structure 700 and the initial word line structure 200 as masks, dry etch the second intermediate portion 112 of the substrate 110. In some embodiments, with the direction perpendicular to the substrate 110 and perpendicular to the extension direction of the initial word line structure 200 as the vertical direction, the dry etching process for etching the second intermediate portion 112 of the substrate 110 is anisotropic etching, and the etching direction is vertical etching. Etch and remove part of the second intermediate portion 112 of the substrate 110 to expose the second preset portion 232 of the initial conductive structure 230.

[0127] Step S242: Use a lateral etching process to remove the second intermediate portion of the substrate under the second part of the initial word line structure. Use a lateral etching process to remove the second intermediate portion of the substrate covered by the bottom surface of the second part of the initial word line structure.

[0128] After removing part of the second intermediate portion 112 of the substrate 110 in step S241, there is still the second intermediate portion 112 of the substrate 110 covered by the initial word line structure 200 that has not been removed. In some embodiments, with the extension direction of the initial word line structure 200 as the lateral direction, use an anisotropic etching process to etch the second intermediate portion 112 of the substrate 110, and the etching direction is lateral etching. Referring to Figure 20 、 Figure 21 、 Figure 22, the second intermediate portion 112 of the substrate 110 covered by the second portion 202 of the initial word line structure 200 is removed to form a third trench 133.

[0129] In this example, through two anisotropic etching processes, part of the structure of the second intermediate portion 112 of the substrate 110 is removed, and only the second intermediate portion 112 of the substrate 110 covered by the intermediate structure 700 is retained. The retained second intermediate portion 112 of the substrate 110 and the substrate 110 retained in the intermediate structure 700 together form the active region structure 600. The second portion 202 of the initial word line structure 200 is suspended in the third trench 133 (refer to Figure 21 ), which reduces the difficulty of etching the second portion 202 of the initial word line structure 200, and at the same time avoids damaging the active region structure 600 when removing part of the second portion 202 of the initial word line structure 200 and affecting the yield of the semiconductor structure.

[0130] Step S250: Remove part of the initial conductive structure in the second portion of the initial word line structure, and the bottom surface of the first portion of the initial word line structure is lower than the bottom surface of the initial conductive structure of the retained second portion of the initial word line structure.

[0131] In some embodiments, removing part of the initial conductive structure 230 in the second portion 202 of the initial word line structure 200 includes:

[0132] S251: Form a first dielectric layer filled in the isolation trench, and the top surface of the first dielectric layer is flush with the lower surface of the initial word line structure.

[0133] As Figure 23 , Figure 24 , Figure 25 shown, referring to Figure 20 , a low-k dielectric material can be deposited by atomic layer deposition (ALD) or chemical vapor deposition (CVD) to fill part of the isolation trench 130 to form the first dielectric layer 310. The first dielectric layer 310 covers the substrate 110 exposed by the third trench 133, and the top surface of the first dielectric layer 310 is flush with the lower surface of the initial word line structure 200. Exemplarily, the material of the first dielectric layer 310 can be silicon nitride, silicon oxide, or silicon oxynitride.

[0134] S252: Remove the initial barrier structure covering the second preset portion of the initial conductive structure and the second preset portion of the initial conductive structure in the second portion of the initial word line structure.

[0135] As Figure 26 , Figure 27 , Figure 28 shown, referring toFigure 22 , Figure 23 , Figure 24 , the initial word line structure 200 is etched by a dry or wet etching process to remove the initial blocking structure 220 covering the second preset portion 232 of the initial conductive structure 230, exposing the second preset portion 232 of the initial conductive structure 230, and then the second preset portion 232 of the initial conductive structure 230 is etched and removed. Since the first preset portion 231 of the initial conductive structure 230 and the intermediate structure 700 have been covered by the protective layer 270, the first preset portion 231 of the initial conductive structure 230 and the intermediate structure 700 are retained during this etching process.

[0136] Refer to Figure 14 , Figure 16 , both the first preset portion 231 and the second preset portion 232 of the initial conductive structure 230 belong to the second portion 202 of the initial word line structure 200. The first preset portion 231 of the initial conductive structure 230 belongs to the second portion 202 of the initial word line structure 200 retained in step S250. The second preset portion 232 of the initial conductive structure 230 belongs to the second portion 202 of the initial word line structure 122 removed in step S250.

[0137] In some embodiments, before removing the second preset portion 232 of the initial conductive structure 230, a protective layer 270 is first formed on the surfaces of the first preset portion 231 of the initial conductive structure 230 and the intermediate structure 700 that need to be retained, and a first dielectric layer 310 is also formed to cover the substrate 110 exposed by the third trench 133, so as to prevent the first preset portion 231 of the initial conductive structure 230 and the intermediate structure 700 from being damaged by etching, and at the same time avoid the substrate 110 covered by the intermediate structure 700 from being etched and damaged, ensuring the structural integrity of the formed active region structure 600 and improving the yield of the produced semiconductor structure.

[0138] In the semiconductor structure formed in some embodiments, the first portion of the initial word line structure is disposed in the active region structure, the second portion of the retained initial word line structure is disposed in the protective layer, the bottom surface of the first portion of the initial word line structure is lower than the bottom surface of the second portion of the retained initial word line structure, and the contact area between the first portion of the initial word line structure and the second portion of the retained initial word line structure is reduced, reducing the adjacent interference of the first portion of the initial word line structure when the semiconductor structure is in a conducting state.

[0139] As Figure 3 shown, a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present disclosure includes the following steps:

[0140] Step S310: Provide an initial structure, which includes a substrate and a plurality of mutually parallel initial word line structures buried in the substrate. The initial word line structures include initial conductive structures.

[0141] In some embodiments, providing the initial structure includes:

[0142] S311: Provide an initial substrate.

[0143] As Figure 4 shown, the initial substrate 101 may include a semiconductor material, where the semiconductor material may be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds.

[0144] S312: Remove a part of the initial substrate to form word line trenches.

[0145] As Figure 4 shown, form a word line mask 102. The word line mask 102 includes a word line pattern 102a, and the word line pattern 102a exposes a part of the top surface of the initial substrate 101. As Figure 5 shown, referring to Figure 4 , etch and remove a part of the initial substrate 101 according to the word line mask 102 to form a plurality of word line trenches 103 in the initial substrate 101. In some embodiments, the plurality of word line trenches 103 are arranged equidistantly and parallel to each other.

[0146] S313: Form an initial gate oxide layer, and the initial gate oxide layer covers the word line trenches.

[0147] As Figure 7 shown, referring to Figure 5 , gate oxide can be deposited by atomic layer deposition (ALD) or chemical vapor deposition (CVD). The gate oxide covers the word line trenches 103 to form an initial gate oxide layer 210. In some embodiments, the material of the initial gate oxide layer 210 is silicon dioxide.

[0148] S314: Form an initial barrier structure, and the initial barrier structure covers the initial gate oxide layer.

[0149] As Figure 7 shown, referring to Figure 5 , barrier material can be deposited by atomic layer deposition or chemical vapor deposition. The barrier material covers the word line trenches 103 on which the initial gate oxide layer 210 has been deposited to form an initial barrier structure 220. The material of the initial barrier structure 220 can be titanium or a titanium compound, and the material of the initial barrier structure 220 can also be tantalum or a tantalum compound.

[0150] In some embodiments, the material of the initial barrier structure 220 includes titanium nitride. The initial barrier structure 220 of titanium nitride is formed by atomic layer deposition using ammonia (NH3) as the reaction gas or a mixed gas of nitrogen (N2) and hydrogen (H2).

[0151] S315: Form an initial conductive structure that fills the inside of the initial barrier structure, and the top surface of the initial conductive structure is lower than the top surface of the initial substrate.

[0152] As Figure 7 shown, referring to Figure 5 , atomic layer deposition or chemical vapor deposition can be used to fill the word line trench 103 with conductive metal, and part of the conductive metal is removed by etch-back. The remaining conductive metal forms the initial conductive structure 230, and the top surface of the initial conductive structure 230 is lower than the top surface of the initial substrate 101. The material of the initial conductive structure 230 may include metal tungsten (W) or tungsten compounds in some embodiments.

[0153] In some embodiments, the initial conductive structure 230 is formed by etch-back of the conductive metal, and at the same time, the initial barrier structure 220 is etch-back so that the top surface of the initial barrier structure 220 is flush with the top surface of the initial conductive structure 230.

[0154] S316: Form an initial insulating structure that covers the top surface of the initial conductive structure, and the top surface of the initial insulating structure is flush with the top surface of the initial substrate.

[0155] As Figure 7 shown, referring to Figure 5 , chemical vapor deposition or physical vapor deposition (PVD for short) can be used to deposit an insulating material to cover the top surface of the initial conductive structure 230 and fill the word line trench 103 to form the initial insulating structure 240.

[0156] As Figure 6 , Figure 7 , Figure 8 shown, in some embodiments, a plurality of parallel initial word line structures 200 are formed in the initial substrate 101. The plurality of initial word line structures 200 and the remaining initial substrate 101 together form the initial structure 100, and the remaining initial substrate 101 serves as the substrate 110 in the initial structure 100. The initial word line structure 200 includes an initial gate oxide layer 210, an initial barrier structure 220, an initial conductive structure 230, and an initial insulating structure 240.

[0157] Step S320: Form a mask layer that covers a part of the top surface of the initial structure, and the projection of the mask layer on the initial structure is a plurality of island-shaped patterns arranged in a parallel array.

[0158] As Figure 9 , Figure 10 , Figure 11 shown, referring to Figure 6 , Figure 7 , Figure 8 , the mask layer 400 includes a plurality of identical island-shaped sub-masks 410. The plurality of island-shaped sub-masks 410 are identical and arranged in an array and parallel to each other on the top surface of the initial structure 100. In some embodiments, the extending direction of the initial word line structure 200 is the first direction, and the extending direction of the island-shaped sub-mask 410 is the second direction. The first direction and the second direction intersect but are not perpendicular.

[0159] The projection of the island-shaped sub-mask 410 on the initial structure 100 is an island-shaped pattern, and both ends of each island-shaped pattern intersect with an initial word line structure 200 respectively.

[0160] Step S330: Remove partial structures of the first intermediate portion of the substrate and partial initial word line structures to form an intermediate trench. The intermediate trench exposes a first preset portion of the partial initial conductive structure, and the remaining first intermediate portion of the substrate forms a plurality of independent intermediate structures.

[0161] In some embodiments, removing partial structures of the first intermediate portion 111 of the substrate 110 and partial initial word line structures 200 according to the mask layer 400 includes: removing the partial structure of the substrate 110 located above the top surface of the initial conductive structure 230, and removing the partial substrate 110 covering the first preset portion 231 of the initial conductive structure 230 and removing the initial barrier structure 220 covering the first preset portion 231 of the initial conductive structure 230 in two steps.

[0162] As Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 shown, referring to Figure 9 , Figure 10 , Figure 11, removing the part of the substrate 110 above the top surface of the initial conductive structure 230, including: removing the substrate 110 exposed by the mask layer 400 and removing the initial insulating structure 240 exposed by the mask layer 400 and the initial gate oxide layer 210 covering the initial insulating structure 240, and etching until the upper surface of the initial conductive structure 230 is exposed and then stopping. The remaining initial insulating structure 240 and the initial gate oxide layer 210 covering the initial insulating structure 240 are located in the remaining substrate 110. The remaining initial insulating structure 240, the initial gate oxide layer 210 covering the initial insulating structure 240, and the remaining substrate 110 together form an intermediate structure 700, and the intermediate structure 700 is an independently arranged island structure.

[0163] Step S340: Form a protective layer that covers at least a first preset portion of the initial conductive structure.

[0164] In some embodiments, the implementation manner of step S340 and step S230 of the above embodiments is the same, and details are not described herein again. In some embodiments, as Figure 16 , Figure 17 , Figure 18 shown, the formed protective layer 270 covers the first preset portion 231 of the initial conductive structure 230, the intermediate structure 700, and the outer surface exposed by the mask layer 400.

[0165] Step S350: Remove a part of the second intermediate portion of the substrate to form a third trench, and the third trench exposes a second preset portion of the initial conductive structure. The remaining second intermediate portion of the substrate and the intermediate structure together constitute a plurality of independent active region structures, and the intermediate trench and the third trench together constitute an isolation trench.

[0166] In some embodiments, the implementation manner of step S350 and step S240 of the above embodiments is the same, and details are not described herein again.

[0167] Step S360: Remove a part of the initial conductive structure in the second part of the initial word line structure, and the bottom surface of the initial conductive structure covered by the active region structure is lower than the bottom surface of the initial conductive structure of the remaining second part of the initial word line structure.

[0168] In some embodiments, the implementation manner of step S360 and step S250 of the above embodiments is the same, and details are not described herein again.

[0169] Step S370: Form a second dielectric layer, and the second dielectric layer fills the isolation trench. The top surface of the second dielectric layer is flush with the top surface of the active region structure, and the first dielectric layer and the second dielectric layer together constitute an isolation structure.

[0170] As Figure 29 , Figure 30 , referring toFigure 25 , Figure 26 , Figure 27 , the isolation trench 130 can be filled with a low-k dielectric material and the top surface of the initial structure 100 can be covered by atomic layer deposition or chemical vapor deposition. The mask layer 400, the protective layer 270 covering the mask layer 400, and a part of the low-k dielectric material are removed to expose the top surface of the active region structure. The remaining low-k dielectric material forms the second dielectric layer 320 (refer to Figure 31 ). The first dielectric layer 310 and the second dielectric layer 320 together form the isolation structure 300 (refer to Figure 31 ). Exemplarily, the material of the second dielectric layer 320 can be silicon nitride, silicon oxide, or silicon oxynitride, and the material of the second dielectric layer 320 and the material of the first dielectric layer 310 can be the same or different.

[0171] In some embodiments, the initial word line structures are arranged in parallel at equal intervals in the initial structure. The mask layer is patterned according to the arrangement of the initial word line structures. The patterned mask layer includes a plurality of island-shaped sub-masks arranged in parallel and independently, so that the positions of the formed active region structure and the initial word line structure are aligned. In some embodiments, a semiconductor structure is formed, and the process sequence of forming the active region structure and forming the initial word line structure is adjusted. At the same time, the alignment accuracy of the active region structure and the word line structure is ensured. The structural accuracy and dimensional accuracy of the semiconductor structure are higher, and the yield of the semiconductor structure is improved.

[0172] According to an exemplary embodiment of the present disclosure, some embodiments provide a semiconductor structure, as shown in Figure 31 , Figure 32 , Figure 33 . The semiconductor structure includes: a substrate 500, a plurality of active region structures 600 independently disposed on the substrate 500, and an isolation structure 300 located between the plurality of active region structures 600. The semiconductor structure further includes a word line structure 800. The word line structure includes a conductive structure 810. The conductive structure 810 includes a contact portion 811 disposed in the active region structure 600 and a connection portion 812 disposed in the isolation structure 300. The bottom surface of the contact portion 811 of the conductive structure 810 is lower than the bottom surface of the connection portion 812 of the conductive structure 810.

[0173] For the semiconductor structure of some embodiments, along the extending direction of the word line structure 800, the conductive structure 810 includes alternately arranged contact portions 811 and connection portions 812. The contact portions 811 penetrate through the active region structure 600, and the connection portions 812 penetrate through the isolation structure 300. Moreover, the bottom surface of the contact portion 811 of the conductive structure 810 is lower than the bottom surface of the connection portion 812. By reducing the size of the connection portion 812, the interference of the connection portion 812 of the conductive structure 810 to the contact portion 811 is reduced, and the interference between adjacent contact portions 811 is also reduced, reducing the occurrence of the row hammer effect, and it can be applied to semiconductor devices with smaller sizes and higher integration degrees.

[0174] According to an exemplary embodiment, most of the content of the semiconductor structure of some embodiments is the same as that of the above embodiments. The difference between some embodiments and the above embodiments is that, as Figure 31 , Figure 32 , Figure 33 shown, the word line structure 800 further includes a first blocking structure 820, and the first blocking structure 820 is disposed between the contact portion 811 of the conductive structure 810 and the active region structure 600.

[0175] As Figure 31 , Figure 32 , Figure 33 shown, the word line structure 800 further includes a gate oxide layer 830, and the gate oxide layer 830 covers the side wall and the bottom surface of the contact portion 811 of the conductive structure 810. The gate oxide layer 830 is disposed between the contact portion 811 of the conductive structure 810 and the active region structure 600. In some embodiments, the gate oxide layer 830 is disposed between the first blocking structure 820 and the active region structure 600.

[0176] As Figure 31 , Figure 32 , Figure 33 shown, the word line structure 800 includes an insulating structure 840, and the insulating structure 840 covers the top surface of the contact portion 811 of the conductive structure 810. The top surface of the insulating structure 840 is flush with the top surface of the active region structure 600.

[0177] As Figure 31 , Figure 32 , Figure 33 shown, the word line structure 800 further includes a second blocking structure 850, and the second blocking structure 850 covers at least the top surface and the side wall of the connection portion 812 of the conductive structure 810. In some embodiments, as Figure 31 , Figure 32 , Figure 33 shown, it also covers a part of the side wall of the active region structure 600.

[0178] In some embodiments, the top surface of the contact portion 811 of the conductive structure 810 is flush with the top surface of the connection portion 812, and the height of the connection portion 811 of the conductive structure 810 is greater than two-thirds of the height of the contact portion 811.

[0179] The semiconductor structure of some embodiments reduces the height of the connection portion 812, retains the conduction function of the connection portion 812 for connecting adjacent contact portions 811, but reduces the contact area between the connection portion 812 and the contact portion 811. When the semiconductor structure is refreshed and read frequently for multiple times, it can reduce the interference of the connection portion 812 to the contact portion 811 and the adjacent interference between the contact portions 811, and reduce charge leakage. It avoids the performance degradation of the semiconductor structure caused by the row hammer effect.

[0180] The semiconductor structure according to an embodiment of the present disclosure may be included in a memory cell and a memory cell array.

[0181] The memory cell and the memory cell array may be included in a storage device, and the storage device may be used in a Dynamic Random Access Memory (DRAM). However, it can also be applied to a Static Random-Access Memory (SRAM), a flash EPROM, a Ferroelectric Random-Access Memory (FeRAM), a Magnetic RandomAccess Memory (MRAM), a Phase change Random-Access Memory (PRAM), etc.

[0182] The embodiments or implementation manners in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0183] In the description of this specification, the description with reference to terms such as "embodiment", "exemplary embodiment", "some implementation manners", "schematic implementation manner", "example", etc. means that the specific features, structures, materials or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of the present disclosure.

[0184] In this specification, the schematic expressions of the above terms do not necessarily refer to the same implementation manner or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more implementation manners or examples.

[0185] In the description of the present disclosure, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present disclosure.

[0186] It can be understood that the terms "first", "second", etc. used in the present disclosure may be used in the present disclosure to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0187] In one or more of the drawings, the same elements are represented by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of brevity, the structure obtained after several steps may be described in one drawing. Many specific details of the present disclosure are described hereinafter, such as the structure, materials, dimensions, processing techniques and technologies of the device, so as to understand the present disclosure more clearly. However, as those skilled in the art can understand, the present disclosure may be implemented without these specific details.

[0188] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The manufacturing method of the semiconductor structure includes: Providing an initial structure, the initial structure includes a substrate and a plurality of mutually parallel initial word line structures buried in the substrate, and the initial word line structure includes an initial conductive structure; Removing a part of the substrate and a part of the initial word line structure to form isolation trenches, and the remaining part of the substrate is isolated by the isolation trenches to form a plurality of mutually independent active region structures. The active region structures cover a first part of the initial word line structure, and the isolation trenches expose a second part of the initial word line structure; Removing a part of the initial conductive structure in the second part of the initial word line structure, and the bottom surface of the initial conductive structure covered by the active region structure is lower than the bottom surface of the initial conductive structure of the remaining second part of the initial word line structure.

2. The manufacturing method of the semiconductor structure according to claim 1, wherein, The removing a part of the substrate and a part of the initial word line structure includes: Removing a part of the structure of the first intermediate part of the substrate and a part of the initial word line structure to form an intermediate trench. The intermediate trench exposes a first preset part of the initial conductive structure, and the first intermediate part of the remaining substrate forms a plurality of mutually independent intermediate structures; Removing a part of the structure of the second intermediate part of the substrate to form a third trench. The third trench exposes a second preset part of the initial conductive structure, and the second intermediate part of the remaining substrate and the intermediate structures together constitute a plurality of mutually independent active region structures. The intermediate trench and the third trench together constitute the isolation trench.

3. The manufacturing method of the semiconductor structure according to claim 2, wherein The initial word line structure further includes an initial barrier structure formed between the substrate and the initial conductive structure; The removing a part of the structure of the first intermediate part of the substrate and a part of the initial word line structure to form an intermediate trench includes: Removing the part of the substrate located above the top surface of the initial word line structure to form a first trench. The first trench exposes the top surface of the second part of the initial word line structure; Removing the substrate covering the first preset part of the initial conductive structure and removing the initial barrier structure covering the first preset part of the initial conductive structure to form a second trench. The second trench exposes the first preset part of the initial conductive structure. The first trench and the second trench together constitute the intermediate trench.

4. The manufacturing method of the semiconductor structure according to claim 3, characterized in that, The remaining substrate above the top surface of the initial word line structure forms a plurality of independently arranged island structures; The removing the substrate covering the first preset part of the initial conductive structure includes: Using the island structures and the top surface of the second part of the initial word line structure as a mask to remove the substrate covering the first preset part of the initial conductive structure.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein, The removing a part of the structure of the second intermediate part of the substrate includes: Using the intermediate structures and the initial word line structure as a mask, and partially removing the second intermediate part of the substrate by a vertical etching process to expose the second preset part of the initial conductive structure.

6. The manufacturing method of the semiconductor structure according to claim 5, characterized in that, The removing a part of the structure of the second intermediate part of the substrate further includes: Adopt a lateral etching process to remove the second intermediate portion of the substrate covered by the second portion of the initial word line structure.

7. The method for fabricating a semiconductor structure according to claim 6, wherein, The removing of a part of the initial conductive structure in the second portion of the initial word line structure includes: Form a first dielectric layer filled in the isolation trench, and the top surface of the first dielectric layer is flush with the lower surface of the initial word line structure; Remove the initial barrier structure covering the second preset portion of the initial conductive structure in the second portion of the initial word line structure, and the second preset portion of the initial conductive structure.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein, After the removing of a part of the initial conductive structure in the second portion of the initial word line structure, it includes: Form a second dielectric layer, the second dielectric layer fills the isolation trench, the top surface of the second dielectric layer is flush with the top surface of the active region structure, and the first dielectric layer and the second dielectric layer together form an isolation structure.

9. The method for manufacturing a semiconductor structure according to claim 2, wherein, Before the removing of a part of the second intermediate portion of the substrate and after the removing of a part of the first intermediate portion of the substrate and a part of the initial word line structure, it includes: Form a protective layer, and the protective layer covers at least the first preset portion of the initial conductive structure.

10. The method for fabricating a semiconductor structure according to claim 2, wherein Before the removing of a part of the first intermediate portion of the substrate and a part of the initial word line structure, it includes: Form a mask layer, the mask layer covers a part of the top surface of the initial structure, and the projection of the mask layer on the initial structure is a plurality of island-shaped patterns arranged in a parallel array.

11. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The providing of the initial structure includes: Provide an initial substrate; Remove a part of the initial substrate to form a word line trench; Form an initial gate oxide layer, and the initial gate oxide layer covers the word line trench; Form an initial barrier structure, and the initial barrier structure covers the initial gate oxide layer; Form an initial conductive structure, the initial conductive structure is filled inside the initial barrier structure, and the top surface of the initial conductive structure is lower than the top surface of the initial substrate; Form an initial insulating structure, the initial insulating structure covers the top surface of the initial conductive structure, and the top surface of the insulating structure is flush with the top surface of the initial substrate; The initial gate oxide layer, the initial barrier structure, the initial conductive structure and the initial insulating structure form the initial word line structure.

12. A semiconductor structure, characterized in that, It includes: A substrate, on which a plurality of independently arranged active region structures are provided; An isolation structure, and the isolation structure is located between the plurality of active region structures; A word line structure, the word line structure includes a conductive structure, the conductive structure includes a contact portion provided in the active region structure and a connection portion provided in the isolation structure, and the bottom surface of the contact portion of the conductive structure is lower than the bottom surface of the connection portion of the conductive structure; wherein, The word line structure further includes a first barrier structure, and the first barrier structure is provided between the contact portion of the conductive structure and the active region structure; and / or The word line structure includes an insulating structure, the insulating structure covers the top surface of the contact portion of the conductive structure, and the top surface of the insulating structure is flush with the top surface of the active region structure; and / or The word line structure further includes a second blocking structure, and the second blocking structure covers at least the top surface and the side walls of the connection portion of the conductive structure.

13. The semiconductor structure according to claim 12, wherein The word line structure further includes a gate oxide layer, the gate oxide layer covers the side walls and the bottom surface of the contact portion of the conductive structure, and the gate oxide layer is disposed between the contact portion of the conductive structure and the active region structure.

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