A display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. The display area of the display panel includes a pixel circuit, a light emitting device and a signal line; the pixel circuit is electrically connected with the light emitting device, and the signal line is electrically connected with the pixel circuit; the signal line includes a constant voltage signal line extending in a first direction, and the constant voltage signal line is connected with a constant voltage terminal; the display area includes a first display area and a second display area, and the first display area is a reserved device setting area; the constant voltage signal line includes a first constant voltage signal line located in the first display area and a second constant voltage signal line located in the second display area; the spacing between two adjacent first constant voltage signal lines in the first display area is D1, the spacing between two adjacent second constant voltage signal lines in the second display area is D2, and D1 is greater than D2. The present application can improve the light transmittance of the first display area by designing the wiring mode of the constant voltage signal line in the first display area, so as to be applied in the under-screen photosensitive device scheme.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] In electronic products such as mobile phones and tablet computers, front-facing cameras, infrared sensing elements and other photosensitive devices occupy a certain space on the front of the product and affect the screen ratio. With the proposal of the concept of full-screen in the display field, major manufacturers are all making efforts in the field of full-screen research. At present, it is generally believed that the under-screen photosensitive device scheme is a relatively optimal scheme that can achieve a true full-screen. Taking the under-screen camera scheme as an example, the camera is arranged below the display area of the display screen, and the camera does not occupy the space of the non-display area on the front of the electronic product. In application, the position where the camera is located can be normally displayed, and the camera receives light penetrating the display screen to form an image. The display panel applied in the under-screen photosensitive device scheme needs to be specially designed to make the light transmittance of the display area corresponding to the photosensitive device meet the requirements. SUMMARY

[0003] The embodiments of the present application provide a display panel and a display device to be applied in the under-screen photosensitive device scheme, so as to improve the light transmittance of the display panel at the position corresponding to the photosensitive device.

[0004] In one aspect, the embodiments of the present application provide a display panel, which comprises a display area, the display area comprising a pixel circuit, a light emitting device and a signal line; the pixel circuit is electrically connected with the light emitting device, and the signal line is electrically connected with the pixel circuit; the signal line comprises a first signal line extending in a first direction, and the first signal line comprises a constant voltage signal line connected with a constant voltage terminal; the display area comprises a first display area and a second display area, and the first display area is a reserved device setting area; the constant voltage signal line comprises a first constant voltage signal line located in the first display area and a second constant voltage signal line located in the second display area.

[0005] The distance between two adjacent first constant voltage signal lines in the first display area is D1, and the distance between two adjacent second constant voltage signal lines in the second display area is D2; wherein D1≥D2.

[0006] In another aspect, the embodiments of the present application also provide a display device comprising the display panel provided by any of the embodiments of the present application.

[0007] The display panel and the display device provided by the embodiment of the present application have the following beneficial effects: in the embodiment of the present application, the wiring mode of the first constant voltage signal line in the first display area is designed in combination with the arrangement mode of the pixel circuit in the first display area, and the wiring mode of the second constant voltage signal line in the second display area is set, so that in the same area where the constant voltage signal lines are arranged: the number of the first constant voltage signal lines in the first display area is not more than the number of the second constant voltage signal lines, the number of the first constant voltage signal lines arranged in the first display area can be reduced, thereby the area of the non-light-transmitting area in the first display area can be reduced, and the area of the light-transmitting area is correspondingly increased, so as to improve the light transmittance of the first display area. In the application in the under-screen photosensitive device scheme, the high demand of the photosensitive device on the light transmittance of the display panel is met. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0009] Figure 1 A display panel schematic diagram provided by the embodiment of the present application;

[0010] Figure 2 Another display panel schematic diagram provided by the embodiment of the present application;

[0011] Figure 3 A Figure 1 A cross-sectional schematic diagram at the position of tangent A-A';

[0012] Figure 4 A pixel circuit schematic diagram in the display panel provided by the embodiment of the present application;

[0013] Figure 5 A Figure 4 A timing diagram of the pixel circuit;

[0014] Figure 6 Another pixel circuit schematic diagram provided by the embodiment of the present application;

[0015] Figure 7 A Figure 6 A timing diagram of the pixel circuit;

[0016] Figure 8 Another pixel circuit schematic diagram provided by the embodiment of the present application;

[0017] Figure 9 A line type schematic diagram of the signal line in the display panel provided by the embodiment of the present application;

[0018] Figure 10 for Figure 1 an enlarged schematic view of the middle region Q at a position;

[0019] Figure 11 for Figure 1 an enlarged schematic view of the middle region Q at a position;

[0020] Figure 12 for Figure 1 an enlarged schematic view of the middle region Q at a position;

[0021] Figure 13 for Figure 1 an enlarged schematic view of the middle region Q at a position;

[0022] Figure 14 for a partial schematic view of another display panel provided by an embodiment of the application;

[0023] Figure 15 for

[0024] a partial schematic view of another display panel provided by an embodiment of the application; Figure 16

[0025] for Figure 17 a partial schematic view of another display panel provided by an embodiment of the application;

[0026] Figure 18 for a partial schematic view of another display panel provided by an embodiment of the application;

[0027] Figure 19 Figure 14 for a cross-sectional schematic view at a position of tangent line B-B';

[0028] Figure 20 for

[0029] a partial schematic view of another display panel provided by an embodiment of the application; Figure 21

[0030] for Figure 22 a cross-sectional schematic view at a position of tangent line C-C'; Figure 21

[0031] for Figure 23 a partial schematic view of another display panel provided by an embodiment of the application;

[0032] Figure 24 for a partial schematic view of another display panel provided by an embodiment of the application;

[0033] Figure 25Another partial simplified schematic view of a display panel is provided for an embodiment of the present application.

[0034] Figure 26 Another partial schematic view of a display panel is provided for an embodiment of the present application.

[0035] Figure 27 Another partial schematic view of a display panel is provided for an embodiment of the present application.

[0036] Figure 28 Another partial schematic view of a display panel is provided for an embodiment of the present application.

[0037] Figure 29 Another partial schematic view of a first display area of a display panel is provided for an embodiment of the present application.

[0038] Figure 30 Another partial schematic view of a display panel is provided for an embodiment of the present application.

[0039] Figure 31 Another partial schematic view of a display panel is provided for an embodiment of the present application.

[0040] Figure 32 Another partial schematic view of a display panel is provided for an embodiment of the present application.

[0041] Figure 33 Another partial schematic view of a display panel is provided for an embodiment of the present application.

[0042] Figure 34 Another partial schematic view of a display panel is provided for an embodiment of the present application.

[0043] Figure 35 For Figure 34 A cross-sectional schematic view at a position of tangent line D-D';

[0044] Figure 36 Another partial schematic view of a display panel is provided for an embodiment of the present application.

[0045] Figure 37 Another partial schematic view of a display panel is provided for an embodiment of the present application.

[0046] Figure 38 Another partial schematic view of a display panel is provided for an embodiment of the present application.

[0047] Figure 39 For Figure 38 A cross-sectional schematic view at a position of tangent line E-E';

[0048] Figure 40 Another partial schematic view of a display panel is provided for an embodiment of the present application.

[0049] Figure 41 FIG. 6 is a partial schematic view of another display panel according to an embodiment of the present application;

[0050] Figure 42 FIG. 7 is a partial schematic view of another display panel according to an embodiment of the present application; Figure 41 FIG. 8 is a partial schematic view of another display panel according to an embodiment of the present application;

[0051] Figure 43 FIG. 9 is a partial schematic view of another display panel according to an embodiment of the present application;

[0052] Figure 44 FIG. 10 is a partial schematic view of another display panel according to an embodiment of the present application;

[0053] Figure 45 FIG. 11 is a partial schematic view of another display panel according to an embodiment of the present application;

[0054] Figure 46 FIG. 12 is a partial schematic view of another display panel according to an embodiment of the present application;

[0055] Figure 47 FIG. 13 is a partial schematic view of another display panel according to an embodiment of the present application;

[0056] Figure 48 FIG. 14 is a partial schematic view of another display panel according to an embodiment of the present application;

[0057] Figure 49 FIG. 15 is a partial schematic view of another display panel according to an embodiment of the present application;

[0058] Figure 50 FIG. 16 is a partial schematic view of another display panel according to an embodiment of the present application;

[0059] Figure 51 FIG. 17 is a partial schematic view of another display panel according to an embodiment of the present application;

[0060] Figure 52 FIG. 18 is a partial schematic view of another display panel according to an embodiment of the present application;

[0061] Figure 53 FIG. 19 is a partial schematic view of another display panel according to an embodiment of the present application;

[0062] Figure 54 FIG. 20 is a partial schematic view of another display panel according to an embodiment of the present application;

[0063] Figure 55 FIG. 21 is a partial schematic view of another display panel according to an embodiment of the present application;

[0064] Figure 56A partial schematic diagram of another display panel provided in an embodiment of the present invention;

[0065] Figure 57 A partial schematic diagram of another display panel provided in an embodiment of the present invention;

[0066] Figure 58 This is a schematic diagram of a display device provided in an embodiment of the present invention;

[0067] Figure 59 for Figure 58 A schematic diagram of the cross section at the position of the tangent line G-G'. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0069] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0070] This invention provides a display panel and a display device. The display area of ​​the display panel includes a reserved device setting area. By designing the circuit wiring method in the reserved device setting area, the light transmittance of the reserved device setting area is increased.

[0071] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 3 for Figure 1 A schematic diagram of the cross section at the position of the tangent line A-A'.

[0072] like Figure 1 and Figure 2 As shown, the display panel includes a display area AA and a non-display area BA. The display area AA includes a first display area AA1 and a second display area AA2. Figure 1 The diagram shows that the second display area AA2 surrounds the first display area AA1. Figure 2The diagram illustrates that a first display area AA1 is partially surrounded by a second display area AA2. The first display area AA1 is a reserved area for a device, used in under-display photosensitive device solutions where the photosensitive device is positioned below this reserved area. The shape of the first display area AA1 is not limited in this embodiment. The light transmittance of the first display area AA1 is greater than that of the second display area AA2.

[0073] In some embodiments, the density of light-emitting devices in the first display area AA1 is less than the density of light-emitting devices in the second display area AA2, and the density of pixel circuits in the first display area AA1 is less than the density of pixel circuits in the second display area AA.

[0074] In some embodiments, the density of light-emitting devices in the first display area AA1 is the same as the density of light-emitting devices in the second display area AA2, and the density of pixel circuits in the first display area AA1 is less than the density of pixel circuits in the second display area AA2. In one embodiment, a pixel circuit (not shown, which may be located in the first display area AA1 or the second display area AA2) is electrically connected to two or more light-emitting devices of the same color in the first display area AA1.

[0075] like Figure 3 As shown, the display panel includes a substrate 10, and an array layer 20, a display layer 30, and an encapsulation layer 40 located on the substrate 10. Pixel circuits 21 and signal lines (not shown) are located on the array layer 20, and the signal lines are electrically connected to the pixel circuits 21. The display layer 30 includes a light-emitting device 31 and a pixel definition layer 32. The pixel circuits 21 are electrically connected to the light-emitting device 31, and the pixel circuit 21 refers to the smallest repeating unit of the circuit structure that drives the light-emitting device 31 to emit light. The light-emitting device 31 includes a first electrode 31a, a light-emitting layer 31b, and a second electrode 31c stacked sequentially. In one embodiment, the light-emitting device 31 is an organic light-emitting device; in another embodiment, the light-emitting device 31 is an inorganic light-emitting device. The encapsulation layer 40 is used to isolate water and oxygen to prevent damage to the light-emitting device 31. The signal lines include at least data lines, reset signal lines, power signal lines, scan lines, and light emission control lines.

[0076] In one embodiment, the first electrode 31a is the anode and the second electrode 31c is the cathode. In another embodiment, the first electrode 31a is the cathode and the second electrode 31c is the anode.

[0077] In some embodiments, the first electrode 31a is a reflective electrode, which includes a reflective layer that may include Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a mixture thereof. The second electrode 31c is a transparent electrode, which is made of one or more of ITO, IZO, ZnO, or In2O3.

[0078] Figure 4 This is a schematic diagram of a pixel circuit in a display panel provided in an embodiment of the present invention. Figure 5 for Figure 4 Timing diagram of the mid-pixel circuit. (e.g.) Figure 4 The pixel circuit shown includes 7 transistors and 1 capacitor, also known as a 7T1C pixel circuit. Figure 4 As shown, the pixel circuit includes a driving transistor Tm, a data writing transistor T1, a threshold compensation transistor T2, a first reset transistor T3, a second reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a storage capacitor Cst. The first reset transistor T3 is used to reset the control terminal of the driving transistor Tm, and the second reset transistor T4 is used to reset the first electrode of the light-emitting device 31.

[0079] Specifically, the first terminal of the data writing transistor T1 is connected to the data line D, and the second terminal of the data writing transistor T1 is electrically connected to the first terminal of the driving transistor Tm; the first terminal of the first light-emitting control transistor T5 is connected to the power signal line P, and the second terminal of the first light-emitting control transistor T5 is electrically connected to the first terminal of the driving transistor Tm; the first terminal of the second light-emitting control transistor T6 is electrically connected to the second terminal of the driving transistor Tm, and the second terminal of the second light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting device 31; the first terminal of the first reset transistor T3 is electrically connected to the control terminal of the driving transistor Tm, the first terminal of the second reset transistor T4 is electrically connected to the first electrode of the light-emitting device 31, and the second terminals of both the first reset transistor T3 and the second reset transistor T4 are connected to the reset signal line Ref; the first terminal of the threshold compensation transistor T2 is electrically connected to the second terminal of the driving transistor Tm, and the second terminal of the threshold compensation transistor T2 is electrically connected to the control terminal of the driving transistor Tm. Figure 4 As illustrated, the control terminals of the data writing transistor T1 and the threshold compensation transistor T2 are both connected to the first scan line S1; the control terminal of the first reset transistor T3 is connected to the second scan line S2; the control terminal of the second reset transistor T4 is connected to the third scan line S3; and the control terminals of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both connected to the light-emitting control line E.

[0080] The operation of the pixel circuit includes a reset phase t1, a data writing phase t2, and a light emission phase t3, combined with...Figure 5 The schematic timing diagram is understood.

[0081] In the reset phase t1: the second scan line S2 provides an effective level signal to control the first reset transistor T3 to open, and the reset signal provided by the reset signal line Ref is written into the control terminal of the driving transistor Tm to reset the control terminal of the driving transistor Tm; the third scan line S3 provides an effective level signal to control the second reset transistor T4 to open, and the reset signal provided by the reset signal line Ref is written into the first electrode of the light emitting device 31 to reset the first electrode.

[0082] In the data writing phase t2: the first scan line S1 provides an effective level signal to control the data writing transistor T1 and the threshold compensation transistor T2 to open, and the data voltage provided by the data line D is written into the control terminal of the driving transistor Tm, and the threshold voltage of the driving transistor Tm is compensated.

[0083] In the light emitting phase t3: the light emitting control line E provides an effective level signal to control the first light emitting control transistor T5 and the second light emitting control transistor T6 to open, and in this phase the driving transistor Tm provides a driving current to the light emitting device 31 to control the light emitting device 31 to emit light.

[0084] In another optional embodiment, with reference to Figure 4 In the reset phase: the second scan line S2 provides an effective level signal to control the first reset transistor T3 to open, and the reset signal provided by the reset signal line Ref is written into the control terminal of the driving transistor Tm to reset the control terminal of the driving transistor Tm.

[0085] In the data writing phase: the first scan line S1 provides an effective level signal to control the data writing transistor T1 and the threshold compensation transistor T2 to open, and the data voltage provided by the data line D is written into the control terminal of the driving transistor Tm, and the threshold voltage of the driving transistor Tm is compensated; and the third scan line S3 provides an effective level signal to control the second reset transistor T4 to open, and the reset signal provided by the reset signal line Ref is written into the first electrode of the light emitting device 31 to reset the first electrode.

[0086] In the light emitting phase: the light emitting control line E provides an effective level signal to control the first light emitting control transistor T5 and the second light emitting control transistor T6 to open, and in this phase the driving transistor Tm provides a driving current to the light emitting device 31 to control the light emitting device 31 to emit light.

[0087] In another optional embodiment, with reference to Figure 6 The difference is that the control terminal of the second reset transistor T4 can be electrically connected with the first scan line S1 to reset the first electrode of the light emitting device 31 synchronously in the data writing phase, which will not be described here.

[0088] In another embodiment, Figure 6 This is another pixel circuit schematic diagram provided in an embodiment of the present invention. Figure 7 for Figure 6 Timing diagram of the mid-pixel circuit. (e.g.) Figure 6 The diagram illustrates that the pixel circuit includes 7 transistors and 1 capacitor. Figure 6 Zhongyu Figure 4 The same parts can be referred to for understanding, and will not be repeated here. Figure 6 In this embodiment, the control terminals of the first reset transistor T3 and the second reset transistor T4 are both connected to the second scan line S2. When the pixel circuit is operating in the reset phase t1, the second scan line S2 provides an effective level signal to control the first reset transistor T3 to turn on in order to reset the control terminal of the driving transistor Tm. At the same time, the second scan line S2 provides an effective level signal to control the second reset transistor T4 to turn on in order to reset the first electrode of the light-emitting device 31.

[0089] In another embodiment, Figure 8 This is another pixel circuit schematic diagram provided in an embodiment of the present invention. Figure 8 Zhongyu Figure 4 The same parts can be referred to for understanding, and will not be repeated here. Figure 8 In this embodiment, the second terminal of the first reset transistor T3 is electrically connected to the first reset signal line 1Ref, and the second terminal of the second reset transistor T4 is electrically connected to the second reset signal line 2Ref. During driving... Figure 8 When the pixel circuit provided in the embodiment is working, the timing of the first scan line S1, the second scan line S2, the third scan line S3, and the light emission control line E can be referenced. Figure 5 A schematic diagram of a timing diagram.

[0090] Specifically, in the reset stage t1: the second scan line S2 provides an effective level signal to control the first reset transistor T3 to be turned on, and the reset signal provided by the first reset signal line 1Ref is written into the control terminal of the driving transistor Tm to reset the control terminal of the driving transistor Tm; the third scan line S3 provides an effective level signal to control the second reset transistor T4 to be turned on, and the reset signal provided by the second reset signal line 2Ref is written into the first electrode of the light emitting device 31 to reset the first electrode. The voltage of the reset signal provided by the first reset signal line 1Ref is greater than the voltage of the reset signal provided by the second reset signal line 2Ref. In this embodiment, the reset of the control terminal of the driving transistor Tm and the reset of the first electrode of the light emitting device can be performed separately. When the second scan line S2 controls the first reset transistor T3 to be turned on to reset the control terminal of the driving transistor Tm, a higher reset voltage signal is provided to the control terminal of the driving transistor Tm through the first reset signal line 1Ref, so that the voltage of the control terminal of the driving transistor Tm is closer to Vdata-Vth(Vdata is the data voltage, and Vth is the threshold voltage of the driving transistor) after the data writing stage, the speed of threshold value capture of the control terminal of the driving transistor Tm is faster when the high-frequency display or low-brightness (or gray scale) display is applied, and the display unevenness is reduced. At the same time, when the third scan line S3 controls the reset of the first electrode of the light emitting device, a lower reset voltage signal is provided to the first electrode of the light emitting device through the second reset signal line 2Ref, which can reduce the light stealing of the light emitting device and improve the low gray scale display effect.

[0091] Figure 4 、 Figure 6 and Figure 8 The transistors in the schematic pixel circuit diagram are all shown as P-type, and the type of the transistors in the pixel circuit is not limited in the present application. It should be noted that “electrically connected” appears in the present application, which means electrically connected and is understood as being connected between different components through a physical line or a transistor that can transmit an electrical signal in the circuit structure.

[0092] In the embodiment of the present application, the signal lines electrically connected with the pixel circuit at least include a data line, a reset signal line, a power signal line, a scan line and a light emitting control line. According to the direction of the signal line, the signal line includes a first signal line extending in a first direction and a second signal line extending in a second direction, wherein the first direction and the second direction intersect each other. It should be noted that the extension direction of the signal line only represents the general trend of the signal line, Figure 9 The line type diagram of the signal line in the display panel provided in the embodiment of the present application is shown in FIG. 1, Figure 9 The trend of the signal line shown in FIG. 1 is direction f, and the signal line in the embodiment of the present application can be a straight line, an “arch” shape line, a broken line or a wavy line, as shown in FIGS. 2, 3, 4 and 5 respectively. Figure 9The schematic diagrams in (1), (2), (3), and (4). Figure 9 The embodiments of the present application do not limit the line type of the signal line, i.e., the signal line is not limited to be a straight line extending in the extending direction thereof.

[0093] Figure 10 For Figure 1 The schematic diagram of one amplification at the position of the region Q, Figure 11 For Figure 1 The schematic diagram of another amplification at the position of the region Q, Figure 12 For Figure 1 The schematic diagram of another amplification at the position of the region Q, Figure 13 For Figure 1 The schematic diagram of another amplification at the position of the region Q.

[0094] As Figure 10 The first signal line 1X extending in the first direction x is illustrated, and the first signal line 1X includes a constant-voltage signal line H connected with a constant-voltage terminal. The constant-voltage terminal is a terminal connected to a driving chip in the display panel, and the position of the constant-voltage terminal is not illustrated in the figure. Specifically, the driving chip provides a constant-voltage signal to the constant-voltage terminal. The constant-voltage signal line H is electrically connected with the constant-voltage terminal, and the constant-voltage signal line H is used for transmitting the constant-voltage signal. The constant-voltage signal line H includes a first constant-voltage signal line H1 located in the first display area AA1 and a second constant-voltage signal line H2 located in the second display area AA2; the first constant-voltage signal line H1 and the second constant-voltage signal line H2 are signal lines transmitting the same kind of signal. The pixel circuit 21 located in the first display area AA1 is electrically connected with the first constant-voltage signal line H1, and the pixel circuit 21 located in the second display area AA2 is electrically connected with the second constant-voltage signal line H2. Figure 10 The pixel circuit 21 is only schematically illustrated. In some embodiments, the first constant-voltage signal line H1 is electrically connected with the second constant-voltage signal line H2; in some embodiments, the first constant-voltage signal line H1 is cut off at the position of the boundary between the first display area AA1 and the second display area AA2.

[0095] The interval between two adjacent first constant-voltage signal lines H1 in the first display area AA1 is D1, and the interval between two adjacent second constant-voltage signal lines H2 in the second display area AA2 is D2; wherein, Figure 10 In the embodiment, D1 is greater than D2, Figure 11In the diagram, D1 is equal to D2. In the embodiment of the present application, D1≥D2. In other words, the distance between two adjacent first constant voltage signal lines H1 in the first display area AA1 is not less than the distance between two adjacent second constant voltage signal lines H2 in the second display area AA2. In other words, in the same area where the constant voltage signal lines H are arranged: the number of the first constant voltage signal lines H1 in the first display area AA1 is not more than the number of the second constant voltage signal lines H2 in the second display area AA2.

[0096] In the embodiment of the present application, the light transmittance of the first display area AA1 is greater than that of the second display area AA2. Specifically, the pixel circuit arrangement density in the first display area AA1 is less than that in the second display area AA2. In the embodiment of the present application, compared with the pixel circuit arrangement in the second display area AA2, the pixel circuits in the first display area AA1 are arranged sparsely in the same area, so that the light transmittance of the first display area AA1 is greater than that of the second display area AA2.

[0097] In the embodiment of the present application, the first display area AA1 includes a plurality of pixel circuit groups Z, and each pixel circuit group Z includes three pixel circuits arranged in the second direction y. In one embodiment, the pixel circuits are arranged in an array in the display panel, the first direction x is the row direction of the pixel circuit groups Z, and the second direction y is the column direction of the pixel circuit groups Z. As shown in Figure 10 In the diagram, taking a pixel circuit group Z including three pixel circuits 21 as an example, in the first display area AA1: the pixel circuit groups Z located in the odd columns in the odd rows are removed, and the pixel circuit groups Z located in the even columns in the even rows are removed, so that the area of the light transmission area in the first display area AA1 is increased.

[0098] In another embodiment, as shown in Figure 12 the first display area AA1 includes a plurality of pixel circuit groups Z, and each pixel circuit group Z includes three pixel circuits 21 arranged in the second direction y, the first direction x is the row direction of the pixel circuit groups Z, and the second direction y is the column direction of the pixel circuit groups Z. In the first display area AA1: the pixel circuits 21 in the pixel circuit group rows in the odd rows are removed, or the pixel circuits 21 in the pixel circuit group rows in the even rows are removed. Then the distance between two adjacent pixel circuit groups in the column direction in the first display area AA1 is increased.

[0099] In another embodiment, as shown in Figure 13 In the first display area AA1: the pixel circuits 21 in the pixel circuit group columns in the even columns are removed, or the pixel circuits 21 in the pixel circuit group columns in the odd columns are removed. Then the distance between two adjacent pixel circuit groups in the second direction y in the first display area AA1 is increased.

[0100] In the embodiments of the present application Figure 10 、 Figure 12 、 Figure 13 In the embodiments of the present application, a column of pixel circuits arranged in the first direction x in the second display area AA2 corresponds to a second constant-voltage signal line H2. A column of pixel circuits in the first display area AA1 corresponds to a first constant-voltage signal line H1, which is equivalent to three columns of pixel circuits corresponding to a first constant-voltage signal line H1. Figure 11 In the embodiments of the present application, the arrangement of the first constant-voltage signal line H1 in the first display area AA1 is designed in combination with the arrangement of the pixel circuit 21 in the first display area AA1, and the arrangement of the second constant-voltage signal line H2 in the second display area AA2 is set, so that in the same area where the constant-voltage signal lines are arranged: the number of the first constant-voltage signal lines H1 in the first display area AA1 is not greater than the number of the second constant-voltage signal lines H2 in the second display area AA2. The number of the first constant-voltage signal lines H1 in the first display area AA1 can be reduced, so that the area of the non-light-transmitting area in the first display area AA1 can be reduced, and the area of the light-transmitting area can be correspondingly increased, so as to improve the light transmittance of the first display area AA1. In the application in the under-screen photosensitive device scheme, the high demand of the photosensitive device on the light transmittance of the display panel can be met.

[0101] The non-light-transmitting area in the first display area AA1, i.e., the area with relatively low light transmittance in the first display area AA1. The first display area AA1 also includes a light-transmitting area, wherein the light transmittance of the light-transmitting area is greater than that of the non-light-transmitting area. In some embodiments, the non-light-transmitting area is arranged around the light-transmitting area. In some embodiments, in the first display area AA1, the area where the light-emitting device, the pixel circuit, the wiring, and their overlapping area are located in the direction perpendicular to the plane of the substrate form the non-light-transmitting area. In some embodiments, an optical shielding layer (metal or resin material) is arranged in the first display area AA1, the optical shielding layer has an opening, and the area where the light-emitting device, the pixel circuit, the wiring, and the optical shielding layer are located in the direction perpendicular to the plane of the substrate form the non-light-transmitting area, and the area where the opening of the optical shielding layer is located forms the light-transmitting area. In the application in the under-screen photosensitive device scheme, the ambient light is transmitted through the display panel from the light-transmitting area in the first display area AA1 and is received by the photosensitive surface of the photosensitive device, so the size of the light-transmitting area in the first display area AA1 has a great influence on the light transmittance of the ambient light through the first display area AA1. By reducing the area of the non-light-transmitting area in the first display area AA1, the area of the light-transmitting area can be correspondingly increased, and the light transmittance of the first display area can be improved, so as to improve the application performance of the photosensitive device.

[0102] In the embodiment of the present application, the display region comprises pixel circuit groups, and each pixel circuit group comprises n pixel circuits arranged in the second direction, where n is a positive integer and n≥2. The arrangement direction of the pixel circuits in the pixel circuit group is different from the extension direction of the constant voltage signal lines defined in the embodiment of the present application. In the first display region, the pixel circuit group can be understood as the smallest pixel circuit group capable of driving a pixel unit to emit white light. Specifically, a pixel unit comprises at least a red light emitting device for emitting red light, a blue light emitting device for emitting blue light, and a green light emitting device for emitting green light. The correspondence between the pixel circuit group and the light emitting devices in the first display region will be described in detail in the specific embodiments below. The pixel circuit group in the second display region needs to be understood in combination with the specific embodiments. When the number of pixel circuits in a pixel circuit group in the second display region is the same as the number of pixel circuits in a pixel circuit group in the first display region, the pixel circuit group in the second display region can drive a pixel unit to emit white light. When the number of pixel circuits in a pixel circuit group in the second display region is less than the number of pixel circuits in a pixel circuit group in the first display region, the pixel circuits in the pixel circuit group in the second display region can only drive part of the pixels in the pixel unit capable of emitting white light to emit light.

[0103] In the embodiment of the present application, the first display region comprises circuit regions and wiring regions. The circuit regions comprise at least one pixel circuit group, that is, in some embodiments, one circuit region comprises one pixel circuit group. In some embodiments, one circuit region comprises two or three pixel circuit groups, and in this embodiment, the spacing between two adjacent pixel circuit groups is less than the spacing between two pixel circuit groups belonging to different circuit regions.

[0104] In some embodiments, the wiring region is located between adjacent circuit regions, and the wiring region is used to arrange signal transmission lines. It can also be understood that the pixel circuits and the signal lines electrically connected to the pixel circuits are arranged in the circuit region, and the signal transmission lines arranged in the wiring region are used to connect the signal lines in the adjacent circuit regions.

[0105] In some embodiments, a portion of the wiring area is located between adjacent circuit areas; another portion of the wiring area connects only one side of the circuit area, and this portion of the wiring area is used to set up wiring connecting pixel circuits and light-emitting devices. In this embodiment of the invention, the first display area AA1 includes multiple pixel circuit groups. The arrangement direction of the pixel circuits in the pixel circuit groups is different from the extension direction of the first constant voltage signal line. Setting the pixel circuits in the same pixel circuit group to be electrically connected to the same first constant voltage signal line can reduce the number of first constant voltage signal lines set in the first display area. On the one hand, this is beneficial to reducing the overall width occupied by the pixel circuit group and the constant voltage signal line connected to it in the second direction (the arrangement direction of the pixel circuits in the pixel circuit group); on the other hand, it can also reduce the number of first constant voltage signal lines set in the wiring area between two adjacent circuit areas in the first direction, which is also beneficial to reducing the width occupied by the wiring area in the second direction. This embodiment can reduce the area of ​​the non-transparent area in the first display area as a whole, and correspondingly increase the area of ​​the transparent area in the first display area, thereby improving the light transmittance of the first display area. Furthermore, in existing technologies, when light passes through the first display area, the various traces arranged within the first display area can form a diffraction grating, which diffracts the light. For example, when the under-display photosensitive device is a camera, the diffraction phenomenon affects the imaging quality of the camera. This embodiment of the invention reduces the number of first constant voltage signal lines within the trace area, which can also improve the diffraction phenomenon when light passes through the first display area to a certain extent, further enhancing the optical performance of the optical device.

[0106] In one embodiment, Figure 14 A partial schematic diagram of another display panel provided in an embodiment of the present invention, as shown below. Figure 14 As shown, within the first display area AA1: pixel circuit group Z includes three (n=3) pixel circuits 21 arranged in the second direction y. The arrangement direction of the pixel circuits 21 in pixel circuit group Z intersects with the extension direction of the first constant voltage signal line H1. The first display area AA1 includes a circuit area QD, and each circuit area QD includes at least one pixel circuit group Z. Figure 14The first constant voltage signal line H1 in the first display area AA1 is extended from the circuit area QD to a trace area ZD adjacent to the circuit area QD in the first direction x, and the pixel circuit 21 in the same pixel circuit group Z is electrically connected to the same first constant voltage signal line H1. The number of the first constant voltage signal lines H1 in the trace area ZD can be reduced, and the width of the trace area ZD in the second direction y can be reduced, which is beneficial to reduce the area of the non-transparent area in the first display area AA1. In the first display area AA1, the display panel includes a first connecting part 1J extending in the second direction y, and the pixel circuit 21 belonging to the same pixel circuit group Z is connected to the first constant voltage signal line H1 through the first connecting part 1J. The extending direction of the first connecting part 1J is the same as (or approximately the same as) the arrangement direction of the pixel circuit 21 in the pixel circuit group Z, so that the first constant voltage signal line H1 can provide voltage signals to the multiple pixel circuits 21 in the pixel circuit group Z through the first connecting part 1J. Specifically, the first connecting part 1J is located in the circuit area QD, and the length of the first connecting part 1J is as small as possible to ensure that the area of the circuit area QD is less affected. In the first display area AA1, the first connecting part 1J is used to connect the element of the pixel circuit 21 receiving the constant voltage signal to the first constant voltage signal line H1.

[0107] Figure 14 The first display area includes the first connecting part in the embodiment, and the second connecting part, the third connecting part, the fourth connecting part and the fifth connecting part will be involved in some embodiments below. The connecting part in the embodiment of the present application is a connecting line segment for realizing the connection between two elements (which can be between two signal lines or between a transistor and a signal line).

[0108] In the first display area AA1 of the present application, the n pixel circuits in a pixel circuit group Z are arranged in the second direction y, the first constant voltage signal line H1 is arranged in the first direction x, and the n pixel circuits in a pixel circuit group Z are connected to the same first constant voltage signal line H1. In the embodiment of the present application, the "n pixel circuits in a pixel circuit group Z are connected to the same first constant voltage signal line H1" can be understood as follows: in the area where the pixel circuit group Z is located or in the adjacent area, only the signal line segment belonging to the first constant voltage signal line H1 is arranged, and the pixel circuits in the pixel circuit group Z are electrically connected to the first constant voltage signal line H1 through the first connecting part, wherein the signal line segment has the same direction as the first constant voltage signal line H1, and the signal line segment belongs to a part of the first constant voltage signal line H1. In other words, in the first display area AA1, for the pixel circuits arranged in the second direction y, n pixel circuits correspond to one first constant voltage signal line; a pixel circuit group includes n pixel circuits arranged in the second direction y, and for the pixel circuit groups arranged in the first direction x, one pixel circuit group corresponds to one first constant voltage signal line.

[0109] For the pixel circuit group Z, the n pixel circuits in the pixel circuit group Z are arranged in the second direction y, and the first constant voltage signal line H1 is arranged in the first direction x. The n pixel circuits in the pixel circuit group Z are connected to the same first constant voltage signal line H1. Figure 14 The schematic pixel circuit structure can be understood with reference to the circuit diagram of the pixel circuit in Figure 4 , which will not be described here again. The display panel has a multi-film layer stack structure, and when connecting the structures at different layers in the display panel, a via hole in an insulating layer is needed to connect the structures, Figure 14 The via hole position Ko is marked in the figure, wherein the first electrode of the first light-emitting control transistor T5 is electrically connected to the power supply signal line P through the via hole at the via hole position Ko. For the via holes at other positions in the pixel circuit, reference can be made to the circuit diagram of the pixel circuit in Figure 4 and the description in the following embodiment related to the film layer structure of the display panel.

[0110] Figure 14 In the embodiment, the constant voltage signal line is a reset signal line Ref.

[0111] Figure 15 Another partial schematic diagram of a display panel is provided in the embodiment of the present application, and the pixel circuits are arranged in a pixel circuit row in the second direction y, as shown in Figure 15 In the figure, one pixel circuit row in the first display area AA1, two pixel circuit rows in the second display area AA2, and the border area between the first display area AA1 and the second display area AA2 are shown. Among them, the first constant voltage signal line H1 in the first display area AA1 is arranged in the same way as in Figure 14The same in the embodiment. Three pixel circuits arranged in the second direction y in the second display area AA2 correspond to one second constant voltage signal line H2. In another embodiment, three pixel circuits arranged in the second direction y in the second display area AA2 correspond to three second constant voltage signal lines H2, that is, the pixel circuits are arranged into pixel circuit columns in the first direction x, and one pixel circuit column corresponds to one second constant voltage signal line H2, which is not shown in the figure.

[0112] In Figure 15 The reset signal line Ref includes the first constant voltage signal line H1 in the first display area AA1 and the second constant voltage signal line H2 in the second display area AA2 in the embodiment. The distance D1 between two adjacent first constant voltage signal lines H1 is greater than the distance D2 between two adjacent second constant voltage signal lines H2. Figure 15 The first constant voltage signal line H1 is connected with the second constant voltage signal line H2 in the embodiment. In some embodiments, the first constant voltage signal line H1 can not be connected with the second constant voltage signal line H2. The wiring mode of the reset signal line Ref is designed in combination with the arrangement mode of the pixel circuit 21 in the first display area AA1 in the embodiment, which reduces the number of reset signal lines set in the first display area AA1. On the one hand, in the second direction y, only one reset signal line Ref needs to be set in the area corresponding to one pixel circuit group Z, which can reduce the width of the circuit area QD in the second direction y; on the other hand, in the extension direction of the reset signal line Ref, the reset signal line Ref is extended from the circuit area QD to the wiring area ZD, which can also reduce the number of reset signal lines Ref set in the wiring area ZD, thereby facilitating the reduction of the width of the wiring area in the second direction y. The embodiment can design the reset signal line in the first display area AA1 to reduce the area of the non-transparent wiring in the first display area AA1, thereby increasing the area of the transparent area in the first display area AA1.

[0113] In the embodiment, the signal lines are divided according to the areas where the line segments of the signal lines are located. At least part of the signal lines includes signal line subsegments and signal line branch segments connected with each other, wherein the signal line subsegments are located in the circuit area, and the signal line branch segments are located in the wiring area. In some embodiments, for one signal line, the signal line branch segment connects two adjacent signal line subsegments. That is, the signal line branch segment is the signal transmission line segment located in the wiring area, and the signal line subsegment is the signal line segment electrically connected with the pixel circuit in the circuit area.

[0114] As Figure 14The power signal line P and the data line D extending along the first direction x, the first scan line S1, the second scan line S2, the third scan line S3 and the light emitting control line E extending along the second direction y are shown in the figure. Among them, the power signal line P includes a power signal line sub-section Pa located in the circuit area QD, the data line D includes a data line sub-section Da located in the circuit area QD, the first scan line S1 includes a first scan line sub-section S1a located in the circuit area QD, the second scan line S2 includes a second scan line sub-section S2a located in the circuit area QD, the third scan line S3 includes a third scan line sub-section S3a located in the circuit area QD, and the light emitting control line E includes a light emitting control line sub-section Ea located in the circuit area QD. In the present application Figure 14 In the embodiment, the first constant voltage signal line H1 and the data line D extend in substantially the same direction.

[0115] Specifically, in the pixel circuit, the first electrode of the first light emitting control transistor T5 is electrically connected with the power signal line sub-section Pa, and the first electrode of the data write transistor T1 is electrically connected with the data line sub-section Da. The control end of the data write transistor T1 belonging to the same pixel circuit group Z is electrically connected with the same first scan line sub-section S1a; the control end of the first light emitting control transistor T5 and the control end of the second light emitting control transistor T6 belonging to the same pixel circuit group Z are electrically connected with the same light emitting control line sub-section Ea; the control end of the first reset transistor T3 belonging to the same pixel circuit group Z is electrically connected with the second scan line sub-section S2a; and the control end of the second reset transistor T4 belonging to the same pixel circuit group Z is electrically connected with the third scan line sub-section S3a.

[0116] Continuing to refer to Figure 14 The first connection part 1J includes a first sub-connection part 1Ja and a second sub-connection part 1Jb. The second electrode of the first reset transistor T3 belonging to the same pixel circuit group Z is electrically connected with the first constant voltage signal line H1 through the first sub-connection part 1Ja; and the second electrode of the second reset transistor T4 belonging to the same pixel circuit group Z is electrically connected with the first constant voltage signal line H1 through the second sub-connection part 1Jb. When the pixel circuit 21 is working, the second electrode of the first reset transistor T3 and the second electrode of the second reset transistor T4 receive the voltage signal provided by the same first constant voltage signal line H1. In this embodiment, according to the positions of the first reset transistor T3 and the second reset transistor T4 in the pixel circuit structure, the corresponding first sub-connection part 1Ja and the second sub-connection part 1Jb are arranged respectively, without changing the relative positions of the layouts of the transistors in the pixel circuit, and the first sub-connection part 1Ja and the second sub-connection part 1Jb do not need to be wired in the circuit area QD, so the arrangement of the first connection part has less impact on the space occupied by the circuit area QD.

[0117] In another embodiment, the constant voltage signal line is the power signal line. Figure 16This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 17 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 16 For reference, see the medium pixel circuit. Figure 8 Understanding the mid-pixel circuitry. Figure 16 Only some signal lines and transistors are shown in the diagram. Figure 17 Zhongyu Figure 14 The same parts can be referred to for understanding, and will not be repeated here.

[0118] like Figure 16 As shown, within the first display area AA1: the pixel circuit group Z includes three pixel circuits 21 arranged in the second direction y, and the pixel circuits 21 in the same pixel circuit group Z are electrically connected to the same first constant voltage signal line H1. Figure 16 The diagram illustrates a first reset signal line 1Ref and a second reset signal line 2Ref. The first reset signal line 1Ref includes a first reset signal line segment 1Refa located in circuit region QD, and the second terminal of the first reset transistor T3 is electrically connected to the first reset signal line segment 1Refa. The second reset signal line 2Ref includes a second reset signal line segment 2Refa located in circuit region QD, and the second terminal of the second reset transistor T4 is electrically connected to the second reset signal line segment 2Refa.

[0119] Specifically, the first connecting part 1J includes a third sub-connecting part 1Jc. The first electrode of the first light-emitting control transistor T5, belonging to the same pixel circuit group Z, is electrically connected to the first constant voltage signal line H1 through the third sub-connecting part 1Jc. Moreover, the third sub-connecting part 1Jc is designed according to the position of the first light-emitting control transistor T5 in the pixel circuit structure, without changing the layout position of each transistor in the pixel circuit. Furthermore, the third sub-connecting part does not need to be wound in the circuit area QD, and the setting of the third sub-connecting part has a small impact on the space occupied by the circuit area QD.

[0120] exist Figure 16 In this embodiment, the extension direction of the first constant voltage signal line H1 is approximately the same as the extension direction of the data line D. The extension direction of the reset signal line Ref is the second direction y. In this embodiment, the first signal line extending in the first direction x includes the power signal line P and the data line D, and the second signal line extending in the second direction y includes the first scan line S1, the second scan line S2, the third scan line S3, the light emission control line E, and the reset signal line Ref.

[0121] Figure 16 In this embodiment, the first constant voltage signal line H1 is the power supply signal line P. Figure 16The first constant voltage signal line H1 is extended from the circuit region QD into the wiring region ZD, and is electrically connected to the same power signal line P through the pixel circuit 21 in the pixel circuit group Z in the first display region AA1. The number of the first power signal lines extended into the wiring region ZD can be reduced, and thus the width of the wiring region ZD in the second direction y can be reduced, which is beneficial to reducing the area of the non-transparent wiring in the first display region AA1.

[0122] For example, the pixel circuits are arranged into pixel circuit rows in the second direction y, Figure 17 In the embodiment, one pixel circuit row in the first display region AA1, two pixel circuit rows in the second display region AA2, and the border region between the first display region AA1 and the second display region AA2 are shown. Figure 17 In the embodiment, the constant voltage signal line is the power signal line P. The first constant voltage signal line H1 in the first display region AA1 is arranged in the same way as Figure 16 In the embodiment, the three pixel circuits arranged in the second direction y in the second display region AA2 correspond to three second constant voltage signal lines H2, that is, the pixel circuits are arranged into pixel circuit columns in the first direction x, and one pixel circuit column corresponds to one second constant voltage signal line H2. In another embodiment, the three pixel circuits arranged in the second direction y in the second display region AA2 correspond to one second constant voltage signal line H2, which is not shown in the figure.

[0123] Figure 17 In the embodiment, the power signal line includes the first constant voltage signal line H1 in the first display region AA1 and the second constant voltage signal line in the second display region AA2. The distance D1 between the two adjacent first constant voltage signal lines H1 is greater than the distance D2 between the two adjacent second constant voltage signal lines H2. Figure 17 In the embodiment, the first constant voltage signal line H1 is connected to the second constant voltage signal line H2. In some embodiments, the first constant voltage signal line H1 can not be connected to the second constant voltage signal line H2. In the embodiment, the arrangement of the pixel circuit 21 in the first display region AA1 is combined with the design of the power signal line P. In the extension direction of the power signal line P, the power signal line P is extended from the circuit region QD to the wiring region ZD. The number of the power signal lines P arranged in the wiring region ZD can be reduced, and thus the width of the wiring region ZD in the second direction y can be reduced. The power signal line in the first display region AA1 is designed to reduce the area of the non-transparent wiring, and thus the area of the transparent region in the first display region AA1 is increased.

[0124] In addition, in the embodiment, Figure 17In the embodiment, as shown in the schematic at the position of region Q4 in the figure, the corresponding semiconductor layers W in two pixel circuits (pixel circuit 21a and pixel circuit 21b) adjacent in the first direction x (i.e., adjacent in the column direction) are disconnected from each other, so that the first reset transistor T3 of the pixel circuit 21b is not connected to the second reset transistor T4 of the pixel circuit 21a. In this embodiment, for one pixel circuit, the second electrode of the first reset transistor T3 and the second electrode of the second reset transistor T4 are connected to different reset signal lines, as described above Figure 16 The second electrode of the first reset transistor T3 is electrically connected to the first reset signal line 1Ref, and the second electrode of the second reset transistor T4 is electrically connected to the second reset signal line 2Ref. By disconnecting the corresponding semiconductor layers W in two pixel circuits adjacent in the first direction x, when the control terminal of the driving transistor is reset after the first reset transistor T3 of the pixel circuit 21b is turned on, the reset signal on the first reset signal line connected to the first reset transistor T3 does not interfere with the voltage signal received by the second electrode of the second reset transistor T4 in the pixel circuit 21a, that is, it is ensured that the second electrode of the second reset transistor T4 can receive the reset signal on the second reset signal line to reset the first electrode of the light emitting device in the operation of the pixel circuit 21a. To ensure that the second electrode of the first reset transistor and the second electrode of the second reset transistor respectively receive different reset signals in the operation of one pixel circuit.

[0125] In another embodiment, Figure 18 Another partial schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 6. As shown in FIG. 6, the display panel includes a first display area AA1 and a second display area AA2. The first display area AA1 includes a first circuit region QD, and the second display area AA2 includes a second circuit region QE. The first circuit region QD and the second circuit region QE are connected to each other by a first display area AA1 and a second display area AA2. The first circuit region QD includes a plurality of pixel circuits 21 arranged in a matrix form. The pixel circuits 21 in the first circuit region QD are connected to a first reset signal line 1Ref and a second reset signal line 2Ref. The first reset signal line 1Ref and the second reset signal line 2Ref are arranged in the first direction x. The first reset signal line 1Ref and the second reset signal line 2Ref are arranged in the second direction y. The first reset signal line 1Ref and the second reset signal line 2Ref are arranged in the first display area AA1 and the second display area AA2. Figure 18 A circuit region QD in the first display area AA1 is shown in FIG. 6. The first signal lines extending in the first direction x include a power signal line P, a data line D, and a reset signal line Ref. The second signal lines extending in the second direction y include a first scan line S1, a second scan line S2, a third scan line S3, and a light emitting control line E. The pixel circuits 21 in the same pixel circuit group Z are connected to the same reset signal line Ref. Specifically, the second electrode of the first reset transistor T3 belonging to the same pixel circuit group Z is electrically connected to the reset signal line Ref through a first sub-connection part 1Ja, and the second electrode of the second reset transistor T4 belonging to the same pixel circuit group Z is electrically connected to the reset signal line Ref through a second sub-connection part 1Jb. The pixel circuits 21 in the same pixel circuit group Z are connected to the same power signal line P. Specifically, the first electrode of the first light emitting control transistor T5 belonging to the same pixel circuit group Z is electrically connected to the power signal line P through a third sub-connection part 1Jc. This embodiment designs the reset signal line Ref and the power signal line P in the first display area AA1, which can reduce the area of the non-transparent area and thus increase the area of the transparent area of the first display area AA1.

[0126] The following embodiments illustrate the film layer structure of the display panel provided by the present invention, so as to explain the film layer location of each signal line and the structure in the pixel circuit.

[0127] Optional, Figure 19 for Figure 14 A schematic diagram of the cross-section at the position of the midtangent B-B' is shown below. Figure 19 As shown, the display panel includes a substrate 10, and a semiconductor layer W, a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4 disposed on the substrate 10 in a direction away from the substrate 10. The display panel also includes insulating layers (not shown) located between adjacent metal layers and between the semiconductor layer and the metal layer. The semiconductor layer W is made of silicon or metal oxide. In one optional embodiment, the semiconductor layer W comprises a low-temperature polycrystalline silicon. In another optional embodiment, the semiconductor layer W comprises indium gallium zinc oxide.

[0128] The pixel circuit 21 includes a channel and a storage capacitor Cst. Specifically, each transistor in the pixel circuit 21 includes a channel. Figure 19 The diagram illustrates the channel m of the driving transistor Tm, located in the semiconductor layer W. The storage capacitor Cst includes a first plate Ca and a second plate Cb, with the first plate Ca located in the first metal layer M1 and the second plate Cb located in the second metal layer M2. The light-emitting control line segment Ea is located in the first metal layer M1, the third scan line segment S3a is located in the third metal layer M3, and the data line segment Da is located in the fourth metal layer M4. Figure 19 The diagram also illustrates that the first constant voltage signal line H1 is located in the fourth metal layer M4, wherein the second sub-connection portion 1Jb is located in the semiconductor layer W, and the second sub-connection portion 1Jb is electrically connected to the first constant voltage signal line H1 through a via K in the insulating layer. In some optional embodiments, the first constant voltage signal line H1 extends in the same direction as the data line, and the first constant voltage signal line H1 and the data line segment Da are located in the same metal layer. By setting the first constant voltage signal line H1 and the signal line extending in the same direction in the same metal layer, while ensuring that different signal lines extending in the same direction are insulated from each other, setting the signal lines extending in the same direction in the same layer can reduce the number of metal layers in the display panel. The signal lines and other components located in the metal layers in the display panel need to be fabricated using photolithography. Structures located in the same metal layer can be fabricated using the same photolithography process. The number of metal layers is related to the photolithography process. By reducing the number of metal layers in the display panel, the number of photolithography processes can be reduced, thereby simplifying the manufacturing process and reducing process costs.

[0129] Figure 19In this embodiment, the first connection portion 1J is only shown as being located in the semiconductor layer W. In some alternative embodiments, the first connection portion 1J is located in any one of the first metal layer M1, the second metal layer M2, and the third metal layer M3, which will not be shown in the accompanying drawings. When the length of the first connection portion is the same, placing the first connection portion in a metal layer can reduce the resistance of the first connection portion, thereby reducing the voltage drop of the voltage signal transmitted on the first constant voltage signal line.

[0130] In some embodiments, the first connection portion is located in two or more of the semiconductor layer W, the first metal layer M1, the second metal layer M2, and the third metal layer M3. Taking the first sub-connection portion 1Ja as an example, the first sub-connection portion 1Ja includes a first sub-part located in the semiconductor layer W and a second sub-part located in the first metal layer M1. The first sub-part and the second sub-part at least partially overlap and are connected in parallel, which can reduce the resistance of the first sub-connection portion 1Ja. The first sub-part and the second sub-part are equivalent to a double-layer trace. That is, in this embodiment, the first connection portion is set as a parallel double-layer or multi-layer trace, which can reduce the overall resistance of the first connection portion, thereby reducing the overall voltage drop of the constant voltage signal line.

[0131] in addition, Figure 14 In this embodiment, the first scan line segment S1a and the second scan line segment S2a in the circuit region QD are located in the third metal layer M3, that is, the first scan line segment S1a, the second scan line segment S2a and the third scan line segment S3a are located in the same layer. The power signal line segment Pa is located in the fourth metal layer, that is, the power signal line segment Pa and the data line segment Da are located in the same metal layer.

[0132] exist Figure 16 In this embodiment, channel m is located in semiconductor layer W. The first electrode Ca of storage capacitor Cst is located in first metal layer M1, and the second electrode Cb is located in second metal layer M2. The light emission control line segment Ea, the first reset signal line segment 1Refa, and the second reset signal line segment 2Refa are located in first metal layer M1, the three scan line segments are located in third metal layer M3, and the data line segment Da and the first constant voltage signal line H1 are located in fourth metal layer M4.

[0133] In this embodiment of the invention, the display panel includes a semiconductor layer on a substrate, and a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer sequentially disposed away from the substrate on the semiconductor layer. The channels of each transistor in the pixel circuit are located in the semiconductor layer. The first electrode of the storage capacitor is located in the first metal layer, and the second electrode of the storage capacitor is located in the second metal layer. Data lines, scan lines (including a first scan line, a second scan line, and a third scan line), reset signal lines, power signal lines, and light emission control lines are rationally routed within the four metal layers (first metal layer, second metal layer, third metal layer, and fourth metal layer).

[0134] In some embodiments, the first metal layer and the second metal layer are made of the same material, and the third metal layer and the fourth metal layer are made of the same material. The material of the first metal layer and the second metal layer includes molybdenum, and the material of the third metal layer and the fourth metal layer includes one or more of titanium, aluminum, and molybdenum. In one embodiment, the third metal layer and the fourth metal layer are a titanium / aluminum / titanium three-layer structure. In another embodiment, the third metal layer and the fourth metal layer are a molybdenum / aluminum / molybdenum three-layer structure.

[0135] In another embodiment, Figure 20 Another partial schematic diagram of a display panel is provided for an embodiment of the present application, as shown in FIG. 6. The display panel includes a first display area AA1 and a second display area AA2. The first display area AA1 and the second display area AA2 are arranged in the first direction x. The first display area AA1 and the second display area AA2 are arranged in the second direction y. The first display area AA1 and the second display area AA2 are arranged in the third direction z. Figure 20 The driving transistor Tm and other transistors in the pixel circuit are schematically shown in FIG. 6. The pixel circuit in FIG. 6 can be understood in combination with the pixel circuit schematically shown in FIG. 5. Figure 20 The pixel circuit in FIG. 6 can be understood in combination with the pixel circuit schematically shown in FIG. 5. Figure 4 The pixel circuit in FIG. 6 can be understood in combination with the pixel circuit schematically shown in FIG. 5. Figure 20 A circuit region QD in the first display area AA1 is schematically shown in FIG. 6. The circuit region QD includes a pixel circuit group. The pixel circuit group includes three pixel circuits 21 arranged in the second direction y. The circuit region QD is provided with a power supply signal line subsegment Pa, a data line subsegment Da, a first scan line subsegment S1a, a second scan line subsegment S1a, a third scan line subsegment S3a, an emission control line subsegment Ea, and a first constant voltage signal line H1 electrically connected to the pixel circuits 21. The connection relationship between each signal line subsegment and the transistors in the pixel circuits 21 can be understood in reference to the description of the above embodiments, which will not be repeated here. The pixel circuits 21 in a pixel circuit group are connected to the same first constant voltage signal line H1 through the first connection portion 1J. Figure 14 A circuit region QD in the first display area AA1 is schematically shown in FIG. 6. The circuit region QD includes a pixel circuit group. The pixel circuit group includes three pixel circuits 21 arranged in the second direction y. The circuit region QD is provided with a power supply signal line subsegment Pa, a data line subsegment Da, a first scan line subsegment S1a, a second scan line subsegment S1a, a third scan line subsegment S3a, an emission control line subsegment Ea, and a first constant voltage signal line H1 electrically connected to the pixel circuits 21. The connection relationship between each signal line subsegment and the transistors in the pixel circuits 21 can be understood in reference to the description of the above embodiments, which will not be repeated here. The pixel circuits 21 in a pixel circuit group are connected to the same first constant voltage signal line H1 through the first connection portion 1J.

[0136] In Figure 20In the embodiment, the channel of each transistor in the pixel circuit is located in the semiconductor layer W, the first plate Ca of the storage capacitor Cst, the first scan line sub-section S1a, the second scan line sub-section S2a, and the third scan line sub-section S3a are located in the first metal layer M1, the second plate Cb of the storage capacitor Cst and the light-emitting control line sub-section Ea are located in the second metal layer M2, the data line sub-section Da and the power signal line sub-section Pa are located in the third metal layer M3. The first constant voltage signal line H1 is located in the third metal layer M3, that is, the first constant voltage signal line H1 is located in the same metal layer as the data line sub-section Da. The first constant voltage signal line H1 and the signal line extending in the same direction are located in the same metal layer, which can reduce the number of metal layers in the display panel under the premise of ensuring the insulation between the signal lines extending in the same direction. The signal lines and other elements located in the metal layer in the display panel need to be manufactured by photolithography process, and the structures located in the same metal layer can be manufactured by the same photolithography process. The number of metal layers is related to the process of photolithography process, and the number of processes of photolithography process can be reduced by reducing the number of metal layers in the display panel, thereby simplifying the manufacturing process and reducing the process cost.

[0137] In some embodiments, the first metal layer and the second metal layer are made of the same material. The material for manufacturing the first metal layer and the second metal layer includes molybdenum, and the material for manufacturing the third metal layer includes one or more of titanium, aluminum, and molybdenum. In one embodiment, the third metal layer is a three-layer structure of titanium / aluminum / titanium. In another embodiment, the third metal layer is a three-layer structure of molybdenum / aluminum / molybdenum.

[0138] In this embodiment, the first constant voltage signal line H1 is a reset signal line Ref, the first connection part 1J includes a first sub-connection part 1Ja and a second sub-connection part 1Jb, and the first sub-connection part 1Ja and the second sub-connection part 1Jb are located in the first metal layer M1.

[0139] Figure 20 In the embodiment, the pixel circuit is the same as that in the embodiment, and the difference lies in the film layer structure of the display panel. Figure 14 The pixel circuit in the embodiment is the same as that in the embodiment, and the difference lies in the film layer structure of the display panel. Figure 14 In the embodiment, the pixel circuit is formed by reasonably arranging the semiconductor layer and the four metal layers above the substrate, Figure 20 In the embodiment, the pixel circuit is formed by reasonably arranging the semiconductor layer and the three metal layers above the substrate, and each signal line connected to the pixel circuit.

[0140] Figure 20 In the embodiment, the light-emitting control line sub-section Ea is located in the second metal layer M2. In another embodiment, the light-emitting control line sub-section Ea is located in the first metal layer M1, and the film layer positions of the other signal lines are the same as those in the Figure 20 same as those in the embodiment, and are not illustrated in the drawings.

[0141] In addition, Figure 20 The first connecting portion 1J is only shown in the first metal layer M1 in the embodiment, and in some optional embodiments, the first connecting portion 1J is located in the semiconductor layer W or the second metal layer M2. When the length of the first connecting portion is the same, the first connecting portion is arranged in the metal layer to reduce the resistance of the first connecting portion, thereby reducing the voltage drop of the voltage signal transmitted on the first constant voltage signal line.

[0142] In some embodiments, the first connecting portion 1J is located in at least two of the semiconductor layer, the first metal layer and the second metal layer, that is, the first connecting portion is a double-layer or a three-layer wiring connected in parallel, which can reduce the resistance of the first connecting portion as a whole, thereby reducing the voltage drop of the constant voltage signal line as a whole.

[0143] Optionally, the display panel further comprises a fourth metal layer. Optionally, the fourth metal layer is made of the same material as the third metal layer. Figure 21 Another partial schematic view of a display panel provided in the embodiment of the present application is shown in FIG. 6. Figure 22 As Figure 21 A schematic view of a cross section at the position of the tangent line C-C' is shown in FIG. 7. Figure 21 The wiring mode of the circuit region QD in the embodiment is basically the same as that in the first embodiment, and the same parts can be understood by referring to the first embodiment, which will not be described here. Figure 20 The wiring mode of the circuit region QD in the embodiment is basically the same as that in the first embodiment, and the same parts can be understood by referring to the first embodiment, which will not be described here.

[0144] As Figure 21 And Figure 22 As shown in the embodiment, the display panel further comprises an auxiliary power signal line P', wherein the auxiliary power signal line P' is located in the fourth metal layer M4, and the power signal line segment Pa is located in the third metal layer M3. In the direction e perpendicular to the plane in which the substrate 10 is located, the auxiliary power signal line P' at least partially overlaps the power signal line segment Pa, and the auxiliary power signal line P' and the power signal line segment Pa overlapping therewith are electrically connected through the via K1. The auxiliary power signal line P' and the power signal line segment Pa are connected in parallel, which can reduce the voltage drop loss on the power signal line, thereby reducing the power consumption of the display panel.

[0145] In addition, Figure 22 In the embodiment, the threshold compensation transistor T2 and the first reset transistor T3 in the pixel circuit are also shown. The via K2 is a structure for realizing the electrical connection between the second electrode of the first reset transistor T3 and the first constant voltage signal line H1 (i.e., the reset signal line Ref).

[0146] In some embodiments, as Figure 4 And Figure 8In the illustrated pixel circuit, the control terminal of the first reset transistor T3 is electrically connected to the second scan line S2, and the control terminal of the second reset transistor T4 is electrically connected to the third scan line S3. That is, in some embodiments, the first reset transistor T3 and the second reset transistor T4 are controlled by different scan lines. Specifically, four sets of driving circuits are arranged in the non-display area of ​​the display panel to provide signals to the first scan line, the second scan line, the third scan line, and the light emission control line in the display area.

[0147] Figure 23 A partial schematic diagram of another display panel provided in an embodiment of the present invention, as shown below. Figure 23 As shown, the display panel also includes a non-display area BA, which includes a first scan driving circuit 61, a second scan driving circuit 62, a third scan driving circuit 63, and a light-emitting driving circuit 64. The first scan driving circuit 61 includes multiple cascaded first shift registers VSR1, with a second scan line segment S2a corresponding to a pixel circuit group Z extending into the non-display area BA and electrically connected to the output of the same first shift register VSR1. The second scan driving circuit 62 includes multiple cascaded second shift registers VSR2, with a first scan line segment S1a corresponding to a pixel circuit group Z extending into the non-display area BA and electrically connected to the output of the second shift register VSR2. The third scan driving circuit 63 includes multiple cascaded third shift registers VSR3, with a third scan line segment S3a corresponding to a pixel circuit group Z extending into the non-display area BA and electrically connected to the output of the third shift register VSR3. The light-emitting driving circuit 64 includes multiple cascaded fourth shift registers VSR4. The light-emitting control line segment Ea corresponding to a pixel circuit group Z extends into the non-display area BA and is electrically connected to the output terminal of the fourth shift register VSR4.

[0148] In some implementations, such as Figure 6 In the illustrated pixel circuit, the control terminals of both the first reset transistor T3 and the second reset transistor T4 are electrically connected to the second scan line S2. When the pixel circuit is operating, the control terminals of the first reset transistor T3 and the second reset transistor T4 receive the same control signal; that is, the reset of the control terminal of the driving transistor Tm and the reset of the first electrode of the light-emitting device occur simultaneously. The following section will combine... Figure 6 The following example illustrates a specific implementation where the control terminals of the first reset transistor T3 and the second reset transistor T4 receive the same control signal. Figure 24 and Figure 25 In the embodiments and Figure 14 The same structures in the embodiments can be understood by reference, and will not be repeated here.

[0149] Specifically, in one embodiment, Figure 24A partial schematic diagram of another display panel provided in an embodiment of the present invention, as shown below. Figure 24 As shown, a circuit area QD within the first display area AA1 is illustrated. The display panel also includes a second connecting portion 2J. At the opposite edges of the pixel circuit group Z along the second direction y, the second scan line segment S2a and the third scan line segment S3a are electrically connected via the second connecting portion 2J. The pixel circuit group Z includes n pixel circuits, which mainly include driving transistors and switching transistors. Considering the areas where the transistors in the n pixel circuits are located as a whole, the edge of the pixel circuit group Z is understood as the periphery of the areas where the transistors in the n pixel circuits are located. In this embodiment, the second connecting portion is located at the edge of the pixel circuit group, without affecting the wiring of each pixel circuit in the pixel circuit group. This arrangement reduces the number of scan lines in the wiring area when the scan line extends from the circuit area to the wiring area, thereby further reducing the space occupied by the non-transparent area and correspondingly increasing the area of ​​the transparent area within the first display area.

[0150] Optionally, in another embodiment, Figure 25 This is a partially simplified schematic diagram of another display panel provided in an embodiment of the present invention. Figure 25 The structure of the mid-pixel circuit is shown in a simplified diagram. For example... Figure 25 As shown, the display panel also includes a non-display area BA, which includes a first scan driving circuit 61. The first scan driving circuit 61 includes multiple cascaded first shift registers VSR1. The second scan line segment S2a and the third scan line segment S3a corresponding to a pixel circuit group Z extend into the non-display area BA and are electrically connected to the output terminal of the same first shift register VSR1. Specifically, the non-display area BA also includes a second scan driving circuit 62 and a light-emitting driving circuit 64. The second scan driving circuit 62 includes multiple cascaded second shift registers VSR2. The first scan line segment S1a corresponding to a pixel circuit group Z extends into the non-display area BA and is electrically connected to the output terminal of the second shift register VSR2. The light-emitting driving circuit 64 includes multiple cascaded fourth shift registers VSR4. The light-emitting control line segment Ea corresponding to a pixel circuit group Z extends into the non-display area BA and is electrically connected to the output terminal of the fourth shift register VSR4. This embodiment reduces the number of driving circuits in the non-display area, thereby reducing the space occupied by the non-display area and improving the screen-to-body ratio of the display panel.

[0151] The following embodiment illustrates the relative positions of the first constant voltage signal line and its corresponding pixel circuit group within the first display area.

[0152] Optionally, within the first display area AA1: such as Figure 14As shown, the first constant voltage signal line H1, electrically connected to pixel circuit group Z, is located between two adjacent pixel circuits 21 in pixel circuit group Z. It should be noted that the wiring of pixel circuits 21 in the display panel is relatively complex, and to ensure space utilization, there may not be a large blank space between adjacent pixel circuits 21 for routing. Therefore, the first constant voltage signal line H1 can overlap with certain structures of the pixel circuit 21. Overlap refers to the overlap of two or more structures in the projection direction onto the plane of the substrate. For example, the first constant voltage signal line H1 overlaps with the semiconductor layer W. In this embodiment of the invention, the first constant voltage signal line H1 being located between two adjacent pixel circuits 21 is understood as follows: the first constant voltage signal line H1 is located between the centers of two adjacent pixel circuits 21, and the center of the pixel circuit 21 is located in the region where the driving transistor Tm is located. The first constant voltage signal line H1 is positioned between two adjacent pixel circuits 21 in its corresponding pixel circuit group. That is, for a given first constant voltage signal line H1, the pixel circuits 21 on both sides of and electrically connected to it belong to the same pixel circuit group Z. This arrangement of the first constant voltage signal line H1 minimizes the length of the first connection portion 1J, thereby reducing the overall space occupied by the circuit area QD. Furthermore, when the first constant voltage signal line H1 extends from the circuit area QD to the routing area, signal lines extending in the same direction as the first constant voltage signal line H1 all converge towards the location of the first virtual center line of the circuit area QD within the routing area (hereinafter...). Figure 29 The schematic convergence routing method can reduce the winding of signal lines and also help to reduce the overall space occupied by the circuit area QD, thereby increasing the area of ​​the light-transmitting area of ​​the first display area AA1.

[0153] In another embodiment, Figure 26 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 26 As shown, within the first display area AA1: the first constant voltage signal line H1, electrically connected to the pixel circuit group Z, is located at the edge of the pixel circuit group Z. The edge of the pixel circuit group Z is understood as the edge of the area occupied by each transistor arranged in the pixel circuit group Z. Therefore, the main structure of the pixel circuit 21 (driving transistors and each switching transistor) in the pixel circuit group Z is located on the same side of the first constant voltage signal line H1. Figure 26 The driving transistors of the pixel circuit 21 shown in the diagram are all located to the left of the first constant voltage signal line H1. This embodiment can be used in conjunction with the wiring method within the wiring area, such as with the following... Figure 32The signal line convergence mode in the wiring area is combined in the embodiment, which can reduce the wiring of the first constant voltage signal line when it extends from the circuit area QD to the wiring area, and also can maximize the area of the light transmission area between the two adjacent circuit areas to reduce the diffraction of the ambient light when it penetrates the first display area. When applied to the under-screen photosensitive device scheme, the optical performance of the photosensitive device is improved.

[0154] In another embodiment, Figure 27 Another partial schematic diagram of a display panel is provided for the embodiment of the present application. Figure 27 The pixel circuit structures in the figures are simplified schematics. As shown in the figure, Figure 27 In the first display area AA1, the pixel circuit groups Z located on both sides of and adjacent to the first constant voltage signal line H1 are connected to the first constant voltage signal line H1. Figure 27 In the figure, one circuit area QD includes two pixel circuit groups Z. Specifically, one pixel circuit group Z can drive one pixel unit to emit white light. This embodiment can further reduce the number of first constant voltage signal lines H1, thereby further reducing the area of the non-light transmission area in the first display area, correspondingly increasing the area of the light transmission area in the first display area, and improving the light transmission rate of the first display area.

[0155] In another embodiment, Figure 28 Another partial schematic diagram of a display panel is provided for the embodiment of the present application. As shown in the figure, Figure 28 As shown in the figure, the pixel circuit groups Z located on both sides of the first constant voltage signal line H1 are misaligned in the second direction y. That is, the pixel circuit groups Z located on both sides of and connected to the first constant voltage signal line H1 are not aligned in the second direction y. As shown in the figure, Figure 28 As shown in the figure, the pixel circuit groups Z1 and Z2 are misaligned in the second direction y, and the misalignment distance of the pixel circuit groups Z1 and Z2 in the first direction x is d. The pixel circuits in the pixel circuit group Z1 are electrically connected to the first constant voltage signal line H1 through the first connection part 1J-1, and the pixel circuits in the pixel circuit group Z2 are electrically connected to the first constant voltage signal line H1 through the first connection part 1J-2, Figure 28 In the figure, the misalignment distance d of the two pixel circuit groups is represented by the distance between the first connection part 1J-1 and the first connection part 1J-2. In some embodiments, the misalignment distance d of the two pixel circuit groups is represented by the distance between the same structures in the two pixel circuit groups in the first direction x.

[0156] In some embodiments, d is not less than the length of one pixel circuit 21 in the first direction x. The larger d is, the more sparse the arrangement of the pixel circuit groups is, and the larger the total area of the light transmission area formed between the circuit areas is, which is beneficial to improving the overall light transmission rate of the first display area.

[0157] The above embodiment improves the light transmittance of the first display area by designing the wiring mode of the first constant voltage signal line, to ensure the demand for the light transmittance of the display panel in the under-screen photosensitive device. Further, the wiring mode of the signal line between the adjacent circuit areas in the first display area is designed in the embodiment of the application, to reduce the diffraction when the ambient light penetrates the first display area, to improve the imaging effect of the photosensitive device in the under-screen photosensitive device scheme.

[0158] Specifically, the signal lines with the same extension direction are wired in a converging manner between the adjacent circuit areas in the embodiment of the application, to concentrate and set the signal lines with the same extension direction, to reduce the diffraction phenomenon when the ambient light penetrates the first display area.

[0159] In an embodiment, Figure 29 Another partial schematic view of a display panel is provided in the embodiment of the application. As Figure 29 shown, the first display area AA1 includes a circuit area QD and a wiring area ZD, and the circuit area QD includes one pixel circuit group Z for illustration. The wiring area ZD is arranged between two adjacent circuit areas QD, and the wiring area ZD is provided with a signal line segment.

[0160] The signal line includes a first signal line 1X extending in a first direction x and a second signal line 2X extending in a second direction y. The extension direction of the signal line is understood as the general trend of the signal line. The first signal line 1X includes a first constant voltage signal line H1, and three pixel circuits 21 in one pixel circuit group Z are connected to the same first constant voltage signal line H1, that is, one pixel circuit group Z corresponds to one constant voltage signal line H1. In an embodiment, the first constant voltage signal line H1 is a reset signal line, and the first signal line 1X further includes a data line and a power signal line. The second signal line includes a first scan line, a second scan line, a third scan line, and a light-emitting control line. In another embodiment, the first constant voltage signal line H1 is a power signal line, and the first signal line 1X further includes a data line and a reset signal line. The second signal line includes a first scan line, a second scan line, a third scan line, and a light-emitting control line.

[0161] As Figure 29The first sub-signal line X-1 and the second sub-signal line X-2 extending in the same direction are shown in the figure, the first sub-signal line X-1 includes a first sub-signal line sub-section X-1a located in the circuit region QD and a first sub-signal line branch X-1b located in the wire region ZD, and the first sub-signal line sub-section X-1a and the first sub-signal line branch X-1b are connected to each other; the second sub-signal line X-2 includes a second sub-signal line sub-section X-2a located in the circuit region QD and a second sub-signal line branch X-2b located in the wire region ZD, and the second sub-signal line sub-section X-2a and the second sub-signal line branch X-2b are connected to each other. In one circuit region QD, the gap between the first sub-signal line sub-section X-1a and the second sub-signal line sub-section X-2a is D3; in one wire region ZD, the gap between the first sub-signal line branch X-1a and the second sub-signal line branch X-2b is D4; D4 < D3. In this way, the signal lines extending in the same direction can converge when extending from the circuit region QD to the wire region ZD, thereby facilitating the formation of a larger area of light transmission region between the wire region ZD and the circuit region QD, weakening the diffraction phenomenon of light in the first display area, and improving the optical performance of the photosensitive device in the under-screen photosensitive device scheme.

[0162] Optionally, the arrangement mode of the pixel circuit groups in the first display area can be combined to design the convergence mode of the signal lines extending from the circuit region to the wire region. Figure 29 In the embodiment, the first signal line 1X extending in the first direction x converges in the wire region ZD, and the second signal line 1X extending in the second direction y converges in the wire region ZD.

[0163] Figure 29 In the embodiment, the signal lines extending from the circuit region QD to the wire region ZD converge between two adjacent circuit regions QD to a position close to the center region. Figure 29 As shown in the figure, the circuit region includes a first virtual center line ZX, and the two edges of the circuit region QD on both sides of the first virtual center line ZX are equidistant from the first virtual center line ZX. The extension direction of the first sub-signal line branch X-1b and the extension direction of the second sub-signal line branch X-2b are the same as the extension direction of the first virtual center line ZX, and the first virtual center line ZX penetrates the wire region ZD.

[0164] It should be noted that the extension direction of the first sub-signal line branch X-1b and the extension direction of the second sub-signal line branch X-2b can be understood as the trend of the signal line branch. In some embodiments, the signal line branch located in the wiring area ZD is a straight line. In some embodiments, the signal line branch located in the wiring area ZD can be a curve, and when the signal line branch is a curve, the overall trend of the signal line where the signal line branch is located can be understood as the trend of the signal line branch, and also understood as the extension direction of the signal line branch.

[0165] It should be noted that the following description is referred to when determining the first virtual center line of the circuit area and the edge of the circuit area. In the embodiment of the present application, the circuit area includes at least one pixel circuit group, and the area occupied by the main structure (driving transistor and switch tube) of the pixel circuit in the pixel circuit group is determined as the area occupied by the circuit area, and the area occupied by the circuit area has a certain geometric shape. According to the geometric shape, the first virtual center line ZX is determined, and the distance between the two edges opposite to each other in the second direction and the first virtual center line ZX is equal. Wherein, considering a certain process error, the error of the distance difference between the two edges of the circuit area QD on both sides of the first virtual center line ZX and the first virtual center line ZX is within ±10% when the distance difference is equal.

[0166] Optionally, in an embodiment, Figure 30 Another partial schematic view of a display panel provided by the embodiment of the present application is shown in FIG. 6. As shown in FIG. 6, in the first display area AA1, the first signal line 1X extending in the first direction x and the second signal line 2X extending in the second direction y in the wiring area ZD are arranged in a staggered manner. Figure 30 Figure 29 ​The pixel circuits in a pixel circuit group Z in the second display area AA2 are arranged in a converging manner. The number of the pixel circuits 21 in a pixel circuit group Z in the second display area AA2 is less than that in a pixel circuit group Z in the first display area AA1. One pixel circuit 21 in a pixel circuit group Z in the second display area AA2 is connected to one second constant voltage signal line H2. In the embodiment, the distance D1 between two adjacent first constant voltage signal lines H1 in the first display area AA1 is greater than the distance D2 between two adjacent second constant voltage signal lines H2 in the second display area AA2. The pixel circuits in a pixel circuit group Z in the second display area AA2 cannot drive a pixel unit to emit white light. In the embodiment, the arrangement of the second constant voltage signal lines H2 in the second display area AA2 is relatively dense, which is beneficial to reduce the voltage drop loss of the constant voltage signal lines.

[0167] In another embodiment, Figure 31 Another partial view of a display panel according to an embodiment of the present application is shown in FIG. 4. The display panel shown in FIG. 4 is similar to the display panel shown in FIG. 3, and the same components are denoted by the same reference numerals, and thus will not be described again. Figure 31 The arrangement of the first constant voltage signal lines H1 in the first display area AA1 in the embodiment is the same as that in the embodiment shown in FIG. 3, and the difference lies in the arrangement of the second constant voltage signal lines H2 in the second display area AA2. As shown in FIG. 4, the number of the pixel circuits 21 in a pixel circuit group Z in the second display area AA2 is less than that in a pixel circuit group Z in the first display area AA1. One pixel circuit 21 in a pixel circuit group Z in the second display area AA2 is connected to one second constant voltage signal line H2. In the embodiment, the distance D1 between two adjacent first constant voltage signal lines H1 in the first display area AA1 is greater than the distance D2 between two adjacent second constant voltage signal lines H2 in the second display area AA2. The pixel circuits in a pixel circuit group Z in the second display area AA2 cannot drive a pixel unit to emit white light. In the embodiment, the arrangement of the second constant voltage signal lines H2 in the second display area AA2 is relatively dense, which is beneficial to reduce the voltage drop loss of the constant voltage signal lines. Figure 30 The arrangement of the first constant voltage signal lines H1 in the first display area AA1 in the embodiment is the same as that in the embodiment shown in FIG. 3, and the difference lies in the arrangement of the second constant voltage signal lines H2 in the second display area AA2. As shown in FIG. 4, the number of the pixel circuits 21 in a pixel circuit group Z in the second display area AA2 is less than that in a pixel circuit group Z in the first display area AA1. One pixel circuit 21 in a pixel circuit group Z in the second display area AA2 is connected to one second constant voltage signal line H2. In the embodiment, the distance D1 between two adjacent first constant voltage signal lines H1 in the first display area AA1 is greater than the distance D2 between two adjacent second constant voltage signal lines H2 in the second display area AA2. The pixel circuits in a pixel circuit group Z in the second display area AA2 cannot drive a pixel unit to emit white light. In the embodiment, the arrangement of the second constant voltage signal lines H2 in the second display area AA2 is relatively dense, which is beneficial to reduce the voltage drop loss of the constant voltage signal lines. Figure 31 The arrangement of the first constant voltage signal lines H1 in the first display area AA1 in the embodiment is the same as that in the embodiment shown in FIG. 3, and the difference lies in the arrangement of the second constant voltage signal lines H2 in the second display area AA2. As shown in FIG. 4, the number of the pixel circuits 21 in a pixel circuit group Z in the second display area AA2 is less than that in a pixel circuit group Z in the first display area AA1. One pixel circuit 21 in a pixel circuit group Z in the second display area AA2 is connected to one second constant voltage signal line H2. In the embodiment, the distance D1 between two adjacent first constant voltage signal lines H1 in the first display area AA1 is greater than the distance D2 between two adjacent second constant voltage signal lines H2 in the second display area AA2. The pixel circuits in a pixel circuit group Z in the second display area AA2 cannot drive a pixel unit to emit white light. In the embodiment, the arrangement of the second constant voltage signal lines H2 in the second display area AA2 is relatively dense, which is beneficial to reduce the voltage drop loss of the constant voltage signal lines.

[0168] Figure 31In the embodiment, one pixel circuit group Z in the first display area AA1 includes three pixel circuits 21, and one pixel circuit group Z in the second display area AA2 includes one pixel circuit 21.

[0169] In another alternative embodiment, one pixel circuit group Z in the first display area AA1 includes three pixel circuits 21, and one pixel circuit group Z in the second display area AA2 includes two pixel circuits 21.

[0170] In another alternative embodiment, one pixel circuit group Z in the first display area AA1 includes four pixel circuits 21. Figure 32 Another partial schematic view of a display panel according to an embodiment of the present application is shown in FIG. 6. Figure 32 In the embodiment, only constant voltage signal lines in the display area are shown. As shown in FIG. 2, one pixel circuit group Z in the first display area AA1 includes four pixel circuits 21 arranged in the second direction y, and the four pixel circuits 21 correspond to one first constant voltage signal line H1. One pixel circuit group Z in the second display area AA2 includes two pixel circuits 21, and the two pixel circuits 21 correspond to one second constant voltage signal line H2. That is, in the second display area AA2, the pixel circuits 21 are arranged in columns in the first direction x, and two columns of pixel circuits correspond to one second constant voltage signal line H2. Figure 32

[0171] In another embodiment, one pixel circuit group Z in the first display area AA1 includes four pixel circuits 21; one pixel circuit group Z in the second display area AA2 includes one pixel circuit 21; or one pixel circuit group Z in the second display area AA2 includes three pixel circuits 21. This is not shown in the figures.

[0172] Figure 29 A convergence mode of the traces between two adjacent circuit areas QD is shown in FIG. 6. In another alternative embodiment, the signal lines extended from the circuit area QD into the trace area ZD converge at positions corresponding to the edge region of the circuit area QD in the trace area ZD.

[0173] Figure 33 Another partial schematic view of a display panel according to an embodiment of the present application is shown in FIG. 6. Figure 33 The first sub-signal line X-1 and the second sub-signal line X-2 are shown to have substantially the same extension direction. In one circuit area QD, the gap between the first sub-signal line sub-segment X-1a and the second sub-signal line sub-segment X-2a is D3; in one trace area ZD, the gap between the first sub-signal line branch segment X-1a and the second sub-signal line branch segment X-2b is D4; D4 < D3. As shown in FIG. 6, the first sub-signal line X-1 and the second sub-signal line X-2 are arranged in the same direction in the trace area ZD. Figure 33 ​As shown, the extension directions of the first sub-signal line segment X-1b and the second sub-signal line segment X-2b are both parallel to the first virtual center line ZX and located on the same side of the first virtual center line ZX; the circuit area QD also includes a first virtual boundary Y, which is parallel to the first virtual center line ZX, and the trace area ZD is adjacent to the extension line of the first virtual boundary Y. The understanding of the first virtual center line can be referred to the above. Figure 29 Description of the embodiment. The first virtual boundary can be understood as the edge of the geometric shape formed by the area jointly occupied by the main structures of the pixel circuits in the pixel circuit group.

[0174] In this embodiment, when signal lines extending in the same direction from circuit area QD to trace area ZD, they converge towards the corresponding position at the edge of circuit area QD. This embodiment can be applied in conjunction with the arrangement of pixel circuits in the first display area AA1 to form a larger light-transmitting area between trace area ZD and circuit area QD, reducing the diffraction phenomenon when light passes through the first display area. When applied to under-display photosensitive device solutions, it can improve the optical performance of the photosensitive device.

[0175] for Figure 33 The wiring method of the second constant voltage signal line in the second display area in the embodiment can refer to the above. Figure 30 and Figure 31 The configuration is shown in the embodiment, and no further illustrations are provided here.

[0176] Optional, Figure 34 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 35 for Figure 34 A schematic diagram of the cross-section at the position of the mid-tangent line D-D'. (See diagram below.) Figure 34 As shown, the signal lines include a third sub-signal line X-3 and a fourth sub-signal line X-4 extending in the same direction. "Extending in the same direction" means that the two signal lines have roughly the same path. The third sub-signal line X-3 includes a sub-segment X-3a located in circuit area QD and a branch segment X-3b located in trace area ZD. Sub-segment X-3a and branch segment X-3b are interconnected. Figure 34 The diagram illustrates two third sub-signal line segments X-3a located in the two circuit regions QD. The fourth sub-signal line X-4 includes the fourth sub-signal line segment X-4a located in the circuit region QD and the fourth sub-signal line branch segment X-4b located in the routing region ZD. The fourth sub-signal line segment X-4a and the fourth sub-signal line branch segment X-4b are interconnected. Figure 34The diagram illustrates two fourth sub-signal line segments X-4a, each of which is located in the same circuit region QD as a third sub-signal line segment X-3a; it also illustrates a fourth sub-signal line branch X-4b located in the same routing region ZD as the third sub-signal line branch X-3b. For example... Figure 35 As shown, within the trace area ZD: in the direction e perpendicular to the plane of the substrate 10, the third sub-signal line segment X-3b and the fourth sub-signal line segment X-4b at least partially overlap. This configuration reduces the width occupied by the trace area in the width direction of the signal line segments, thus reducing the area occupied by the trace area and facilitating an increase in the area of ​​the light-transmitting region within the first display area. Simultaneously, the presence of at least partial overlap between two signal line segments within the trace area also reduces the gap between adjacent signal lines within the trace area, thereby reducing diffraction that occurs when light penetrates the first display panel.

[0177] Optional, Figure 36 A partial schematic diagram of another display panel provided in an embodiment of the present invention, as shown below. Figure 36 As shown, within the first display area AA1, the display panel also includes a third connecting part 3J. Two adjacent first connecting parts 1J in the second direction y are electrically connected through the third connecting part 3J, which is located in the trace area ZD. The arrangement of the third connecting part 3J enables the first connecting parts 1J in the multiple circuit areas QD arranged in the second direction y to be interconnected. Overall, the first connecting parts 1J and the third connecting part 3J constitute a horizontally connected trace extending in the second direction y. Thus, within the first display area AA1, the first constant voltage signal line H1, the first connecting part 1J, and the third connecting part 3J can form a grid-like trace, thereby reducing the voltage drop of the constant voltage signal transmitted on the first constant voltage signal line H1.

[0178] In one implementation, Figure 37 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 37Part of the first display area AA1 and part of the second display area AA2 are shown in the figure. A first auxiliary constant-voltage signal line H1' is arranged in the first display area AA1, the first auxiliary constant-voltage signal line H1' extends in the second direction y, the extension direction of the first auxiliary constant-voltage signal line H1' and the extension direction of the first constant-voltage signal line H1 cross each other, one first auxiliary constant-voltage signal line H1' crosses and is electrically connected with a plurality of first constant-voltage signal lines H1, and the first auxiliary constant-voltage signal line H1' transmits the same voltage signal as the first constant-voltage signal line H1. Then, in the first display area AA1, the first auxiliary constant-voltage signal line H1' and the first constant-voltage signal line H1 cross each other to form a grid-shaped trace. A second auxiliary constant-voltage signal line H2' is arranged in the second display area AA2, the second auxiliary constant-voltage signal line H2' extends in the second direction y, the extension direction of the second auxiliary constant-voltage signal line H2' and the extension direction of the second constant-voltage signal line H2 cross each other, then one second auxiliary constant-voltage signal line H2' crosses and is electrically connected with a plurality of second constant-voltage signal lines H2, and the second auxiliary constant-voltage signal line H2' transmits the same voltage signal as the second constant-voltage signal line H2. In the second display area AA2, the second auxiliary constant-voltage signal line H2' and the second constant-voltage signal line H2 cross each other to form a grid-shaped trace. In this embodiment, the grid-shaped trace is used to transmit the constant-voltage signal, which can reduce the voltage drop of the constant-voltage signal and reduce power consumption.

[0179] In some embodiments, Figure 37 In the embodiment, the constant-voltage signal line is a reset signal line.

[0180] In some embodiments, Figure 37 In the embodiment, the constant-voltage signal line is a power supply signal line.

[0181] In an alternative embodiment, the first auxiliary constant-voltage signal line H1' includes alternately connected first connection portions 1J and third connection portions 3J.

[0182] In an embodiment, the third connection portion 3J and the first connection portion 1J are located in the same layer. In another embodiment, the third connection portion 3J and the first connection portion 1J are located in different layers.

[0183] In combination with the above Figure 19 In the embodiment, the third connection portion 3J is located in any one of the semiconductor layer W, the first metal layer M1, the second metal layer M2, and the third metal layer M3.

[0184] In combination with the above Figure 20 In the embodiment, the third connection portion 3J is located in any one of the semiconductor layer W, the first metal layer M1, and the second metal layer M2.

[0185] In an embodiment, Figure 38 Another partial schematic view of a display panel provided by an embodiment of the present application is shown in FIG. 7.Figure 38 As shown, the first display area AA1 includes a light-transmitting area AT and a non-light-transmitting area AF. The virtual boundary BY between the light-transmitting area AT and the non-light-transmitting area AF is a curve. That is, the virtual boundary of the light-transmitting area AT is a curve. The non-light-transmitting area AF includes the circuit area QD, the wiring area ZD, and the area where the light-emitting device 31 is located; the non-light-transmitting area AF at least partially surrounds the light-transmitting area AT. The non-light-transmitting structures in the non-light-transmitting area AF include at least the light-emitting device 31, the pixel circuit in the circuit area QD, and the signal lines in the wiring area ZD. In this embodiment of the invention, setting the virtual boundary of the light-transmitting area AT as a curve is beneficial to improving the diffraction of light when it penetrates the first display area. When applied to an under-display photosensitive device solution, it can improve the optical performance of the photosensitive device. When the photosensitive device is a camera, it can reduce the impact of diffraction on the image captured by the camera, which is beneficial to improving the clarity of the captured image and improving the image quality. In some embodiments, the display panel includes a light-shielding layer located above a substrate, wherein the light-shielding layer has an opening, and optionally, the material used to make the light-shielding layer includes black color resist or light-shielding (opaque) metal. In a direction perpendicular to the plane of the substrate, the area formed by the light-shielding layer and other opaque structures in the display panel, and the area formed by their overlap, is an opaque area; the area formed by the overlap of the opening of the light-shielding layer and the light-transmitting areas in other film layers of the display panel is a light-transmitting area.

[0186] In some embodiments, the orthographic projection of the opening of the light-shielding layer onto the substrate substantially coincides with the light-transmitting area, that is, the shape of the opening of the light-shielding layer is approximately the same as the shape of the light-transmitting area.

[0187] In one embodiment, Figure 39 for Figure 38 A schematic diagram of the cross-section at the position of the tangent line E-E', as shown below. Figure 39 As shown, the light-shielding layer 50 and the first electrode 31a of the light-emitting device 31 are located on the same layer. The area where the opening V of the light-shielding layer 50 is located is the light-transmitting region AT. The projection shape formed by the orthographic projection of the edge of the opening V of the light-shielding layer 50 onto the substrate 10 in the direction e perpendicular to the plane of the substrate 10, and the shape of the virtual boundary BY of the light-transmitting region AT, are also shown. This embodiment designs the shape of the opening of the light-shielding layer, making the edge of the opening curved, so that the virtual boundary of the light-transmitting region is curved. Since the light-shielding layer 50 and the first electrode 31a are located on the same layer, they can be fabricated in the same process, simplifying the manufacturing process.

[0188] In another embodiment, the light-shielding layer 50 is located on the side of the second electrode 31c away from the substrate 10. In this embodiment, the light-shielding layer 50 further includes a first opening that exposes the light-emitting device 31 in a direction perpendicular to the plane of the substrate, so as to ensure that the light-emitting device 31 emits light.

[0189] In another embodiment, the light-shielding layer 50 is located on the side of the pixel circuit 21 near the substrate 10. In this embodiment, the light-shielding layer 50 is fabricated on the substrate 10, and the array layer 20 and the display layer 30 are fabricated sequentially after the process of the light-shielding layer 50. The setting of the light-shielding layer 50 does not affect the process of the array layer and the display layer in the display panel.

[0190] In another embodiment, the light-shielding layer 50 is located between the array layer 20 and the display layer 30. In this embodiment, the light-shielding layer 50 further includes a second opening for accommodating a via connecting the pixel circuit 21 to the first electrode 31a of the light-emitting device 31.

[0191] Figure 38 The shape of the light-transmitting area AT is illustrated as a circle. In this embodiment of the invention, the shape of the light-transmitting area can also be elliptical or other irregular shapes. Generally, shapes that can be mathematically defined and named, such as circles, triangles, and opposite sides, are considered regular shapes. Correspondingly, shapes that cannot be defined and named are considered irregular shapes. That is to say, irregular shapes cannot be named according to mathematical definitions. Figure 40 A partial schematic diagram of another display panel provided in an embodiment of the present invention, as shown below. Figure 40 As shown, the shape of the light-transmitting area AT is irregular, and the virtual boundary BY between the light-transmitting area AT and the non-light-transmitting area AF is a curve. That is, the virtual boundary of the light-transmitting area AT is a curve.

[0192] In one embodiment, Figure 41 This is a partial schematic diagram of the first display area of ​​another display panel provided in an embodiment of the present invention, as shown below. Figure 41 As shown, the signal lines located at least at the edge of the trace area ZD are curved. By designing the shape of the signal lines within the trace area ZD, straight edges can be avoided, thus reducing the degree of diffraction when light penetrates the first display area AA1. Figure 41 The irregularly shaped area resembling a cloud, enclosed by the four circuit regions QD and the four wiring regions ZD, is the light-transmitting region AT. In the non-light-transmitting region AF, the orthographic projection of non-light-transmitting structures such as the first electrode of the light-emitting device 31, components in the pixel circuit (including transistors, capacitor plates, and connecting lines between transistors), the connecting portions located at the edges of the pixel circuit group mentioned in the above embodiments, and signal lines located within the wiring regions onto the substrate forms the shape of the non-light-transmitting region AF. The edge of this orthographic projection shape is the virtual boundary BY between the non-light-transmitting region AF and the light-transmitting region AT.

[0193] exist Figure 41In this embodiment, by designing the shape of the traces in the trace area ZD and the circuit area QD, the virtual boundary of the light-transmitting area AT is made to be a curve, which can form a larger area of ​​light-transmitting area AT in the area enclosed by the trace area ZD and the circuit area QD, thereby improving the light transmittance of the first display area AA1.

[0194] In another embodiment, Figure 42 for Figure 41 A schematic diagram of a cross-section at the mid-tangent F-F'. (See diagram below.) Figure 42 As shown, the display panel includes a light-shielding layer 50, which includes light-shielding units 50Y. The orthographic projection of the light-shielding unit 50Y onto the substrate 10 at least covers the orthographic projection of the wiring area ZD onto the substrate 10. That is, in the direction e perpendicular to the plane of the substrate 10, the light-shielding unit 50Y overlaps with the wiring in the wiring area ZD. By blocking the gaps between signal lines in the wiring area ZD through the light-shielding unit 50Y, diffraction caused when light passes through the wiring area ZD can be reduced.

[0195] Figure 42 The illustration only shows the second signal line 2X in the routing area ZD located on the same layer, and is not intended to limit the invention.

[0196] In another embodiment, a portion of the line segment located at the edge of the circuit region QD is designed. The line type of this segment at the edge of the circuit region QD is set to a curve. In some embodiments, the line segment located at the edge of the circuit region QD is a portion of a signal line extending from the circuit region QD to the trace region ZD, for example... Figure 34 The signal line within region Q1 shown in the embodiment is a segment of the second scan line S2. In one embodiment, Figure 34 In the embodiment, the line segments within the illustrated area Q1 are set as curves. When some curved line segments together with other non-transparent structures form the virtual boundary of the light-transmitting area, the diffraction of light penetrating the first display area can be reduced.

[0197] In this embodiment of the invention, the display panel includes a light-emitting device group, which comprises n light-emitting devices. That is, the number of light-emitting devices in the light-emitting device group is the same as the number of pixel circuits in a pixel circuit group within the first display area. The n light-emitting devices in the light-emitting device group can cooperate to mix light and emit white light.

[0198] In one embodiment, within the first display area, if one pixel circuit in a pixel circuit group is electrically connected to one light-emitting device, then one pixel circuit group corresponds to one light-emitting device group.

[0199] In another embodiment, within the first display area, if one pixel circuit in a pixel circuit group is electrically connected to two or more light-emitting devices, then one pixel circuit group corresponds to two or more light-emitting device groups.

[0200] In some embodiments, one light emitting device group includes one first light emitting device, one second light emitting device and one third light emitting device, which are different in light emitting color, and the total number of light emitting devices is three.

[0201] As shown in Figure 43 , Figure 43 Fig. 6 is a partial schematic view of a first display area of another display panel according to an embodiment of the present application, one pixel circuit group Z includes three pixel circuits 21, and in one light emitting device group 31Z: the first light emitting device 1-31, the second light emitting device 2-31 and the third light emitting device 3-31 are arranged in a "pin" shape. And the pixel circuit group Z and the light emitting device group 31Z are one-to-one corresponding, one pixel circuit 21 in one pixel circuit group Z is connected to one light emitting device. The second light emitting control transistor in the pixel circuit is electrically connected to the first electrode of the light emitting device, and in some embodiments, the distance between the first electrode of the light emitting device and the second light emitting control transistor in the pixel circuit connected thereto is far, and the second light emitting control transistor is connected to the corresponding second light emitting control transistor through a wire made in the same layer as the first electrode.

[0202] In an embodiment, Figure 44 Fig. 7 is a partial schematic view of another display panel according to an embodiment of the present application, and Figure 44 Fig. 7 schematically shows the arrangement of light emitting devices in the first display area AA1 and the arrangement of light emitting devices in the second display area AA2. In the second display area AA2: the first light emitting device 1-31, the second light emitting device 2-31 and the third light emitting device 3-31 are alternately arranged in the first direction x to form light emitting device columns L, and a plurality of light emitting device columns L are arranged in the second direction y. In the second display area AA2, the three light emitting devices in the light emitting device group 31Z-1 and the three light emitting devices in the light emitting device group 31Z-2 are arranged in a "pin" shape, and the adjacent light emitting device group 31Z-1 and the light emitting device group 31Z-2 in the first direction x form a repeating unit.

[0203] In Figure 43 the schematic light emitting device group, the areas of the first light emitting device 1-31, the second light emitting device 2-31 and the third light emitting device 3-31 are approximately equal. In an embodiment, the first light emitting device 1-31 is a red light emitting device, the second light emitting device 2-31 is a blue light emitting device, and the third light emitting device 3-31 is a green light emitting device.

[0204] In another embodiment, Figure 45 Fig. 8 is a partial schematic view of a first display area of another display panel according to an embodiment of the present application, and Figure 45As shown in FIG. 1, in the first display area, one pixel circuit group Z corresponds to two light emitting device groups 31Z, that is, one pixel circuit 21 corresponds to two light emitting devices with the same color of light respectively belonging to the two light emitting device groups 31Z. As shown in FIG. 1, the two light emitting device groups 31Za and 31Zb correspond to the same pixel circuit group Z. Figure 45 As shown in FIG. 1, the light emitting device group 31Za and the light emitting device group 31Zb correspond to the same pixel circuit group Z.

[0205] For the embodiment that one pixel circuit group corresponds to three or more light emitting device groups, it can be understood by referring to Figure 45 and will not be described here again.

[0206] In another embodiment, Figure 46 A partial schematic view of a first display area of another display panel provided by an embodiment of the present application is shown in FIG. 2. Figure 46 As shown in FIG. 2, three light emitting devices in one light emitting device group 31Z are arranged dispersedly. The light emitting devices are distributed uniformly in the first display area AA1. Optionally, the traces electrically connecting the light emitting devices and the pixel circuit 21 are arranged in curves to reduce the diffraction when the light penetrates the first display area AA1.

[0207] In another embodiment, Figure 47 A partial schematic view of a first display area of another display panel provided by an embodiment of the present application is shown in FIG. 2. Figure 47 As shown in FIG. 2, one pixel circuit group Z includes three pixel circuits 21, and in one light emitting device group 31Z: the first light emitting device 1-31, the second light emitting device 2-31 and the third light emitting device 3-31 are arranged in a "π" shape. And, Figure 47 As shown in FIG. 2, the pixel circuit group Z corresponds to the light emitting device group 31Z one by one, and one pixel circuit 21 corresponds to one light emitting device.

[0208] Figure 48 A partial schematic view of another display panel provided by an embodiment of the present application is shown in FIG. 3. Figure 48The arrangement of the light emitting devices in the first display area AA1 and the arrangement of the light emitting devices in the second display area AA2 are shown in FIG. 1. In the second display area AA2, the first light emitting devices 1-31 and the second light emitting devices 2-31 are arranged in the first direction x to form first light emitting device columns L1, and the third light emitting devices 3-31 are arranged in the first direction x to form second light emitting device columns L2, and the first light emitting device columns L1 and the second light emitting device columns L2 are arranged in the second direction y alternately, and for adjacent first light emitting device columns L1 and second light emitting device columns L2, one third light emitting device 3-31 corresponds to one first light emitting device 1-31 and one second light emitting device 2-31. The length of the third light emitting device 3-31 in the first direction x is greater than the length of the first light emitting device 1-31 in the first direction x, and the length of the third light emitting device 3-31 in the first direction x is greater than the length of the second light emitting device 2-31 in the first direction x. In an embodiment, the length of the third light emitting device 3-31 in the first direction x is approximately the sum of the length of the first light emitting device 1-31 in the first direction x and the length of the second light emitting device 2-31 in the first direction x. In an embodiment, the area of the first light emitting device 1-31 is approximately the same as the area of the second light emitting device 2-31, and the area of the third light emitting device 3-31 is approximately twice the area of the first light emitting device 1-31.

[0209] In another embodiment, Figure 49 A partial schematic view of another display panel provided by an embodiment of the present application is shown in FIG. 2. Figure 49 The arrangement of the light emitting devices in the first display area AA1 and the arrangement of the light emitting devices in the second display area AA2 are shown in FIG. 1. In the second display area AA2, the first light emitting devices 1-31 and the second light emitting devices 2-31 are arranged in the first direction x to form first light emitting device columns L1, and the third light emitting devices 3-31 are arranged in the first direction x to form second light emitting device columns L2, and the first light emitting device columns L1 and the second light emitting device columns L2 are arranged in the second direction y alternately, and for adjacent first light emitting device columns L1 and second light emitting device columns L2, one third light emitting device 3-31 corresponds to one first light emitting device 1-31 and one second light emitting device 2-31. The length of the third light emitting device 3-31 in the first direction x is greater than the length of the first light emitting device 1-31 in the first direction x, and the length of the third light emitting device 3-31 in the first direction x is greater than the length of the second light emitting device 2-31 in the first direction x. In an embodiment, the length of the third light emitting device 3-31 in the first direction x is approximately the sum of the length of the first light emitting device 1-31 in the first direction x and the length of the second light emitting device 2-31 in the first direction x. In an embodiment, the area of the first light emitting device 1-31 is approximately the same as the area of the second light emitting device 2-31, and the area of the third light emitting device 3-31 is approximately twice the area of the first light emitting device 1-31.

[0210] In some embodiments, the light emitting device group includes one first light emitting device, one second light emitting device and two third light emitting devices, which are different in light emitting color, and there are four light emitting devices in total.

[0211] In an embodiment, Figure 50 A partial schematic view of another display panel provided by an embodiment of the present application is shown in FIG. 2. Figure 50As shown, a pixel circuit group Z includes four pixel circuits 21 within a light-emitting device group 31Z: the four light-emitting devices are located at the four vertices of the first virtual quadrilateral 70, with two third light-emitting devices 3-31 located at one opposite corner of the first virtual quadrilateral 70, and the first light-emitting device 1-31 and the second light-emitting device 2-31 located at the other opposite corner. Specifically, the third light-emitting device 3-31 is a green light-emitting device, and one of the first light-emitting devices 1-31 and the second light-emitting device 2-31 is a red light-emitting device and the other is a blue light-emitting device. The location of a light-emitting device at one of the vertices of the first virtual quadrilateral 70 is understood as the geometric center of the light-emitting device coinciding with the vertices of the first virtual quadrilateral 70. Each light-emitting device includes a light-emitting layer, and the geometric center of the light-emitting layer is the geometric center of the light-emitting device.

[0212] Optionally, in one embodiment, within the light-emitting device group 31Z, the line connecting the centers of the two third light-emitting devices 3-31 is approximately parallel to the first direction x, and the line connecting the centers of the first light-emitting device 1-31 and the centers of the second light-emitting device 2-31 is approximately parallel to the second direction y.

[0213] In one embodiment, the area of ​​the second light-emitting device 2-31 is larger than that of the first light-emitting device 1-31, and the area of ​​the second light-emitting device 2-31 is larger than that of the third light-emitting device 3-31.

[0214] Figure 51 A partial schematic diagram of another display panel provided in an embodiment of the present invention, as shown below. Figure 51 The diagram illustrates the arrangement of light-emitting devices in the first display area AA1 and the second display area AA2. Specifically, in the second display area AA2: first light-emitting devices 1-31 and second light-emitting devices 2-31 are arranged alternately in the first direction x to form a first light-emitting device column L1, and multiple third light-emitting devices 3-31 are arranged in the first direction x to form a second light-emitting device column L2. In the second direction y, the first light-emitting device column L1 and the second light-emitting device column L2 are alternately arranged. Optionally, Figure 51 In this embodiment, the third light-emitting device 3-31 is a green light-emitting device, which improves the uniformity of the green light-emitting device arrangement. This enhances the overall display effect when using sub-pixel rendering.

[0215] In another embodiment, Figure 52 This is a partial schematic diagram of the first display area of ​​another display panel provided in an embodiment of the present invention, as shown below. Figure 52As shown, a pixel circuit group Z includes four pixel circuits 21 within a light-emitting device group 31Z: a first light-emitting device 1-31 and a second light-emitting device 2-31 are arranged in a first device row 31H1 in the second direction y, and two third light-emitting devices 3-31 are arranged in a second device row 31H2 in the second direction. The second direction y intersects the first direction x, wherein the first device row 31H1 and the second device row 31H2 are staggered in the first direction x; in the second direction y, the stagger distance between one of the third light-emitting devices 3-31 and the first light-emitting device 1-31 is d1, the distance between the first light-emitting device 1-31 and the second light-emitting device 2-31 is d2, d1 is less than d2, and the stagger distance between the third light-emitting device 3-31 and the second light-emitting device 2-31 is d3, d3 is less than d2. It should be noted that, in understanding this embodiment, the stagger distance between two light-emitting devices is calculated as the distance between identical structures in the two light-emitting devices in the second direction y. Optionally, the misalignment distance between the two light-emitting devices can be calculated using the distance between their geometric centers in the second direction y. In this embodiment, the arrangement of the light-emitting devices within the second display area AA2 can be similar to... Figure 51 The arrangement of the light-emitting devices in the second display area AA2 is the same in the embodiment, and will not be shown in the attached figure here.

[0216] Optionally, in one embodiment, the line connecting the center of the first light-emitting device 1-31 and the center of the second light-emitting device 2-31 in the first device row 31H1 is approximately parallel to the second direction y; the line connecting the centers of the two third light-emitting devices 3-31 in the second device row 31H2 is approximately parallel to the second direction y.

[0217] In the above embodiments, the shape of the light-emitting device is illustrated as a rectangle. It should be noted that the present invention does not limit the specific shape of the light-emitting device. In some embodiments, the shape of the light-emitting device can be a circle, a rounded rectangle, an ellipse, or a hexagon, etc.

[0218] In another embodiment, the first display area AA1 includes a first sub-region and a second sub-region, and the pixel circuit driving the light-emitting devices in the second sub-region is located in the first sub-region. The transmittance of the second sub-region is greater than that of the first sub-region.

[0219] Specifically, Figure 53 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 53The first sub-region A1G and the second sub-region A1T in the first display region AA1 are shown in FIG. 1. The light emitting device group 31Z is arranged in the second sub-region A1T, and the pixel circuit driving the light emitting device group 31Z in the second sub-region A1T is located in the first sub-region A1G. That is, no pixel circuit is arranged in the second sub-region A1T, so that the light transmittance of the second sub-region A1T can be greatly improved. When the screen under light sensing device scheme is applied, the light sensing device is arranged below the second sub-region A1T, which can meet the higher requirement of the light transmittance of the display panel in the screen under light sensing device scheme.

[0220] In an optional embodiment, the arrangement density of the light emitting device in the second sub-region A1T is less than that in the first sub-region A1G.

[0221] In some embodiments, the first constant voltage signal line and the second constant voltage signal line are connected at the junction of the first display region and the second display region.

[0222] Optionally, in an embodiment, Figure 54 Another partial schematic view of a display panel according to an embodiment of the present application is shown in FIG. 2. Figure 54 As shown in FIG. 2, the first constant voltage signal line H1 and the second constant voltage signal line H2 are electrically connected by the fourth connection part 4J at the junction of the first display region AA1 and the second display region AA2. Figure 54 The line segment at the position of the region Q2 shown in FIG. 2 is the fourth connection part 4J.

[0223] Optionally, in another embodiment, Figure 55 Another partial schematic view of a display panel according to an embodiment of the present application is shown in FIG. 3. Figure 55 As shown in FIG. 3, the first constant voltage signal line H1 and the second constant voltage signal line H2 are electrically connected by the fourth connection part 4J at the junction of the first display region AA1 and the second display region AA2. Figure 55 The line segment at the position of the region Q3 shown in FIG. 3 is the fourth connection part 4J.

[0224] In some embodiments, the first display region AA1 accounts for a small proportion of the entire display region, and the second display region AA2 is arranged around at least part of the first display region AA1. The arrangement of the first display region AA1 makes the second display region AA2 not in a regular rectangular shape (as shown in FIG. 1 and FIG. 2). Figure 1 and Figure 2 As can be seen from FIG. 1 and FIG. 2, the second display region AA2 has a notch, and the shape of the notch is the same as that of the first display region AA1. Thus, the second display region AA2 includes second constant voltage signal lines with different lengths in the first direction x. Figure 54The diagram illustrates the second constant voltage signal line H2-1 and the second constant voltage signal line H2-2. In this embodiment of the invention, the first constant voltage signal line H1 and the second constant voltage signal line H2-2 are connected via a fourth connecting portion. This not only allows the voltage signal to be transmitted to the first constant voltage signal line H1 within the first display area AA1 via the second constant voltage signal line H2-2, thereby providing a voltage signal to the pixel circuits within the first display area AA1, but also reduces the voltage drop difference between the second constant voltage signal line H2-1 and the second constant voltage signal line H2-2, which is beneficial for the uniformity of the display panel.

[0225] In one embodiment, the fourth connection portion is located in the same metal layer as the first constant voltage signal line H1 and the second constant voltage signal line H2. For example... Figure 54 As shown, one end of the fourth connection 4J is connected to the first constant voltage signal line H1, and the other end is connected to the second constant voltage signal line H2. The fourth connection 4J does not intersect with signal lines (such as data lines) located on the same metal layer as the constant voltage signal lines in its extension direction. Therefore, the fourth connection located at the boundary between the two areas is situated on the same metal layer as the constant voltage signal lines. This solution requires designing the wiring method for the second constant voltage signal line H2 within the second display area AA2 to facilitate the electrical connection between the first constant voltage signal line H1 and the second constant voltage signal line H2.

[0226] In another embodiment, the fourth connection 4J is located in a different metal layer from at least one of the first constant voltage signal line H1 and the second constant voltage signal line H2.

[0227] In some implementations, such as Figure 55 As shown, in the first direction of the extension of the constant voltage signal line, when the first constant voltage signal line H1 extends from the first display area AA1 to the second display area AA2, there is a gap d4 between the first constant voltage signal line H1 and the second constant voltage signal line H2 that is closer to it. The gap d4 is larger when perpendicular to the extension direction of the constant voltage signal line, and the fourth connecting part 4J may cross and short-circuit with other signal lines located on the same layer as the constant voltage signal line. By setting the fourth connecting part to be located on a different metal layer from at least one of the first constant voltage signal line H1 and the second constant voltage signal line H2, it is possible to avoid short-circuiting between lines transmitting different signals, and at the same time, it is also possible to achieve interconnection between the constant voltage signal lines in the first display area and the constant voltage signal lines in the second display area.

[0228] In another embodiment, Figure 56 A partial schematic diagram of another display panel provided in an embodiment of the present invention, as shown below. Figure 56As shown, at least a portion of the first constant voltage signal line H1 terminates near the second display area AA2. That is, the end of the first constant voltage signal line H1 near the second display area AA2 is not connected to the second constant voltage signal line H2. In this embodiment, the first display area AA1 also includes a fifth connecting portion J5, which intersects the extension direction of the first constant voltage signal line H1. Specifically, the fifth connecting portion J5 extends approximately along the second direction y. The fifth connecting portion J5 is electrically connected to the first constant voltage signal line H1, and extends from within the first display area AA1 to within the second display area AA2, where it is electrically connected to the second constant voltage signal line H2. In conjunction with the above... Figure 55 In the embodiment, the first connecting portion 1J located in the circuit area QD, the third connecting portion J4 located in the trace area ZD, and the fifth connecting portion J5 extending from the first display area AA1 to the second display area AA2 together constitute the first auxiliary constant voltage signal line H1'. Within the first display area AA1, the first auxiliary constant voltage signal line H1' is electrically connected to the first constant voltage signal line H1, and they intersect to form a grid pattern. In this embodiment, a constant voltage signal can be transmitted to the first constant voltage signal line H1 through the first auxiliary constant voltage signal line H1'. Furthermore, it can reduce the voltage drop on the constant voltage signal line within the first display area AA1.

[0229] In one embodiment, the portion of the fifth connecting part J5 located within the first display area AA1 is on the same layer as the first connecting part 1J.

[0230] In another embodiment, Figure 57 A partial schematic diagram of another display panel provided in an embodiment of the present invention, as shown below. Figure 57 As shown, the first constant voltage signal line H1 terminates near the second display area AA2. That is, the first constant voltage signal line H1 and the second constant voltage signal line H2 are not connected at the boundary between the first display area AA1 and the second display area AA2. Optionally, the first constant voltage signal line H1 extends from the first display area AA1 to the non-display area BA in its direction of travel, and a portion of the second constant voltage signal line H2 extends from the second display area AA2 to the non-display area BA in its direction of travel. The first constant voltage signal line H1 is electrically connected to the second constant voltage signal line H2 via a lead XX within the non-display area BA.

[0231] This invention also provides a display device. Figure 58 This is a schematic diagram of a display device provided in an embodiment of the present invention. Figure 59 for Figure 58 A schematic diagram of the cross-section at the position of the tangent line G-G'. (See diagram below.) Figure 58As shown in FIG. 1, the display device includes the display panel 100 provided by any of the embodiments of the present application. The arrangement of the sub-pixels in the display panel 100 has been described in the above embodiments, and will not be repeated here. The display device in the embodiments of the present application can be any device having a display function, such as a mobile phone, a tablet computer, a notebook computer, an e-paper, a television, a smart wearable product, etc.

[0232] As shown in FIG. 1, the display device includes the display panel 100 provided by any of the embodiments of the present application. The arrangement of the sub-pixels in the display panel 100 has been described in the above embodiments, and will not be repeated here. The display device in the embodiments of the present application can be any device having a display function, such as a mobile phone, a tablet computer, a notebook computer, an e-paper, a television, a smart wearable product, etc. Figure 59 As shown in FIG. 1, the display device includes the display panel 100 provided by any of the embodiments of the present application. The arrangement of the sub-pixels in the display panel 100 has been described in the above embodiments, and will not be repeated here. The display device in the embodiments of the present application can be any device having a display function, such as a mobile phone, a tablet computer, a notebook computer, an e-paper, a television, a smart wearable product, etc.

[0233] The above only describes the preferred embodiments of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0234] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the above embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized by, The display panel comprises a display area, the display area comprising a pixel circuit, a light emitting device and a signal line; the pixel circuit is electrically connected with the light emitting device, and the signal line is electrically connected with the pixel circuit; the signal line comprises a signal transmission line extending in a first direction; the display area comprises a first display area and a second display area; The display area comprises a plurality of pixel circuit groups, each pixel circuit group comprising n pixel circuits arranged in a second direction, n being a positive integer greater than or equal to 2, and the second direction intersecting the first direction; In the first display area, the display panel comprises a first connecting portion extending in the second direction, and the pixel circuits belonging to the same pixel circuit group are electrically connected with the signal transmission line through the first connecting portion; The pixel circuit comprises a driving transistor, a first reset transistor M5 and a second reset transistor M7; a first electrode of the first reset transistor is electrically connected with a control terminal of the driving transistor; a first electrode of the second reset transistor is electrically connected with a first electrode of the light emitting device; The first connecting portion comprises a first sub-connecting portion and a second sub-connecting portion; A second electrode of the first reset transistor belonging to the same pixel circuit group is electrically connected with the signal transmission line through the first sub-connecting portion; and a second electrode of the second reset transistor belonging to the same pixel circuit group is electrically connected with the signal transmission line through the second sub-connecting portion.

2. The display panel of claim 1, wherein The pixel circuit further comprises a data writing transistor, a first light emitting control transistor and a second light emitting control transistor; The signal line further comprises a power signal line sub-section, a data line sub-section, a first scan line sub-section, a second scan line sub-section, a third scan line sub-section and a light emitting control line sub-section; A first electrode of the data writing transistor is electrically connected with the data line sub-section, a second electrode of the data writing transistor is electrically connected with a first electrode of the driving transistor, and control terminals of the data writing transistors belonging to the same pixel circuit group are electrically connected with the same first scan line sub-section; A first electrode of the first light emitting control transistor is electrically connected with the power signal line sub-section, a second electrode of the first light emitting control transistor is electrically connected with the first electrode of the driving transistor, a first electrode of the second light emitting control transistor is electrically connected with a second electrode of the driving transistor, and a second electrode of the second light emitting control transistor is electrically connected with the first electrode of the light emitting device; Control terminals of the first light emitting control transistor and the second light emitting control transistor belonging to the same pixel circuit group are electrically connected with the same light emitting control line sub-section; Control terminals of the first reset transistors belonging to the same pixel circuit group are electrically connected with the second scan line sub-section, and control terminals of the second reset transistors belonging to the same pixel circuit group are electrically connected with the third scan line sub-section.

3. A display panel, characterized by, The display panel comprises a display area, the display area comprising a pixel circuit, a light emitting device and a signal line; the pixel circuit is electrically connected with the light emitting device, and the signal line is electrically connected with the pixel circuit; the signal line comprises a signal transmission line extending in a first direction; the display area comprises a first display area and a second display area; The display area comprises a plurality of pixel circuit groups, each pixel circuit group comprising n pixel circuits arranged in a second direction, n being a positive integer greater than or equal to 2, and the second direction intersecting the first direction; In the first display area, the display panel comprises a first connecting portion extending in the second direction, and the pixel circuits belonging to the same pixel circuit group are electrically connected with the signal transmission line through the first connecting portion; The pixel circuit comprises a driving transistor, a first light emitting control transistor M1 and a second light emitting control transistor M6; The first electrode of the first light emitting control transistor is electrically connected with the signal transmission line, and the second electrode of the first light emitting control transistor is electrically connected with the first electrode of the driving transistor; the first electrode of the second light emitting control transistor is electrically connected with the second electrode of the driving transistor, and the second electrode of the second light emitting control transistor is electrically connected with the first electrode of the light emitting device; The first connecting portion comprises a third sub-connecting portion; The first electrodes of the first light emitting control transistors belonging to the same pixel circuit group are electrically connected with the signal transmission line through the third sub-connecting portion.

4. The display panel of claim 3, wherein The pixel circuit further comprises a data writing transistor, a first reset transistor and a second reset transistor; The signal line further comprises a reset signal line sub-segment, a data line sub-segment, a first scan line sub-segment, a second scan line sub-segment, a third scan line sub-segment and a light emitting control line sub-segment; The first electrode of the data writing transistor is electrically connected with the data line sub-segment, the second electrode of the data writing transistor is electrically connected with the first electrode of the driving transistor, the control terminals of the data writing transistors belonging to the same pixel circuit group are electrically connected with the same first scan line sub-segment; the first electrode of the first reset transistor is electrically connected with the control terminal of the driving transistor, the first electrode of the second reset transistor is electrically connected with the first electrode of the light emitting device; the second electrode of the first reset transistor and the second electrode of the second reset transistor are both electrically connected with the reset signal line sub-segment; The control terminals of the first reset transistors belonging to the same pixel circuit group are electrically connected with the second scan line sub-segment; the control terminals of the second reset transistors belonging to the same pixel circuit group are electrically connected with the third scan line sub-segment; the control terminals of the first light emitting control transistors and the control terminals of the second light emitting control transistors belonging to the same pixel circuit group are both electrically connected with the same light emitting control line sub-segment.

5. The display panel of claim 1 or 3, wherein The signal transmission line comprises a first signal line located in the first display area and a second signal line located in the second display area; A distance between two adjacent first signal lines in the first display area is D1, and a distance between two adjacent second signal lines in the second display area is D2; wherein D1≥D2.

6. The display panel of claim 1 or 3, wherein, the first display area comprises a circuit area and a wire area, and the circuit area comprises at least one pixel circuit group; the signal lines comprise first and second sub-signal lines having the same extension direction, the first sub-signal line comprises a first sub-signal line segment in the circuit area and a first sub-signal line branch in the wire area, and the first sub-signal line segment and the first sub-signal line branch are connected to each other; the second sub-signal line comprises a second sub-signal line segment in the circuit area and a second sub-signal line branch in the wire area, and the second sub-signal line segment and the second sub-signal line branch are connected to each other; wherein, in one circuit area, a gap between the first sub-signal line segment and the second sub-signal line segment is D3; in one wire area, a gap between the first sub-signal line branch and the second sub-signal line branch is D4; D4 < D3.

7. The display panel of claim 6, wherein, in the first display area: the signal lines comprise third and fourth sub-signal lines having the same extension direction, the third sub-signal line comprises a third sub-signal line segment in the circuit area and a third sub-signal line branch in the wire area, and the third sub-signal line segment and the third sub-signal line branch are connected to each other; the fourth sub-signal line comprises a fourth sub-signal line segment in the circuit area and a fourth sub-signal line branch in the wire area, and the fourth sub-signal line segment and the fourth sub-signal line branch are connected to each other; wherein, in the wire area: in a direction perpendicular to a plane on which a substrate of the display panel lies, the third sub-signal line branch and the fourth sub-signal line branch at least partially overlap.

8. The display panel of claim 6, wherein, the first display area comprises a light-transmitting area and a non-light-transmitting area, the non-light-transmitting area comprises the circuit area, the wire area, and a region in which the light-emitting device is located; the non-light-transmitting area at least partially surrounds the light-transmitting area; and the light-transmitting area has a circular shape, an elliptical shape, or an irregular shape.

9. The display panel of claim 8, wherein, the circuit area comprises a light-emitting device group, the light-emitting device group comprises n light-emitting devices, in the pixel circuit group, at least one pixel circuit is electrically connected to at least one light-emitting device; n = 3, the light-emitting device group comprises a first light-emitting device, a second light-emitting device, and a third light-emitting device having different light-emitting colors; in one light-emitting device group: the three light-emitting devices are arranged in a "π" shape; the first light-emitting device is a red light-emitting device for emitting red light, the second light-emitting device is a blue light-emitting device for emitting blue light, and the third light-emitting device is a green light-emitting device for emitting green light. In the first direction, the length of the second light emitting device is greater than the length of the first light emitting device and the length of the majority of the third light emitting devices.

10. The display panel of claim 6, wherein, the circuit region comprises a light emitting device group, the light emitting device group comprises n light emitting devices, in the pixel circuit group, one pixel circuit is electrically connected to at least one light emitting device; n = 4, the light emitting device group comprises a first light emitting device, a second light emitting device and two third light emitting devices with different light emitting colors; the first light emitting device is a red light emitting device emitting red light, the second light emitting device is a blue light emitting device emitting blue light, and the third light emitting device is a green light emitting device emitting green light.

11. The display panel of claim 1 or 3, wherein, the second display region further comprises a light emitting device group, the light emitting device group comprises n light emitting devices; in the pixel circuit group, one pixel circuit is electrically connected to at least one light emitting device; n = 4, the light emitting device group comprises a first light emitting device, a second light emitting device and two third light emitting devices with different light emitting colors; in one light emitting device group: four light emitting devices are respectively located at four corner positions of a first virtual quadrilateral, wherein two third light emitting devices are respectively located at a pair of corner positions of the first virtual quadrilateral, and the first light emitting device and the second light emitting device are located at another pair of corner positions of the first virtual quadrilateral; the first light emitting device is a red light emitting device emitting red light, the second light emitting device is a blue light emitting device emitting blue light, and the third light emitting device is a green light emitting device emitting green light; the light emitting area of the light emitting device is rectangular, circular, rounded rectangular, elliptical or hexagonal.

12. A display panel, characterized by The display panel comprises a display region, the display region comprises pixel circuits, light emitting devices and signal lines; the pixel circuits are electrically connected to the light emitting devices, and the signal lines are electrically connected to the pixel circuits; the signal lines comprise power signal lines extending in a first direction, and the display region comprises a first display region and a second display region; the first display region comprises a circuit region and a wiring region, the circuit region comprises at least one pixel circuit group, the pixel circuit group comprises n pixel circuits arranged in a second direction, n is a positive integer and n ≥ 2, and the second direction intersects the first direction; in the circuit region: the display panel comprises a first connecting part extending in the second direction, and the pixel circuits belonging to the same pixel circuit group are electrically connected to the power signal lines through the first connecting part; in the second display region: the pixel circuits in the same pixel circuit group are electrically connected to the same power signal line, and the number of pixel circuits in the pixel circuit group in the second display region is not greater than the number of pixel circuits in the pixel circuit group in the first display region.

13. A display panel, characterized by The display panel comprises a display area, the display area comprises a pixel circuit, a light emitting device and a signal line; the pixel circuit is electrically connected with the light emitting device, and the signal line is electrically connected with the pixel circuit; the signal line comprises a power signal line extending in a first direction, and the display area comprises a first display area and a second display area; The first display area comprises a circuit area and a wiring area, the circuit area comprises at least one pixel circuit group, the pixel circuit group comprises n pixel circuits arranged in a second direction, n is greater than or equal to 2 and is a positive integer, and the second direction intersects the first direction; In the circuit area, the display panel comprises a first connecting part extending along the second direction, and the pixel circuits belonging to the same pixel circuit group are electrically connected with the power signal line through the first connecting part; The pixel circuit comprises a driving transistor, a first light emitting control transistor M1 and a second light emitting control transistor M6; In the circuit area, the power signal line comprises a power signal line subsegment; The first electrode of the first light emitting control transistor is electrically connected with the power signal line subsegment, and the second electrode of the first light emitting control transistor is electrically connected with the first electrode of the driving transistor; the first electrode of the second light emitting control transistor is electrically connected with the second electrode of the driving transistor, and the second electrode of the second light emitting control transistor is electrically connected with the first electrode of the light emitting device; The first connecting part comprises a third subconnecting part; The first electrodes of the first light emitting control transistors belonging to the same pixel circuit group are electrically connected with the power signal line subsegment through the third subconnecting part.

14. The display panel of claim 13, wherein The pixel circuit further comprises a data writing transistor, a first reset transistor and a second reset transistor; In the circuit area, the signal line further comprises a data line subsegment, a first scan line subsegment and a light emitting control line subsegment; The first electrode of the data writing transistor is electrically connected with the data line subsegment, the second electrode of the data writing transistor is electrically connected with the first electrode of the driving transistor, and the control terminals of the data writing transistors belonging to the same pixel circuit group are electrically connected with the same first scan line subsegment; The control terminals of the first light emitting control transistors and the control terminals of the second light emitting control transistors belonging to the same pixel circuit group are electrically connected with the same light emitting control line subsegment.

15. The display panel of claim 14, wherein The pixel circuit further comprises a first reset transistor and a second reset transistor; In the circuit area, the signal line further comprises a reset signal line subsegment, a second scan line subsegment and a third scan line subsegment; The first electrode of the first reset transistor is electrically connected with the control terminal of the driving transistor, and the first electrode of the second reset transistor is electrically connected with the first electrode of the light emitting device; the second electrode of the first reset transistor is electrically connected with the reset signal line subsegment, and the second electrode of the second reset transistor is electrically connected with the reset signal line subsegment; The control end of the first reset transistor belonging to the same pixel circuit group is electrically connected with the second scan line subsegment; and the control end of the second reset transistor belonging to the same pixel circuit group is electrically connected with the third scan line subsegment. 16.The display panel of claim 15, wherein, The second end of the first reset transistor belonging to the same pixel circuit group is electrically connected with the first reset signal line subsegment; and the second end of the second reset transistor belonging to the same pixel circuit group is electrically connected with the second reset signal line subsegment. 17.The display panel of claim 15, wherein, The reset signal line subsegment includes a first reset signal line subsegment and a second reset signal line subsegment; The first reset signal line subsegment and the second reset signal line subsegment both extend along the first direction; The second end of the first reset transistor belonging to the same pixel circuit group is electrically connected with the first reset signal line subsegment; The second end of the second reset transistor belonging to the same pixel circuit group is electrically connected with the second reset signal line subsegment. 18.The display panel of claim 17, wherein, In the circuit region, at least two of the power signal line subsegment, the data line subsegment, the first reset signal line subsegment and the second reset signal line subsegment are located in the same metal layer. 19.The display panel of claim 18, wherein, In the circuit region, the power signal line subsegment, the first reset signal line subsegment and the second reset signal line subsegment are located in the same metal layer. 20.The display panel of claim 13, wherein, The pixel circuit includes a storage capacitor including a first plate and a second plate, and the second plate is electrically connected with the power signal line subsegment; In the circuit region, the third sub-connection part and the second plate are located in the same metal layer. 21.The display panel of claim 13, wherein, The pixel circuit includes a storage capacitor including a first plate and a second plate, and the second plate is electrically connected with the power signal line subsegment; In the circuit region, the second plates of the storage capacitors belonging to the same pixel circuit group are electrically connected, and the third sub-connection part is multiplexed as the second plate. 22.The display panel of claim 15, wherein, In the circuit region, at least two of the first scan line subsegment, the second scan line subsegment and the third scan line subsegment are located in the same metal layer.

23. A display panel comprising: The display panel includes a display region including pixel circuits, light emitting devices and signal lines; the pixel circuits are electrically connected with the light emitting devices, and the signal lines are electrically connected with the pixel circuits; the signal lines include power signal lines extending in a first direction, and the display region includes a first display region and a second display region; The first display area includes a circuit area and a trace area, the circuit area includes at least one pixel circuit group, the pixel circuit group includes n pixel circuits arranged in a second direction, n is greater than or equal to 2 and is a positive integer, and the second direction intersects the first direction; In the circuit area, the display panel includes a first connecting part extending along the second direction, and the pixel circuits belonging to the same pixel circuit group are electrically connected to the power signal line through the first connecting part; The power signal line includes a first power signal line located in the first display area and a second power signal line located in the second display area, and the first power signal line and the second power signal line are electrically connected; The first power signal line includes a power signal line subsegment located in the circuit area and a power signal line branch located in the trace area; At least two of the power signal line subsegment, the power signal line branch and the second power signal line are located in the same metal layer.

24. The display panel of claim 12 or 13 or 23, wherein, In the circuit area, the power signal line electrically connected to the pixel circuit group is located between two adjacent pixel circuits in the pixel circuit group.

25. A display panel comprising: The display panel includes a display area, the display area includes a pixel circuit, a light emitting device and a signal line, the pixel circuit is electrically connected to the light emitting device, and the signal line is electrically connected to the pixel circuit; the signal line includes a reset signal line extending in a first direction, and the display area includes a first display area and a second display area; The first display area includes a circuit area and a trace area, the circuit area includes at least one pixel circuit group, the pixel circuit group includes n pixel circuits arranged in a second direction, n is greater than or equal to 2 and is a positive integer, and the second direction intersects the first direction; In the circuit area, the display panel includes a first connecting part extending along the second direction, and the pixel circuits belonging to the same pixel circuit group are electrically connected to the reset signal line through the first connecting part; The pixel circuit includes a driving transistor, a first reset transistor M5 and a second reset transistor M7; a first electrode of the first reset transistor is electrically connected to a control end of the driving transistor; and a first electrode of the second reset transistor is electrically connected to a first electrode of the light emitting device; The first connecting part includes a first sub-connecting part and a second sub-connecting part; In the circuit area, the reset signal line includes a reset signal line subsegment; A second electrode of the first reset transistor belonging to the same pixel circuit group is electrically connected to the reset signal line subsegment through the first sub-connecting part, and a second electrode of the second reset transistor belonging to the same pixel circuit group is electrically connected to the reset signal line subsegment through the second sub-connecting part.

26. The display panel of claim 25, wherein, The reset signal line subsegment includes a first reset signal line subsegment and a second reset signal line subsegment; The first reset signal line subsegment and the second reset signal line subsegment both extend along the first direction; The second electrode of the first reset transistor belonging to the same pixel circuit group is electrically connected with the first reset signal line subsegment through the first subconnection part; and the second electrode of the second reset transistor belonging to the same pixel circuit group is electrically connected with the second reset signal line subsegment through the second subconnection part. 27.The display panel of claim 26, wherein, The pixel circuit further comprises a data write transistor; In the circuit region, the signal line further comprises a data line subsegment, a first scan line subsegment, a second scan line subsegment, a third scan line subsegment, and a light emitting control line subsegment; The first electrode of the data write transistor is electrically connected with the data line subsegment, the second electrode of the data write transistor is electrically connected with the first electrode of the drive transistor, and the control terminal of the data write transistor belonging to the same pixel circuit group is electrically connected with the same first scan line subsegment; The control terminal of the first reset transistor belonging to the same pixel circuit group is electrically connected with the second scan line subsegment, and the control terminal of the second reset transistor belonging to the same pixel circuit group is electrically connected with the third scan line subsegment. 28.The display panel of claim 26, wherein, The pixel circuit further comprises a first light emitting control transistor and a second light emitting control transistor; In the circuit region, the signal line further comprises a power signal line subsegment and a light emitting control line subsegment; The first electrode of the first light emitting control transistor is electrically connected with the power signal line subsegment, the second electrode of the first light emitting control transistor is electrically connected with the first electrode of the drive transistor, the first electrode of the second light emitting control transistor is electrically connected with the second electrode of the drive transistor, and the second electrode of the second light emitting control transistor is electrically connected with the first electrode of the light emitting device; The control terminal of the first light emitting control transistor and the control terminal of the second light emitting control transistor belonging to the same pixel circuit group are both electrically connected with the same light emitting control line subsegment. 29.The display panel of claim 28, wherein, The first connection part comprises a third subconnection part; The first electrode of the first light emitting control transistor belonging to the same pixel circuit group is electrically connected with the power signal line subsegment through the third subconnection part. 30.The display panel of claim 29, wherein, The first subconnection part, the second subconnection part, and the third subconnection part all extend along the second direction; At least two of the first subconnection part, the second subconnection part, and the third subconnection part are located in the same metal layer. 31.The display panel of claim 30, wherein, The pixel circuit comprises a storage capacitor, the storage capacitor comprises a first plate and a second plate, and the second plate is electrically connected with the power signal line subsegment; In the circuit region, the first subconnection part, the second subconnection part, and the third subconnection part are located in the same metal layer as the second plate. 32.The display panel of claim 29, wherein, The pixel circuit comprises a storage capacitor, the storage capacitor comprises a first plate and a second plate, and the second plate is electrically connected with the power signal line subsegment. In the circuit area, the second plates of the storage capacitors belonging to the same pixel circuit group are electrically connected, and the third sub-connection part is multiplexed as the second plate.

33. The display panel of claim 27, wherein, In the circuit area, at least two of the first scan line subsegment, the second scan line subsegment and the third scan line subsegment are located in the same metal layer.

34. The display panel of claim 26, wherein, In the circuit area, the first reset signal line subsegment electrically connected with the pixel circuit group is located between two adjacent pixel circuits in the pixel circuit group, or the second reset signal line subsegment electrically connected with the pixel circuit group is located between two adjacent pixel circuits in the pixel circuit group.

35. The display panel of claim 26, wherein, In the circuit area, the first reset signal line subsegment electrically connected with the pixel circuit group is located on the same side of all pixel circuits in the pixel circuit group, or the second reset signal line subsegment electrically connected with the pixel circuit group is located on the same side of all pixel circuits in the pixel circuit group.

36. A display panel comprising: The display panel comprises a display area, the display area comprises pixel circuits, light emitting devices and signal lines; the pixel circuits are electrically connected with the light emitting devices, and the signal lines are electrically connected with the pixel circuits; the signal lines comprise reset signal lines extending in a first direction, and the display area comprises a first display area and a second display area; The first display area comprises a circuit area and a wiring area, the circuit area comprises at least one pixel circuit group, the pixel circuit group comprises n pixel circuits arranged in a second direction, n≥2 and is a positive integer, and the second direction intersects the first direction; In the circuit area, the display panel comprises a first connection part extending along the second direction, and the pixel circuits belonging to the same pixel circuit group are electrically connected with the reset signal lines through the first connection part; The reset signal lines comprise first reset signal lines located in the first display area and second reset signal lines located in the second display area, and the first reset signal lines and the second reset signal lines are electrically connected; The first reset signal lines comprise reset signal line subsegments located in the circuit area and reset signal line branches located in the wiring area; The reset signal line subsegments, the reset signal line branches and the second reset signal lines are located in the same metal layer.

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