High-speed parallelization FPGA design based on OpenCL

Abstract

The application discloses a high-speed parallelization FPGA design architecture based on OpenCL, and in view of the characteristics of large data volume and high real-time requirement in the field of radar signal processing, a complete CPU+FPGA heterogeneous acceleration scheme supporting multiple parallel optimization modes is provided.The scheme is optimized for common parallel optimization modes such as pipeline parallelism, multi-channel parallel optimization and loop iteration, and three memory access mechanisms, global memory, local memory and direct transmission between kernels, are provided to improve the data transmission efficiency in the parallelization calculation process.The architecture proposed in the application realizes related radar algorithms including two-dimensional FFT calculation and special point calculation, and compared with the efficiency before optimization, analysis results are given, which prove that the proposed architecture can meet the data transmission requirements of most parallel processing.

Description

Technical Field

[0001] This invention belongs to the fields of radar signal processing and heterogeneous computing, and specifically relates to a high-speed parallel FPGA design based on OpenCL. Background Technology

[0002] Heterogeneous computing technology emerged in the mid-1980s. Due to its ability to economically and effectively acquire high-performance computing capabilities, its good scalability, high utilization of computing resources, and its enormous development potential, it has become one of the research hotspots in the field of parallel / distributed computing. OpenCL (Open Computing Language) is the first open, free standard for general-purpose parallel programming for heterogeneous systems, and also a unified programming environment. Based on the C language, it provides a cross-platform, universal API. The development of OpenCL meets the rapidly growing demand for standardized, high-performance applications across various heterogeneous computing platforms.

[0003] In most current applications, computer programs rely heavily on the CPU. However, CPU performance is limited when dealing with large amounts of data. FPGAs, with their powerful computing capabilities, have become the best choice for radar communication among various OpenCL heterogeneous computing platforms. OpenCL, as a cross-platform development language, provides a new CPU+FPGA development method for FPGAs, offering advantages such as short development cycles, high abstraction levels, and strong portability. Summary of the Invention

[0004] Purpose of the Invention: Existing OpenCL-based FPGA implementations are generally ported from existing GPU applications, commonly used in image processing and video encoding / decoding. However, their application in embedded radar signal processing is limited, and the general-purpose FPGA design framework is inefficient in practical radar signal processing, failing to meet the real-time processing requirements of radar. This invention proposes a high-speed parallelized FPGA design based on OpenCL, featuring a more efficient architecture for radar signal processing algorithms. It supports parallel processing of large datasets to improve computational efficiency and incorporates multiple memory access mechanisms, including global memory, local memory, and direct inter-kernel transfer, to address data transmission efficiency issues, thereby enhancing the system's computational performance.

[0005] Technical Solution: This invention proposes a high-speed parallel FPGA design based on OpenCL, supporting common parallelism methods such as pipelined parallelism, multi-channel parallel optimization, and loop unrolling. It also features a variety of memory access mechanisms and implements relevant radar algorithms such as 2D FFT and special point calculation on the FPGA. The specific development steps are as follows:

[0006] (1) OpenCL API call and implementation: Based on the general API interface, different parameter formats are used to configure the special requirements of the kernel according to the specific needs of the radar algorithm.

[0007] (2) Low-level API calls: Call the VxWorks operating system API and SRIO driver functions to achieve communication with the FPGA.

[0008] (3) Instruction reception and distribution: Data is received through the SRIO interface, and the instructions and data are initially split and parsed. The instructions are arbitrated according to the instruction type and kernel number and other information, and then sent to the corresponding computing kernel.

[0009] (4) Pipeline kernel group: It obtains configuration parameters through instruction parsing, configures and calls the kernel, realizes parallel computing, event feedback and data synchronization under the kernel execution model, and interacts with the storage module for the required input data and the kernel's calculation results.

[0010] (5) Data storage: The storage resources that the computing kernel can use are divided into global memory, local memory, inter-kernel direct transmission pipes and kernel private memory. Global memory is implemented by DDR, local memory is implemented by multiple RAMs, inter-kernel direct transmission is implemented by the dedicated module PIPE, and private memory is implemented by RAM or FIFO within the kernel.

[0011] (6) Feedback: The OpenCL support information, platform information, kernel integration status, etc. of the ROM storage platform are fed back to the software through the SRIO interface. Attached Figure Description

[0012] Figure 1 This is a diagram of the high-speed parallelization FPGA implementation architecture designed for this invention.

[0013] Figure 2 This is a schematic diagram of the local memory process of the present invention;

[0014] Figure 3 This is a flowchart illustrating the PIPE module of the present invention; Detailed Implementation

[0015] To illustrate the technical solutions disclosed in this invention in detail, further explanation will be provided below with reference to the accompanying drawings and specific examples.

[0016] The OpenCL architecture is mainly divided into two parts: the host and the device. In this invention, the host is implemented using a CPU, while the device is implemented using an FPGA to meet the real-time processing requirements of radar signals. The high-speed parallelized FPGA architecture implemented in this invention is as follows: Figure 1 As shown, its main modules are as follows:

[0017] (1) Instruction receiving and distribution module: It integrates the SRIO IP kernel interface, which is responsible for receiving response packets from the CPU, parsing instructions and data, sending them to the corresponding computing kernel according to the instruction information, and collecting feedback information to send back to the CPU.

[0018] (2) Pipeline kernel group: responsible for the implementation of specific radar signal processing algorithms. It has a unified interface and adopts pipeline implementation. When hardware resources are sufficient, it can be copied multiple times. Multiple kernels work at the same time to achieve higher parallelism and improve the overall computing efficiency. Different computing kernels can be designed according to different algorithms.

[0019] (3) Storage Module: Responsible for kernel data access. In addition to the kernel's private memory, three data access methods are designed to meet the high-speed parallel transmission requirements: global memory, local memory, and inter-kernel direct transmission pipeline. For data with large volume and wide usage, it is generally stored in global memory. Due to the characteristics of FPGA, global memory is implemented by DDR in this invention. For data with small volume and high access bandwidth, it is generally stored in local memory, which is implemented by multiple RAMs with arbitration mechanism. In this invention, the access efficiency has been further improved through design improvements. For radar algorithm characteristics, for data that does not need to change the data format, does not need to be accessed multiple times, and has extremely high access bandwidth requirements, inter-kernel direct data transmission is achieved through the newly added PIPE module. In this invention, it is implemented by multiple FIFOs with arbitration matching mechanism.

[0020] Due to the bandwidth limitations of DDR in global memory, all kernel groups need to go through the DDR arbitration access module before they can connect to DDR for reading and writing. This means that in parallel computing scenarios, only a few kernel groups can access DDR at any given time, which greatly limits the efficiency of data transmission.

[0021] The local memory module, as a storage module accessible only to the corresponding kernel group, offers lower access latency compared to global memory. In actual construction, data required from global memory is typically cached in the local cache first, thereby reducing the proportion of memory access operations in the overall task and improving processing efficiency. In this invention, to better adapt to the parallel processing requirements of the radar algorithm, in addition to the conventional RAM for caching global data, multiple arbitration access mechanisms from RAM are added, allowing kernels within the group to flexibly read and write data. The flowchart is shown below. Figure 2 As shown, the main steps include:

[0022] (1) Receive the read instruction for global memory and cache the required data in the main RAM;

[0023] (2) Read data from the main RAM according to the main RAM read instruction and send it to the corresponding kernels;

[0024] (3) Read or write the data of each kernel to the corresponding numbered slave RAM according to the read / write instructions and read / write number from the slave RAM;

[0025] (4) Feed back the usage information of main RAM and slave RAM to the instruction receiving and dispatching module and then send it to the CPU.

[0026] In typical OpenCL architectures, memory module access usually employs a many-to-one bus arbitration mechanism, such as the crossbar module for global memory (DDR). While this can be optimized by adding scheduling arbitration mechanisms like priority sorting, data transmission latency and waiting issues persist, failing to meet the demands of real-time radar processing. The newly added PIPE module offers greater flexibility compared to traditional bus arbitration memory access. It allows for the free increase of the number of FIFOs, enabling simultaneous direct data transfer between multiple cores, significantly improving data transmission efficiency during parallel computation. Furthermore, it requires fewer read / write restrictions and less storage resources compared to local RAM. Simultaneously, the introduction of FIFOs as intermediate caches allows for the early release of front-end cores for new computations, mitigating the problem of front-end cores stagnating while waiting for data from back-end cores due to mismatched computation speeds, further enhancing computational efficiency.

[0027] The implementation flowchart of the PIPE module is as follows: Figure 3 As shown, the specific steps include:

[0028] (1) The state machine sequentially visits each connected kernel channel through a polling strategy to check if there is a storage requirement. When the valid signal of the channel data is high, it enters the configuration judgment state.

[0029] (2) When configuring the judgment state, the system will sequentially query the FIFO's free status, the current input channel's configuration status, and the sent channel's blocking status. Only when all judgment conditions are met will the system enter the channel configuration state.

[0030] (3) In the channel configuration state, first set the usage status of the allocated FIFO, the configuration status of the current input channel, and the blocking status of the transmitting channel to 1. Then connect the input data to the input terminal of the FIFO, and store the last signal as the highest bit of din in the FIFO. After two clock cycles, match the transmitting channel with the output terminal of the FIFO according to the transmitting channel information attached to the FIFO's dot terminal. After the output matching is completed, exit the configuration judgment state and continue polling.

[0031] (4) Regarding the FIFO's idle state, this module pre-sets 10 FIFOs. The FIFO's idle state will be set to full only when all FIFOs are in use; otherwise, it will be empty. For the usage state of a single FIFO, it is set to 1 when it is assigned to enter the channel configuration state, i.e., in use, and is set to 0 when the FIFO outputs the last data. The configuration state of the current input channel and the blocking state of the sent channel are both set to 1 when entering the channel configuration state and set to 0 after sending or receiving the last data.

[0032] To illustrate the advantages of the proposed design, we will introduce two common radar algorithms: two-dimensional FFT calculation and special point calculation.

[0033] FFT calculations are commonly used in signal processing fields such as image processing, audio decoding, and radar signal pulse compression. A common optimization method is to transmit the input data required by multiple working kernels in parallel, thereby processing the data results in parallel. However, in scenarios with a large number of FFT points or high real-time requirements for multiple FFT calculations, direct FFT calculation often fails to meet the actual needs of radar signal processing. In such cases, it is necessary to perform FFT calculations on segments of the computation data, such as two-dimensional FFT calculations.

[0034] The steps of the two-dimensional matrix FFT algorithm are as follows: First, divide the sequence to be calculated into an N1xN2 two-dimensional matrix. Then, perform N2 N1-point FFT calculations. Multiply the calculation result by the hinge factor and perform N1 N2-point FFT calculations to obtain the output result.

[0035] In FPGA design, the sequence to be computed is first mapped to the main RAM in local memory. Since the read / write bandwidth of DDR is four times that of the FFT core, and considering the read / write characteristics of dual-port RAM, eight points can be output in parallel for parallel processing. That is, N2 is set to 8, and eight FFT cores are used to compute the N1-point FFT of each segment in parallel. The calculation results are multiplied by the hinge factor and cached in eight slave RAMs in local memory. Then, the corresponding data is retrieved from the eight slave RAMs in sequence to perform N1 eight-point FFT calculations. Since the slave RAMs are dual-port RAMs, this can also be divided into two cores for parallel processing. At the same time, in order to save the latency of switching data between different RAMs, eight FIFOs can be pre-set in the processing core to cache part of the output data from the eight slave RAMs.

[0036] The computational delay of mapping the above two-dimensional matrix FFT algorithm onto an FPGA is compared with that of a typical one-dimensional FFT algorithm, as shown below:

[0037] FFT points clock frequency Computation delay of 2D-FFT / 1D-FFT 8K 200MHz 17.3％ 16K 200MHz 17.0％ 32K 200MHz 16.8％ 64K 200MHz 16.7％

[0038] Of course, for cases with a large number of FFT points, in order to save storage resources, data can be directly obtained from global memory and sent to the corresponding FFT kernel. However, since the read and write bandwidth of DDR is 4 times that of the FFT kernel, it can only meet the input requirements of 4 FFT kernels for parallel computing at the same time. For the above 8 parallel computing segments, the calculation latency of the N1-point FFT of each segment is doubled. However, in actual operation, it is still much less latency than the one-dimensional FFT algorithm.

[0039] Feature point calculation is commonly used in the post-processing stage of radar signal processing. It mainly includes a data modulus accumulation module, a large point sorting module, a feature point control and reading module, and a data packaging module. In FPGA design, the basic workflow is as follows: the host computer first stores the data in the FPGA's DDR via SRIO. The FPGA retrieves the data from the DDR for processing. After data modulus accumulation calculation, the results are sequentially sent to the large point sorting module. After N sorting operations, the N largest values ​​are selected, and their coordinates are sent to the feature point control and reading module. The module reads the data from the DDR and sends it to the data packaging module, which finally sends it back to the host computer via the SRIO port.

[0040] The data transmission between the four modules mentioned above is all implemented through the kernel direct transfer module PIPE. Its main advantages compared to local memory are as follows: First, for the large-point sorting module, the input results need to be accessed and sorted N times. Although it could be stored in local memory, storing the input data in the kernel's private memory via PIPE is more convenient and efficient to save access overhead. Second, for the special point control reading module, its input data can be transmitted through either local memory or the kernel direct transfer module PIPE. However, considering the actual situation of the algorithm, using the kernel direct transfer module PIPE can save some storage and logic resource overhead. Furthermore, this module reads data directly from DDR instead of caching it in local memory first, considering the large data volume in actual radar applications. Finally, also due to the large data volume and the excessive storage resource overhead of caching to local memory, the data is sent to the packaging module via the kernel direct transfer module, accelerating the overall computational efficiency.

[0041] Compared to transmitting data via global memory, using the inter-kernel direct transfer module reduces the frequency of DDR access, thereby reducing communication overhead, lowering congestion latency during multi-kernel parallel operation, improving data transmission efficiency, and meeting the real-time requirements of radar signal processing.

Claims

1. A high-speed parallel FPGA design architecture based on OpenCL, characterized in that... This architecture supports a parallel optimization method, which includes the following steps: (1) Based on the general API interface, different parameter formats are used to configure the special requirements of the radar algorithm, and the parallelization method is used to call multiple kernels for parallel processing. (2) Call the underlying system functions and driver functions to complete the communication with the FPGA; (3) Configure the kernel parallelization process according to the instruction format of the host; (4) According to the configuration instructions, implement parallel computing, event feedback and data synchronization under the kernel execution model, and improve data transmission efficiency through a variety of memory access mechanisms, including global memory, local memory and direct transmission between kernels; (5) Collect OpenCL support information, platform information, kernel integration status, and memory usage information and feed them back to the CPU. (6) The relevant radar algorithms implemented in the architecture include two-dimensional FFT calculation and special point calculation; The aforementioned local memory is characterized by, in addition to the common main RAM that caches some global data, also proposing a slave RAM management mechanism for flexible kernel calls. After receiving read instructions for global memory and caching the calculated data, the main RAM sends it to the corresponding kernels. Each kernel reads or writes to the corresponding slave RAM according to the read / write instructions and read / write numbers, and feeds back the RAM usage information to the instruction receiving and distribution module. The aforementioned inter-kernel direct transmission mechanism is characterized by the ability to freely increase the number of FIFOs to enable simultaneous direct data transmission between multiple kernels, and it has fewer read / write restrictions and requires fewer storage resources compared to RAM in local memory. This module sequentially accesses each connected kernel channel through a polling strategy. When a valid channel signal is received, it enters the configuration judgment state. When the FIFO's free state, the current input channel's configuration state, and the sending channel's blocking state are satisfied, it enters the channel configuration state. After configuration, it re-enters the polling state, realizing the function of simultaneous transmission by multiple kernels. The aforementioned radar algorithms implemented in the architecture include the specific parallelization implementation process of two-dimensional FFT calculation and special point calculation.

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