Semiconductor super junction power device

Abstract

The semiconductor super-junction power device provided by the embodiment of the present application comprises an n-type drain region, an n-type drift region and a plurality of p-type columns, the width of each p-type column is equal, and the interval between two adjacent p-type columns is equal; the top of the p-type column is provided with a p-type body region corresponding to the p-type column, the p-type body region is provided with an n-type source region, and the width of the p-type body region is equal; two gate trenches are arranged between two adjacent p-type body regions, and the width of the gate trench is equal; the symmetry axis of at least part of the p-type body region is offset from the symmetry axis of the corresponding p-type column, so that the interval between the two gate trenches between two adjacent p-type body regions has at least two different interval values. The present application can reduce the sudden change speed of the gate-drain capacitance of the semiconductor super-junction power device when the semiconductor super-junction power device is turned on or turned off, and reduce the gate voltage oscillation of the semiconductor super-junction power device.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor power devices, and particularly relates to a semiconductor super-junction power device. BACKGROUND

[0002] The semiconductor super-junction power device is based on charge balance technology, can reduce on-resistance and parasitic capacitance, and has extremely fast switching characteristics, so that the semiconductor super-junction power device can reduce switching loss and realize higher power conversion efficiency. In the prior art, the gate-drain capacitance (Cgd) of the semiconductor super-junction power device will be mutated when being turned on and turned off, which causes serious oscillation of the gate voltage of the semiconductor super-junction power device. SUMMARY

[0003] Therefore, the application aims to provide a semiconductor super-junction power device to solve the problem of gate-drain capacitance mutation of the semiconductor super-junction power device in the prior art.

[0004] The semiconductor super-junction power device provided by the embodiment of the application comprises a terminal region and a cell region, and the cell region comprises:

[0005] an n-type drain region, an n-type drift region and a plurality of p-type columns, the width of each p-type column in the plurality of p-type columns is equal, and the interval between two adjacent p-type columns is equal;

[0006] The top part of each p-type column in the plurality of p-type columns is respectively provided with a p-type body region corresponding to the p-type column in one-to-one correspondence, an n-type source region is arranged in the p-type body region, and the width of the p-type body region is equal;

[0007] Two gate trenches are arranged between two adjacent p-type body regions, the width of the gate trench is equal, and a gate dielectric layer and a gate electrode are arranged in the gate trench;

[0008] The symmetry axis of at least part of the p-type body region is offset from the symmetry axis of the corresponding p-type column, so that the interval between the two gate trenches between two adjacent p-type body regions has at least two different interval values.

[0009] Optionally, the interval between the two gate trenches between two adjacent p-type body regions is sequentially set as: C, C+1D, C, C+1D, C, …; or sequentially set as: C, C+1D, …, C+nD, C+(n-1)D, …, C, C+1D, …, C+nD, C+(n-1)D, …, C, …; or sequentially set as: C, C, …, C+1D, C+1D, …, C+nD, C+nD, …, C+(n-1)D, C+(n-1)D, …, C, C, …, wherein: n≥2 and n is an integer, C is a basic interval value of the interval between the two gate trenches between two adjacent p-type body regions and C>0; and D is a changed value of the interval between the two gate trenches between two adjacent p-type body regions and D>0.

[0010] The semiconductor super-junction power device provided by the application adopts a double-gate trench structure between adjacent p-type body regions, and by adjusting the offset between the symmetry axis of the p-type body region and the symmetry axis of the corresponding p-type column, the interval between the two gate trenches between two adjacent p-type body regions has at least two different interval values, so that the sudden change speed of the gate-drain capacitance of the semiconductor super-junction power device when the semiconductor super-junction power device is turned on or turned off is reduced, and the gate voltage oscillation of the semiconductor super-junction power device is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the application, the drawings needed in the description of the embodiments will be briefly introduced.

[0012] Figure 1 is a cross-sectional structure schematic diagram of the first embodiment of the semiconductor super-junction power device provided by the application. DETAILED DESCRIPTION

[0013] The technical solutions of the application will be described in detail below with reference to the drawings of the embodiments of the application, and the technical solutions of the application will be described completely and specifically through specific ways. Obviously, the described embodiments are a part of the embodiments of the application, rather than all the embodiments of the application. Meanwhile, in order to clearly illustrate the specific embodiments of the application, the sizes of the drawings listed in the description are not representative of the actual sizes, and the drawings in the description are schematic and should not limit the scope of the application.

[0014] Figure 1 is a cross-sectional structure schematic diagram of the first embodiment of the semiconductor super-junction power device provided by the application, as Figure 1 shown, the semiconductor super-junction power device provided by the embodiment of the application comprises an n-type drain region 20, the n-type drain region 20 can be externally connected to a drain voltage through a metal layer.

[0015] A plurality of p-type columns 22, in order to facilitate display and description, Figure 1Three p-type pillars 22 are shown as examples. The width of each p-type pillar 22 in the plurality of p-type pillars 22 is equal, and the spacing between two adjacent p-type pillars 22 is equal, forming a charge-balanced pn junction structure between the p-type pillar 22 and the adjacent n-type drift region 21.

[0016] The top part of each p-type pillar 22 in the plurality of p-type pillars 22 is respectively provided with a p-type body region 23 corresponding to the p-type pillar 22, Figure 1 Three p-type body regions 23a, 23b and 23c are shown as examples, and the width of each p-type body region is equal. An n-type source region 24 is arranged in each p-type body region.

[0017] By setting the width of each p-type body region to be equal, the layout design size of each p-type body region is the same, and the layout design size of each n-type source region is also the same, thereby simplifying the design of the semiconductor super-junction power device.

[0018] Two gate trenches are arranged between two adjacent p-type body regions, and the width of the gate trenches is equal. A gate dielectric layer 26 and a gate electrode 27 are arranged in the gate trenches, and the gate electrode 27 controls the opening and closing of the current channel between the n-type source region 24 and the n-type drift region 21 through a gate voltage.

[0019] In the semiconductor super-junction power device, the symmetry axis of at least some of the p-type body regions is offset from the symmetry axis of the corresponding p-type pillar. Since the width of each p-type pillar 22 in the plurality of p-type pillars 22 is equal, and the spacing between two adjacent p-type pillars 22 is equal, and the width of each p-type body region is equal, the spacing between the two gate trenches between two adjacent p-type body regions has at least two different spacing values. For example, Figure 1 In the example, the symmetry axis of the p-type body region 23a and the p-type body region 23c coincides with the symmetry axis of the corresponding p-type pillar 22, and the symmetry axis of the p-type body region 23b is offset from the symmetry axis of the corresponding p-type pillar 22 by a distance b to the right, thereby making Figure 1 In the example, the spacing between the two gate trenches between two adjacent p-type body regions has two different spacing values a1 and a2, and the difference between a1 and a2 is 2b.

[0020] By setting the offset of one or more p-type body regions, the spacing between the two gate trenches between two adjacent p-type body regions can be set as C, C+1D, C, C+1D, C, … in turn, that is, the spacing between the two gate trenches between at least some adjacent p-type body regions has two different spacing values and is set in turn in a cycle of spacing; or set as C, C+1D, …, C+nD, C+(n-1)D, …, C, C+1D, …, C+nD, C+(n-1)D, …, C, … in turn, that is, the spacing between the two gate trenches between at least some adjacent p-type body regions first increases in turn, then decreases in turn, then increases in turn, and then decreases in turn, and so on; or set as C, C, …, C+1D, C+1D, …, C+nD, C+nD, …, C+(n-1)D, C+(n-1)D, …, C, C, … in turn, that is, the spacing between the two gate trenches between adjacent p-type body regions includes multiple groups of spacing values, the spacing values in the same group of spacing values are the same, and the spacing values in different groups of spacing values first increase in turn, then decrease in turn, and so on, where n≥2 and n is an integer; C is a basic spacing value of the spacing between the two gate trenches between adjacent p-type body regions and C>0; D is a value of the change of the spacing between the two gate trenches between adjacent p-type body regions and D>0, and the specific values of n, C and D are determined according to product design requirements. By setting different spacing values between the two gate trenches between adjacent p-type body regions, as the source-drain voltage rises when the semiconductor super-junction power device is turned on and off, the region with a smaller spacing value will be depleted first, and the gate-drain capacitance will suddenly decrease at this source-drain voltage point; then, as the source-drain voltage further rises, the region with a larger spacing value will be depleted in turn, and the gate-drain capacitance will suddenly decrease at these source-drain voltage points, so that the mutation points of the gate-drain capacitance of the semiconductor super-junction power device are distributed on several different source-drain voltage points, which reduces the mutation speed of the gate-drain capacitance when the semiconductor super-junction power device is turned on and off, and reduces the gate voltage oscillation of the semiconductor super-junction power device.

[0021] The above specific embodiments and examples are specific supports for the technical idea of the present application, and cannot limit the protection scope of the present application. Any equivalent changes or equivalent modifications made according to the technical idea of the present application on the basis of the technical solution are still within the protection scope of the technical solution of the present application.

Claims

1. A semiconductor super junction power device, characterized by, The terminal region and the cell region, the cell region comprising: An n-type drain region, an n-type drift region and a plurality of p-type pillars, each of the p-type pillars having an equal width and an equal spacing between two adjacent p-type pillars; Each of the p-type pillars is provided with a p-type body region corresponding to the p-type pillar, and the p-type body region is provided with an n-type source region, and the width of the p-type body region is equal; Two gate trenches between two adjacent p-type body regions, the gate trenches having an equal width, and the gate trenches are provided with a gate dielectric layer and a gate electrode; At least part of the p-type body region has an offset with the symmetry axis of the corresponding p-type pillar, so that the spacing between the two gate trenches between two adjacent p-type body regions has at least two different spacing values.

2. The semiconductor super junction power device of claim 1, wherein, The spacing values between the two gate trenches between two adjacent p-type body regions are sequentially set as: C, C+1D, C, C+1D, C, …; or sequentially set as: C, C+1D, …, C+nD, C+(n-1)D, …, C, C+1D, …, C+nD, C+(n-1)D, …, C, …; or sequentially set as: C, C, …, C+1D, C+1D, …, C+nD, C+nD, …, C+(n-1)D, C+(n-1)D, …, C, C, …, wherein: n≥2 and n is an integer, C is a basic spacing value of the spacing between the two gate trenches between two adjacent p-type body regions and C>0; D is a changed value of the spacing between the two gate trenches between two adjacent p-type body regions and D>0.

Images