Semiconductor superjunction power devices

Abstract

An embodiment of the present invention provides a semiconductor superjunction power device, comprising an n-type drain region, an n-type drift region, and a plurality of p-type pillars; each of the plurality of p-type pillars has an equal width, and the spacing between two adjacent p-type pillars is equal; a p-type body region corresponding to the p-type pillar is provided on top of each of the plurality of p-type pillars, and the widths of the p-type body regions are all equal; an n-type source region is provided in the p-type body region, and a gate structure for controlling the opening and closing of the current channel between the n-type source region and the n-type drift region; a JFET region is located above the n-type drift region and between adjacent p-type body regions, and the JFET region has two or more different widths. The present invention can reduce the gate-drain capacitance mutation rate of the semiconductor superjunction power device when it is turned on or off, thereby reducing the gate voltage oscillation of the semiconductor superjunction power device.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power devices, and in particular relates to a semiconductor super junction power device. Background Art

[0002] Semiconductor superjunction power devices utilize charge-balance technology to reduce on-resistance and parasitic capacitance, resulting in extremely fast switching characteristics, reduced switching losses, and higher power conversion efficiency. However, existing semiconductor superjunction power devices experience sudden changes in gate-to-drain capacitance (Cgd) when turning on and off, causing severe gate voltage oscillations. Summary of the Invention

[0003] In view of this, an object of the present invention is to provide a semiconductor super junction power device to solve the gate-drain capacitance mutation problem of semiconductor super junction power devices in the prior art.

[0004] An embodiment of the present invention provides a semiconductor super junction power device, comprising a terminal region and a cell region, wherein the cell region comprises:

[0005] An n-type drain region, an n-type drift region, and a plurality of p-type pillars, wherein each of the plurality of p-type pillars has an equal width, and a distance between two adjacent p-type pillars is equal;

[0006] A p-type body region corresponding to the p-type column is provided on the top of each of the plurality of p-type columns, and the widths of the p-type body regions are all equal;

[0007] An n-type source region is provided in the p-type body region, and a gate structure controls the opening and closing of the current channel between the n-type source region and the n-type drift region;

[0008] A JFET region is located above the n-type drift region and between adjacent p-type body regions, and the JFET region has two or more different widths.

[0009] Optionally, the width of the JFET region is set to be: C, C+1D, C, C+1D, C, ... in sequence; or is set to be: C, C+1D, ..., C+nD, C+(n-1)D, ..., C, C+1D, ..., C+nD, C+(n-1)D, ..., C, ... in sequence; or is set to be: C, C, ..., C+1D, C+1D, ..., C+nD, C+nD, ..., C+(n-1)D, C+(n-1)D, ..., C, C, ..., where: n≥2 and n is an integer, C is the basic width of the JFET region and C>0; D is the variable width of the JFET region and D>0.

[0010] Optionally, the gate structure includes a gate dielectric layer covering the current channel region and the JFET region, and a gate located on the gate dielectric layer.

[0011] Optionally, the gate structure includes a gate dielectric layer covering the current channel region, and a gate located above the gate dielectric layer, and the gate is disconnected above the JFET region.

[0012] The present invention adopts two or more JFET region structures with different widths in the cell region of a semiconductor superjunction power device, which can reduce the gate-drain capacitance mutation rate of the semiconductor superjunction power device when it is turned on or off, thereby reducing the gate voltage oscillation of the semiconductor superjunction power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments.

[0014] Figure 1 1 is a schematic cross-sectional view of a first embodiment of a semiconductor super junction power device provided by the present invention;

[0015] Figure 2 It is a schematic cross-sectional structural diagram of a second embodiment of a semiconductor super junction power device provided by the present invention. DETAILED DESCRIPTION

[0016] The following will fully describe the technical solution of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention through specific methods. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. At the same time, to clearly illustrate the specific implementation methods of the present invention, the sizes of the figures listed in the drawings in the specification do not represent the actual sizes. The drawings in the specification are for schematic purposes only and should not limit the scope of the present invention.

[0017] Figure 1 FIG. 1 is a schematic cross-sectional view of a first embodiment of a semiconductor superjunction power device provided by the present invention. Figure 1 As shown, a semiconductor super junction power device provided by an embodiment of the present invention includes an n-type drain region 20 , which can be connected to an external drain voltage through a metal layer, and an n-type drift region 21 located above the n-type drain region 20 .

[0018] For the convenience of display and explanation, a plurality of p-type columns 22 are provided. Figure 1 Only three p-type pillars 22 are shown as examples. Each of the plurality of p-type pillars 22 has the same width, and the spacing between two adjacent p-type pillars 22 is equal. A charge-balanced pn junction structure is formed between the p-type pillars 22 and the adjacent n-type drift region 21.

[0019] The top of each of the plurality of p-type pillars 22 is provided with a p-type body region corresponding to the p-type pillar 22 . Figure 1 The figure shows three p-type body regions, p-type body region 23a, p-type body region 23b, and p-type body region 23c, each having equal width. Setting the widths of the p-type body regions to be equal allows the layout design dimensions of each p-type body region to be identical, and the layout design dimensions of each n-type source region to be identical, simplifying the design of semiconductor superjunction power devices. Furthermore, the current channel length within each p-type body region can be equal, without affecting the consistency of the semiconductor superjunction power device.

[0020] The JFET region is located above the n-type drift region 21 and between adjacent p-type body regions. The JFET region is a parasitic junction field effect transistor region in the super junction power device. Figure 1 exemplarily shows four JFET regions, JFET region 25a, JFET region 25b, JFET region 25c and JFET region 25d, wherein the JFET regions are provided with two or more different widths. Figure 1 The width of the middle JFET region 25b is set to a1, and the width of the JFET region 25c is set to a2.

[0021] Since the width of each p-type column 22 in the plurality of p-type columns 22 is equal, and the spacing between adjacent p-type columns 22 is equal, and the width of the p-type body regions are all equal, in order to realize that the JFET region has two or more different widths, it is necessary to offset some p-type body regions relative to their corresponding p-type columns 22. For example, Figure 1 , the p-type body region 23a and the p-type body region 23c coincide with the symmetry axis of their corresponding p-type column 22, and the symmetry axis of the p-type body region 23b is offset to the right by a distance b from the symmetry axis of its corresponding p-type column 22. Therefore, the difference between the width a1 of the JFET region 25b and the width a2 of the JFET region 25c is 2b.

[0022] By setting the offset of one or more p-type body regions, the JFET region can have two or more different widths. Preferably, the width of the JFET region is sequentially set as: C, C+1D, C, C+1D, C, ..., that is, the width of at least part of the JFET region has two different width values, and they are sequentially arranged in a cyclic manner; or it is sequentially set as: C, C+1D, ..., C+nD, C+(n-1)D, ..., C, C+1D, ..., C+nD, C+(n-1)D, ..., C, ..., that is, the width of at least part of the JFET region first increases, then decreases, then increases, and then decreases. The process is repeated in this way; or the process is sequentially set to: C, C, …, C+1D, C+1D, …, C+nD, C+nD, …, C+(n-1)D, C+(n-1)D, …, C, C, …, that is, the JFET region includes multiple JFET region groups, the widths of the JFET regions in the same JFET region group are the same, and the widths of the JFET regions in different JFET region groups first increase in sequence, and then decrease in sequence, and the process is repeated in this way, wherein: n≥2 and n is an integer; C is the basic width of the JFET region and C>0; D is the variable width of the JFET region and D>0, and the specific values ​​of n, C, and D are determined according to product design requirements. By setting JFET region structures of different widths, when the semiconductor superjunction power device is turned on and off, as the source-drain voltage increases, the JFET region is gradually depleted, and the JFET region with a smaller width will be depleted first, and the gate-drain capacitance will suddenly drop at this source-drain voltage point; then, as the source-drain voltage continues to rise, the JFET regions with a slightly wider width will be depleted in turn, and the gate-drain capacitance will suddenly drop in turn at these source-drain voltage points. As a result, the mutation points of the gate-drain capacitance of the semiconductor superjunction power device are divided into several different source-drain voltage points, which reduces the gate-drain capacitance mutation speed of the semiconductor superjunction power device when it is turned on and off, and reduces the gate voltage oscillation of the semiconductor superjunction power device.

[0023] An n-type source region 24 is provided in each p-type body region, and a gate structure for controlling the opening and closing of the current channel between the n-type source region 24 and the n-type drift region 21 is provided. Figure 1 In the embodiment, the gate structure includes a gate dielectric layer 26 covering the current channel region and the JFET region of the device, and a gate 27 located on the gate dielectric layer 26. This structure can be referred to as a gate of a full-gate structure.

[0024] Figure 2 is a schematic cross-sectional view of a second embodiment of a semiconductor super junction power device provided by the present invention, and Figure 1 Compared with the semiconductor super junction power device shown, Figure 2The gate structure of the semiconductor super junction power device includes a gate dielectric layer 26 covering the current channel region, and a gate 27 located on the gate dielectric layer 26. The gate 27 is disconnected above the JFET region. This structure can be called a split-gate structure gate.

[0025] The above specific implementation methods and examples are specific support for the technical ideas of the present invention and cannot be used to limit the scope of protection of the present invention. Any equivalent changes or equivalent modifications made on the basis of this technical solution in accordance with the technical ideas proposed by the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A semiconductor super junction power device, characterized in that: It includes a terminal region and a cellular region, wherein the cellular region includes: An n-type drain region, an n-type drift region, and a plurality of p-type pillars, wherein each of the plurality of p-type pillars has an equal width, and a distance between two adjacent p-type pillars is equal; A p-type body region corresponding to the p-type column is provided on the top of each of the plurality of p-type columns, and the widths of the p-type body regions are all equal; An n-type source region is provided in the p-type body region; a gate structure for controlling the opening and closing of a current channel between the n-type source region and the n-type drift region; A JFET region is located above the n-type drift region and between adjacent p-type body regions, and the JFET region has two or more different widths.

2. The semiconductor super junction power device according to claim 1, characterized in that: The width of the JFET region is set to be: C, C+1D, C, C+1D, C, ... in sequence; or is set to be: C, C+1D, ..., C+nD, C+(n-1)D, ..., C, C+1D, ..., C+nD, C+(n-1)D, ..., C, ... in sequence; or is set to be: C, C, ..., C+1D, C+1D, ..., C+nD, C+nD, ..., C+(n-1)D, C+(n-1)D, ..., C, C, ..., where: n≥2 and n is an integer, C is the basic width of the JFET region and C>0; D is the variable width of the JFET region and D>0.

3. The semiconductor super junction power device according to claim 1, wherein: The gate structure includes a gate dielectric layer covering the current channel region and the JFET region, and a gate located on the gate dielectric layer.

4. The semiconductor super junction power device according to claim 1, wherein: The gate structure includes a gate dielectric layer covering the current channel region and a gate located on the gate dielectric layer, and the gate is disconnected above the JFET region.

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