Semiconductor super junction power device

Abstract

The embodiment of the present application provides a kind of semiconductor super junction power device, comprising: n-type drain region;N-type drift region is located on the n-type drain region;Several identical width p-type column, the spacing between adjacent two p-type column is same;The top of the p-type column is equipped with first p-type body region, the width of the first p-type body region is same, and first n-type source region is equipped in the first p-type body region;Two gate trenches between adjacent two first p-type body region, gate dielectric layer and gate are equipped in the gate trench;The gate trench is equipped with at least two different widths, so that the spacing between two gate trenches between adjacent two first p-type body region has at least two different spacing values.The present application can adjust the change curve of the gate-drain capacitance of semiconductor super junction power device, and reduce on-resistance.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor power devices, and particularly relates to a semiconductor super-junction power device. BACKGROUND

[0002] The semiconductor super-junction power device is based on charge balance technology, can reduce on-resistance and parasitic capacitance, and has very fast switching characteristics, so that the semiconductor super-junction power device can reduce switching loss and achieve higher power conversion efficiency. In the process of turning on and turning off, the Miller capacitance (Crss) and the gate-drain capacitance (Cgd) corresponding to the Miller capacitance play an important role in the switching process of the semiconductor super-junction power device. The gate-drain capacitance (Cgd) of the known semiconductor super-junction power device will change suddenly when turning on and turning off, which makes the electrical performance of the semiconductor super-junction power device also change suddenly. SUMMARY

[0003] Therefore, the purpose of the application is to provide a semiconductor super-junction power device which can adjust the change curve of the gate-drain capacitance, so as to solve the problem of sudden change of the gate-drain capacitance of the semiconductor super-junction power device in the prior art.

[0004] The semiconductor super-junction power device provided by the embodiment of the application comprises:

[0005] an n-type drain region;

[0006] an n-type drift region located above the n-type drain region;

[0007] a plurality of p-type columns with the same width, and the spacing between adjacent two p-type columns is the same;

[0008] a first p-type body region is arranged at the top of the p-type column, the width of the first p-type body region is the same, and a first n-type source region is arranged in the first p-type body region;

[0009] two gate trenches are arranged between adjacent two first p-type body regions, and a gate dielectric layer and a gate electrode are arranged in the gate trench;

[0010] The gate trench is provided with at least two different widths, so that the spacing between the two gate trenches between adjacent two first p-type body regions is provided with at least two different spacing values.

[0011] Optionally, a second p-type body region is arranged between the two gate trenches between adjacent two first p-type body regions, a second n-type source region is arranged in the second p-type body region, and the width of the second p-type body region is provided with at least two different width values.

[0012] Optionally, the thickness of the gate dielectric layer at the bottom of the gate trench is greater than the thickness of the gate dielectric layer at the sidewall of the gate trench.

[0013] The semiconductor super-junction power device of the embodiment of the present application adopts a double-trench gate structure between adjacent first p-type body regions, adjusts the change curve of the gate-drain capacitance by adjusting the width of the gate trench and the spacing between adjacent gate trenches, and simultaneously, the on-resistance of the semiconductor super-junction power device can be reduced by increasing the number of current channels. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present application, the drawings needed in the description of the embodiments are briefly introduced as follows.

[0015] Figure 1 is a cross-sectional structure schematic diagram of a first embodiment of the semiconductor super-junction power device provided by the present application;

[0016] Figure 2 is a cross-sectional structure schematic diagram of a second embodiment of the semiconductor super-junction power device provided by the present application. DETAILED DESCRIPTION

[0017] The technical solutions of the present application will be described in detail below with reference to the drawings in the embodiments of the present application, through specific means, and the technical solutions of the present application will be completely described. Obviously, the described embodiments are a part of the embodiments of the present application, rather than all the embodiments of the present application. At the same time, in order to clearly illustrate the specific embodiments of the present application, the sizes of the drawings listed in the description of the drawings do not represent the actual sizes, and the drawings in the description are schematic and should not limit the scope of the present application.

[0018] Figure 1 is a cross-sectional structure schematic diagram of a first embodiment of the semiconductor super-junction power device provided by the present application, as Figure 1 shown, a semiconductor super-junction power device provided by the embodiment of the present application includes an n-type drain region 20, the n-type drain region 20 can be externally connected to a drain voltage through a metal layer. An n-type drift region 21 located above the n-type drain region 20.

[0019] A plurality of p-type columns 23, the widths of the p-type columns 23 are the same, and the spacing between the adjacent two p-type columns 23 is the same, the p-type column 23 and the adjacent n-type drift region 21 form a charge-balanced pn junction structure, for the convenience of display and description, Figure 1 only three p-type columns 23 are exemplarily shown in the figure.

[0020] A first p-type body region 24 is arranged at the top of each p-type column 23, the widths of the first p-type body regions 24 are the same, and a first n-type source region 25 is arranged in the first p-type body region 24.

[0021] Two gate trenches are arranged between the adjacent two first p-type body regions 24, the gate trenches are provided with at least two different widths, exemplarily, Figure 1Three gate trenches 22 and one gate trench 22a are shown in the figure, the gate width of the three gate trenches 22 is set as b2, the width of the gate trench 22a is set as b1 (b1≠b2), because the width of the p-type pillars 23 is the same and the interval between the adjacent p-type pillars 23 is the same, and the width of the first p-type body region 24 is also the same, which makes the interval between the two gate trenches between the adjacent two first p-type body regions 24 have at least two different interval values, and in Figure 1 the interval between the two gate trenches between the adjacent two first p-type body regions 24 have c1 and c2 two different interval values, the difference between c1 and c2 is the difference between b1 and b2.

[0022] The gate dielectric layer 26 and the gate electrode 27 are arranged in the gate trench 22, and the gate electrode 27 usually controls the opening and closing of the first current channel of the first p-type body region 24 through the external gate voltage.

[0023] When the semiconductor super-junction power device of the present application is turned on and off, when the source-drain voltage makes the region between the two gate trenches between the adjacent two first p-type body regions be fully depleted, the gate-drain capacitance will suddenly drop at this voltage point, by setting the width of the region to have at least two different values, the region with small width value will be depleted first, and the gate-drain capacitance will suddenly drop at this source-drain voltage point; then, as the source-drain voltage further rises, the region with large width value will be depleted in turn, and the gate-drain capacitance will suddenly drop at these source-drain voltage points. Therefore, the mutation points of the gate-drain capacitance of the product are divided into several different source-drain voltage points, which reduces the mutation speed of the gate-drain capacitance of the product, and also reduces the gate voltage oscillation caused by the mutation of the gate-drain capacitance. The semiconductor super-junction power device of the present application adopts a double-trench gate structure between the adjacent first p-type body regions, and adjusts the width of the gate trench and the interval between the adjacent gate trenches to adjust the change curve of the gate-drain capacitance, which can reduce the gate voltage oscillation.

[0024] Figure 2 is a cross-sectional structure schematic diagram of a second embodiment of the semiconductor super-junction power device provided by the present application, compared with Figure 1 the embodiment shown in the figure, Figure 2 the semiconductor super-junction power device of the present application further comprises a second p-type body region 44, which is arranged between the two gate trenches between the adjacent two first p-type body regions 24 and located above the n-type drift region 21, at this time, the width of the second p-type body region 44 has at least two different width values, and Figure 1 correspondingly, Figure 2The width of the second p-type body region 44 in the semiconductor super-junction power device is provided with two different width values c1 and c2 (c1≠c2). The second n-type source region 45 is provided in the second p-type body region 44, and the gate 27 can also control the opening and closing of the second current channel in the second p-type body region 44 through the gate voltage, and the number of current channels in the semiconductor super-junction power device is increased, which can reduce the on-resistance of the semiconductor super-junction power device.

[0025] The semiconductor super-junction power device can also make the thickness of the gate dielectric layer 26 at the bottom of the gate trench 22 greater than the thickness of the gate dielectric layer 26 at the sidewall of the gate trench 22, which can reduce the value of the gate-drain capacitance and further reduce the degree of gate-drain capacitance mutation. The structure is no longer specifically shown in the embodiments of the present application.

[0026] The above specific embodiments and examples are specific support for the technical idea of the present application, and cannot limit the protection scope of the present application. Any equivalent changes or equivalent modifications made according to the technical idea of the present application on the basis of the technical solution still belong to the protection scope of the technical solution of the present application.

Claims

1. A semiconductor super junction power device, characterized by, Comprise: n-type drain region; n-type drift region above the n-type drain region; a plurality of p-type pillars with the same width, the distance between adjacent two p-type pillars being the same; a first p-type body region on top of the p-type pillar, the first p-type body region having the same width, and a first n-type source region in the first p-type body region; two gate trenches between adjacent two first p-type body regions, the gate trenches having a gate dielectric layer and a gate electrode; the gate trenches have at least two different widths, so that the distance between the two gate trenches between adjacent two first p-type body regions has at least two different distance values.

2. The semiconductor super junction power device of claim 1, wherein, Further comprising a second p-type body region between the two gate trenches between adjacent two first p-type body regions, the second p-type body region having a second n-type source region, and the second p-type body region having at least two different width values.

3. The semiconductor super junction power device of claim 1, wherein, The thickness of the gate dielectric layer at the bottom of the gate trench is greater than the thickness of the gate dielectric layer at the sidewall of the gate trench.

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