An oscillator and voltage regulation circuit

Abstract

The present disclosure provides an oscillator and a voltage regulation circuit, belonging to the technical field of analog circuit power supply control systems, wherein the oscillator is applied to a PWM regulation module of the voltage regulation circuit to provide a pulse signal for the voltage regulation circuit; the voltage regulation circuit is configured to generate an output voltage based on the pulse signal and an input voltage; the oscillator includes a control unit and a ramp voltage generating circuit; the ramp voltage generating circuit includes M parallel first branches, N parallel second branches and a first switch unit; M and N are both integers greater than or equal to 2; the M parallel first branches and the N parallel second branches are connected in series, and the first switch unit is connected in parallel with the N parallel second branches; any first branch is configured with a current source and a second switch unit connected in series; any second branch is configured with a third switch unit and a regulating capacitor connected in series.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of analog circuit power supply control systems, and in particular relates to an oscillator and a voltage regulation circuit. Background Art

[0002] As people's requirements for the size, battery life, and processing speed of consumer electronic products increase, power management chips, as the heart of portable electronic products, are showing a development trend of becoming smaller and smaller, with higher conversion efficiency and more frequent transient conversions. Among them, switching power supplies have gradually become the first choice for power management chips due to their advantages such as high conversion efficiency and simple circuit structure. DC-DC converters intermittently apply DC voltage to the load by controlling the on and off of power electronic devices, and change the average output voltage by changing the duty cycle. Taking the boost type DC-DC converter as an example, it is widely used in products with boost requirements such as fast charging mobile power supplies and electronic cigarettes. Among traditional methods, taking the voltage mode boost circuit as an example, there is still room for improvement in the efficiency, stability and other aspects of the performance of the switching power supply. Summary of the Invention

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provides an oscillator and a voltage adjustment circuit.

[0004] In a first aspect, an embodiment of the present disclosure provides an oscillator, which is applied to a PWM regulation module of a voltage regulation circuit, and is used to provide a pulse signal for the voltage regulation circuit; the voltage regulation circuit is configured to generate an output voltage according to the pulse signal and an input voltage; the oscillator includes a control unit and a ramp voltage generating circuit; wherein,

[0005] The ramp voltage generating circuit includes M parallel first branches, N parallel second branches, and a first switch unit; M and N are both integers greater than or equal to 2; the M parallel first branches and the N parallel second branches are connected in series, and the first switch unit is connected in parallel with the N parallel second branches; any of the first branches is configured with a current source and a second switch unit connected in series; any of the second branches is configured with a third switch unit and an adjustment capacitor connected in series;

[0006] The first switch unit is configured to switch on the branch in which it is located in response to a first control signal output by the control unit; the first control signal is opposite to the pulse signal;

[0007] The second switch unit is configured to transmit the first current generated by the current source of the first branch in which the second switch unit is located to each of the second branches in response to a second control signal output by the control unit; the second control signal is a control signal generated by the control unit according to a clock frequency;

[0008] The third switch unit is configured to switch on the second branch in response to a third control signal and a fourth control signal output by the control unit, and charge the regulating capacitor of the second branch in which the third switch unit is located through the first current; the third control signal is a control signal generated by the control unit according to the input voltage, and the fourth control signal is a control signal generated by the control unit according to the output voltage; or,

[0009] The second switch unit is configured to transmit the first current generated by the current source of the first branch in which the second switch unit is located to each of the second branches in response to the third control signal and the fourth control signal output by the control unit;

[0010] The third switch unit is configured to switch on the second branch in response to the second control signal output by the control unit, and charge the regulating capacitor of the second branch through the first current.

[0011] In some embodiments, the first switch unit includes a first switch, a first end of the first switch is connected to the first ends of the N parallel second branches, and a second end of the first switch is connected to the second ends of the N parallel second branches.

[0012] In some embodiments, the second switch unit is configured to transmit the first current generated by the current source of the first branch to each of the second branches in response to the second control signal output by the control unit, and the second switch unit includes a second switch; the third switch unit is configured to switch on the second branch in response to the third control signal and the fourth control signal output by the control unit, and charge the regulating capacitor of the second branch in response to the third control signal and the fourth control signal output by the control unit, and the third switch unit includes a third switch and a fourth switch connected in series; wherein,

[0013] The first end of the second switch is connected to the current source, the second end of the second switch is connected to the first end of the third switch, the second end of the third switch is connected to the first end of the fourth switch, the second end of the fourth switch is connected to the first end of the regulating capacitor, and the second end of the regulating capacitor is connected to the first reference voltage end.

[0014] In some embodiments, when the second switch unit is configured to transmit the first current generated by the current source of the first branch in which it is located to each second branch in response to the third control signal and the fourth control signal output by the control unit, the second switch unit includes a third switch and a fourth switch connected in series; when the third switch unit is configured to switch on the second branch in which it is located and charge the adjustment capacitor of the second branch in which it is located with the first current in response to the second control signal output by the control unit, the third switch unit includes a second switch; wherein,

[0015] The first end of the third switch is connected to the current source, the second end of the third switch is connected to the first end of the fourth switch, the second end of the fourth switch is connected to the first end of the second switch, the second end of the second switch is connected to the first end of the regulating capacitor, and the second end of the regulating capacitor is connected to the first reference voltage end.

[0016] In a second aspect, an embodiment of the present disclosure further provides a voltage adjustment circuit, which includes the oscillator described in any one of the above embodiments.

[0017] In some embodiments, the voltage adjustment circuit further includes a sampling feedback module, a PWM adjustment module and a voltage conversion module;

[0018] The voltage conversion module is configured to generate an output voltage according to the pulse signal output by the PWM regulation module and the input voltage;

[0019] The sampling feedback module is configured to sample the output voltage to generate a feedback voltage, and generate a control voltage according to the feedback voltage and a reference voltage;

[0020] The PWM regulation module is configured to generate the pulse signal according to the sawtooth wave signal output by the oscillator and the control voltage.

[0021] In some embodiments, the voltage conversion module includes an inductor, a power switch tube, a diode, a load capacitor and a load resistor; the first end of the inductor is connected to the input voltage end, the second end of the inductor is connected to the second end of the power switch tube and the first end of the diode, the first end of the power switch tube is connected to the second reference voltage end, the control electrode of the power switch tube is connected to the second end of the PWM regulation module, and the second end of the diode is connected to the first end of the load capacitor and the first end of the load resistor.

[0022] In some embodiments, the sampling feedback module includes a first voltage-dividing resistor, a second voltage-dividing resistor, and an error amplifier; the first end of the first voltage-dividing resistor is connected to the second end of the diode, the second end of the first voltage-dividing resistor is connected to the first end of the second voltage-dividing resistor and the inverting input end of the error amplifier, the non-inverting input end of the error amplifier is connected to the reference voltage end, and the output end of the error amplifier is connected to the first end of the PWM regulation module.

[0023] In some embodiments, the PWM regulation module includes a PWM regulator; the output end of the error amplifier is connected to the non-inverting input end of the PWM regulator, the inverting input end of the PWM regulator is connected to the oscillator, and the output end of the PWM regulator is connected to the control end of the power switch tube.

[0024] In some embodiments, the voltage adjustment circuit further includes a loop compensation module to compensate for a feedback loop of the voltage adjustment circuit.

[0025] In some embodiments, the loop compensation module includes a first resistor, a second resistor, a first capacitor, a second capacitor and a third capacitor; the first end of the first resistor is connected to the output end of the error amplifier, the second end of the first resistor is connected to the first end of the first capacitor, the second end of the first capacitor is connected to the inverting input end of the error amplifier, the first end of the third capacitor is connected to the output end of the error amplifier, and the second end of the third capacitor is connected to the inverting input end of the error amplifier; the first end of the second resistor is connected to the first end of the first voltage divider resistor, the second end of the second resistor is connected to the first end of the second capacitor, and the second end of the second capacitor is connected to the second end of the first voltage divider resistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of a voltage adjustment circuit structure provided by an embodiment of the present disclosure;

[0027] Figure 2 for Figure 1 Schematic diagram of the small signal model transfer function of the circuit in the figure;

[0028] Figure 3 It is a traditional ramp voltage generating circuit;

[0029] Figure 4 for Figure 1 Schematic diagram of the boost circuit structure;

[0030] Figure 5 for Figure 4 Voltage and current waveforms of the Boost circuit in DCM mode;

[0031] Figure 6 This is a typical waveform diagram of the voltage mode control system;

[0032] Figure 7 A ramp voltage generating circuit provided in an embodiment of the present disclosure;

[0033] Figure 8 Another ramp voltage generating circuit is provided in an embodiment of the present disclosure.

[0034] The figures are marked as follows: 1. oscillator; 2. sampling feedback module; 3. PWM regulation module; 4. voltage conversion module; 5. loop compensation module; P1, pulse signal; Vin, input voltage; Vout, output voltage; Vfb, feedback voltage; Vref, reference voltage; Vc, control voltage; Islp, current source; Cslp, regulation capacitor; L, inductor; S1, power switch tube; S2, diode; Co, load capacitor; Rload, load resistor; Vramp, ramp voltage; 10, first switch unit; 20, second switch unit; 30, third switch unit; 11, first switch; 21, second switch; 31, third switch; 32, fourth switch; Rf1, first voltage divider resistor; Rf2, second voltage divider resistor; EA, error amplifier; 03, PWM regulator; R1, first resistor; R2, second resistor; C1, first capacitor; C2, second capacitor; C3, third capacitor. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the disclosure for which protection is sought, but merely represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure.

[0036] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0037] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0038] In the prior art, DC-DC converter is a typical nonlinear system, and its stability is often affected. For the sake of ease of description and understanding, the present disclosure is specifically described by taking the Boost circuit of voltage mode control as an example. The inventors have found that in the Boost circuit of voltage mode control, the traditional ramp voltage generating circuit adopts a fixed current source to charge a fixed capacitor, which can cause the loop gain in the circuit to change with the change of duty cycle, load and switching frequency, making the loop unstable. Normally, in order to ensure that the circuit loop can remain stable under the worst conditions, the slope of the ramp voltage can be maintained at a relatively high level. Although such an arrangement can solve some problems, it also brings about a new problem that overcompensation is prone to occur when the circuit needs a small ramp voltage, which ultimately still affects the stability of the circuit.

[0039] Figure 1 A schematic diagram of a voltage adjustment circuit structure provided by an embodiment of the present disclosure is shown. Figure 2 for Figure 1 Schematic diagram of the small signal model transfer function of the circuit in Figure 3 It is a traditional ramp voltage generating circuit; Figure 1 As shown, the voltage adjustment circuit provided by the embodiment of the present disclosure includes Figure 3The ramp voltage generating circuit shown includes an oscillator 1, a sampling feedback module 2, a PWM regulation module 3 and a voltage conversion module 4; the voltage conversion module 4 is configured to generate an output voltage Vout based on the pulse signal P1 output by the PWM regulation module 3 and the input voltage Vin; the sampling feedback module 2 is configured to sample the output voltage Vout to generate a feedback voltage Vfb, and generate a control voltage Vc based on the feedback voltage Vfb and a reference voltage Vref; the PWM regulation module 3 is configured to generate a pulse signal P1 based on the sawtooth wave signal output by the oscillator 1 and the control voltage Vc; wherein the voltage conversion module 4 includes an inductor L, a power switch tube S1, a diode S2, a load capacitor Co and a load resistor Rload.

[0040] Specifically, such as Figure 3 As shown, the conventional ramp generating circuit includes a current source Islp and a regulating capacitor Cslp connected in series, and a switch connected in parallel with the regulating capacitor Cslp. The switch responds to a control signal opposite to the pulse signal P1. The current source Islp and the regulating capacitor Cslp are both fixed and do not change with the external environment. That is, a fixed current source Islp charges a fixed regulating capacitor Cslp. Figure 1 and Figure 2 As shown, according to the small signal model transfer function, the loop gain can be calculated as:

[0041] A v =K EA ×F m ×|G VD |×K FB

[0042]

[0043] Among them, A v represents the loop gain; K EA Represents the gain of the error amplifier EA; F m G represents the gain from the error amplifier EA to the boost converter; VD represents the transfer function from duty cycle to output voltage Vout; K FB is the feedback coefficient of the output voltage Vout, that is, from V out to V fb The voltage divider ratio; L is the inductor L value; D is the duty cycle; T s is the clock period; C o is the load capacitance Co of the circuit.

[0044] It is understood that the voltage regulation circuit in the present disclosure can be divided into a continuous conduction mode (CCM) and a discontinuous conduction mode (DCM) depending on whether the current in the inductor L is continuous. For ease of description and understanding, the present disclosure specifically describes the circuit operating in DCM mode as an example.

[0045] Figure 4 for Figure 1 Schematic diagram of the Boost circuit structure. Figure 5 for Figure 4 The voltage and current waveforms of the Boost circuit in DCM mode are as follows: Figure 4 and Figure 5 As shown in the figure, when the power switch tube S1 is turned on, observing the S1 switch current (S1 SwitchCurrent), it can be seen that the voltage (Vsw Voltage) at the Vsw point is at a low level. When the power switch tube S1 is turned off, observing the S2 switch current (S2 Switch Current), it can be seen that the voltage (Vsw Voltage) at the Vsw point is at a high level. The inductor current (Inductor Current) gradually increases when the power switch tube S1 is turned on, and gradually decreases when the diode S2 is turned on, thereby realizing the boost function of the Boost circuit.

[0046] Figure 6 This is a typical waveform diagram of the voltage mode control system, such as Figure 6 As shown, in the voltage-mode controlled Boost circuit, there are Figure 3 The ramp voltage generation circuit shown in the figure generates a ramp voltage Vramp and a control voltage Vc, which are input into a PWM regulator 03. The control voltage Vc is derived by processing the feedback voltage Vfb and the reference voltage Vref via the error amplifier EA. The control voltage Vc serves as the modulation signal for the PWM regulator 03, while the ramp voltage Vramp serves as the carrier signal. When the ramp voltage Vramp rises to the control voltage Vc, the PWM regulator 03 flips, causing the power switch S1 to change state, thereby returning the switching power supply circuit to its desired operating state.

[0047] Depend on Figure 6 It can be seen that the duty cycle can be obtained by dividing the control voltage Vc by the peak value of the ramp voltage Vramp, that is,

[0048]

[0049] Among them, F m D to V c The gain, therefore

[0050]

[0051] Assume that the slope of the ramp voltage Vramp is S e ,So

[0052]

[0053] available

[0054]

[0055] The ramp voltage Vramp is generated as follows Figure 3 As shown, we can get

[0056]

[0057] According to the above analysis and deduction, we can further get

[0058]

[0059] Among them, g m is the transconductance of the error amplifier EA; R c It is the compensation zero resistance outside the error amplifier EA;

[0060] Among them, due to C o Has a certain voltage coefficient (K), and V out The larger the C o The smaller, that is, C o With V out Inversely proportional;

[0061] Therefore, C can be o Simplified to

[0062]

[0063] Then the expression of loop gain can be simplified to

[0064]

[0065] The above formula is (1)

[0066] According to the output current I o With input voltage V in , output voltage V out , switching frequency F s , the inductance L relationship can be seen

[0067]

[0068] Will I o Substituting the expression into (1) we can get

[0069]

[0070] The above formula is (2) and can be further obtained

[0071]

[0072] The above formula is (3)

[0073] In formula (1), it can be seen that the third term is basically a constant. Therefore, as long as the product of the first and second terms is kept at a fixed value, the loop gain can be kept constant.

[0074] Multiplying the product of the first and second terms in (1) to a certain value A, we can get

[0075]

[0076] The above formula is (4)

[0077] It should be noted that since we cannot obtain intuitive information about the output current and duty cycle, we cannot use Equation (1) alone for compensation. However, Equation (3) shows that, compared with Equations (1) and (2), Equation (3) performs square root processing on the output current, which is equivalent to compensating the output current. When compensating the circuit according to Equation (3), the gain can be kept stable under different duty cycles and switching frequencies. At the same time, the output current changes less, and the impact on system stability is also less.

[0078] In view of this, an embodiment of the present disclosure provides an oscillator 1, which is applied to a PWM regulation module 3 of a voltage regulation circuit to provide a pulse signal P1 for the voltage regulation circuit. The oscillator 1 provided by the present disclosure utilizes a dynamic slope compensation circuit to ensure that the circuit loop gain remains stable under various conditions and the phase margin remains within a reasonable range.

[0079] It should be noted that the voltage adjustment circuit mentioned in the embodiment of the present disclosure can be various topology circuits of the switching power supply. For the convenience of description and understanding, the voltage adjustment circuit in the present disclosure is specifically described by taking the voltage-mode controlled Boost circuit as an example.

[0080] On the first aspect, the technical solution adopted to solve the above technical problems is an oscillator 1, which is applied to the PWM regulation module 3 of the voltage regulation circuit to provide a pulse signal P1 for the voltage regulation circuit; the voltage regulation circuit is configured to generate an output voltage Vout according to the pulse signal P1 and the input voltage Vin; the oscillator 1 includes a control unit and a ramp voltage generating circuit. Figure 7 A ramp voltage generating circuit is provided in an embodiment of the present disclosure, such as Figure 7 As shown, the ramp voltage generating circuit includes M parallel first branches, N parallel second branches and a first switch unit 10; M and N are both integers greater than or equal to 2; the M parallel first branches and the N parallel second branches are connected in series, and the first switch unit 10 is connected in parallel with the N parallel second branches; any first branch is configured with a current source Islp and a second switch unit 20 connected in series; any second branch is configured with a third switch unit 30 and a regulating capacitor Cslp connected in series; the first switch unit 10 is configured to select the branch in which it is located in response to a first control signal output by the control unit; the first control signal is opposite to the pulse signal P1; the second switch The switch unit 20 is configured to transmit the first current generated by the current source Islp of the first branch to each second branch in response to the second control signal output by the control unit; the second control signal is a control signal generated by the control unit according to the clock frequency; the third switch unit 30 is configured to select the second branch in response to the third control signal and the fourth control signal output by the control unit, and charge the adjustment capacitor Cslp of the second branch in which it is located through the first current; the third control signal is a control signal generated by the control unit according to the input voltage Vin, and the fourth control signal is a control signal generated by the control unit according to the output voltage Vout. In the ramp voltage generating circuit in the embodiment of the present disclosure, different adjustment capacitors Cslp are charged by different current sources Islp, thereby changing the slope of the output ramp voltage Vramp, and then changing the duty cycle of the pulse signal P1 in the voltage adjustment circuit. This setting can make the circuit loop gain not change with the duty cycle, load, and switching frequency, thereby ensuring that the system can remain stable under any circumstances.

[0081] Specifically, such as Figure 1 and Figure 7As shown, the first switch unit 10 is configured to respond to a first control signal output by the control unit. The first control signal is opposite to the pulse signal P1. When the power switch tube S1 is turned on, the first switch unit 10 turns off the branch in which it is located, and the current source Islp selected in the first branch charges the regulating capacitor Cslp selected in the second branch. At this time, the ramp voltage Vramp rises until it is the same as the control voltage Vc. At this time, the power switch tube S1 is disconnected, and the first switch unit 10 selects the branch in which it is located, and directly pulls the ramp voltage Vramp to 0. Among them, in the embodiment of the present disclosure, the second switching unit 20 is configured to transmit the first current generated by the current source Islp of the first branch in which it is located to each second branch in response to the second control signal output by the control unit; the second control signal is a control signal generated by the control unit according to the clock frequency; the third switching unit 30 is configured to select the second branch in which it is located in response to the third control signal and the fourth control signal output by the control unit, and charge the adjustment capacitor Cslp of the second branch in which it is located through the first current; the third control signal is a control signal generated by the control unit according to the input voltage Vin, and the fourth control signal is a control signal generated by the control unit according to the output voltage Vout. Specifically, in the embodiment of the present disclosure, the third switch 31 in the third switch unit 30 controls its switching state based on control signals generated by different input voltages Vin, and the fourth switch 32 controls its switching state based on control signals generated by different output voltages Vout. For example, when the first, second, and third second branches are enabled based on control signals generated by different input voltages Vin, the first and second second branches are enabled based on control signals generated by different output voltages Vout. Ultimately, the first and second second branches are enabled. Similarly, the third switch 31 controls its switching state based on control signals generated by different output voltages Vout, and the fourth switch 32 controls its switching state based on control signals generated by different input voltages Vin, thereby also achieving the aforementioned functions. Therefore, in the embodiment of the present disclosure, the control signals generated by the input voltage Vin and the output voltage Vout jointly determine which second branch is enabled, thereby charging the regulating capacitor Cslp on the enabled second branch via the first current. This setting satisfies the condition that A in formula (4) is a certain value, that is,

[0082]

[0083]

[0084] The user can select the second control signal, the third control signal and the fourth control signal output by the control unit according to actual needs, thereby selecting the number of the current source Islp and the adjustment capacitor Cslp, and then changing the slope of the ramp voltage Vramp.

[0085] In some embodiments, Figure 8 Another ramp voltage generating circuit provided by the embodiment of the present disclosure is as follows: Figure 8 As shown, the second switch unit 20 is configured to transmit the first current generated by the current source Islp of the first branch in which it is located to each second branch in response to the third control signal and the fourth control signal output by the control unit; the third switch unit 30 is configured to select the second branch in which it is located in response to the second control signal output by the control unit, and charge the adjustment capacitor Cslp of the second branch in which it is located through the first current. Specifically, in the embodiment of the present disclosure, the third switch 31 in the second switch unit 20 is controlled by the control signal generated by different input voltages Vin, and the fourth switch 32 is controlled by the control signal generated by different output voltages Vout. For example, when the first first branch, the second first branch, and the third first branch are selected according to the control signal generated by different input voltages Vin, and the first first branch and the second first branch are selected according to the control signal generated by different output voltages Vout, the first first branch and the second first branch are ultimately selected. Similarly, the third switch 31 controls its switching state according to the control signal generated by different output voltages Vout, and the fourth switch 32 controls its switching state according to the control signal generated by different input voltages Vin, which can also achieve the above functions. Therefore, in the embodiment of the present disclosure, the control signal generated by the input voltage Vin and the output voltage Vout actually jointly determines the first branch to be selected, thereby transmitting the first current generated by the current source Islp on the selected first branch to each second branch. This setting satisfies the condition that A is a certain value in formula (4), that is,

[0086]

[0087]

[0088] Specifically, in the embodiment of the present disclosure, the user can select the second control signal, the third control signal and the fourth control signal output by the control unit according to actual needs, thereby selecting the number of current sources Islp and adjustment capacitors Cslp, and then changing the slope of the ramp voltage Vramp.

[0089] In some embodiments, the first switch unit 10 includes a first switch 11 , a first end of the first switch 11 connected to first ends of the N parallel second branches, and a second end of the first switch 11 connected to second ends of the N parallel second branches.

[0090] Specifically, such as Figure 7 and Figure 8 As shown, in the embodiment of the present disclosure, the first switch unit 10 includes a first switch 11, which responds to a first control signal output by the control unit, and the first control signal is opposite to the pulse signal P1; when the power switch tube S1 is turned on, the first switch 11 turns off the branch in which it is located, and the current source Islp selected in the first branch charges the regulating capacitor Cslp selected in the second branch. At this time, the ramp voltage Vramp rises until it is the same as the control voltage Vc. At this time, the power switch tube S1 is disconnected, and the first switch 11 selects the branch in which it is located, and directly pulls the ramp voltage Vramp to 0.

[0091] In some embodiments, as Figure 7 As shown, the second switch unit 20 is configured to transmit the first current generated by the current source Islp of the first branch in which it is located to each second branch in response to the second control signal output by the control unit, and the second switch unit 20 includes a second switch 21; the third switch unit 30 is configured to select the second branch in which it is located in response to the third control signal and the fourth control signal output by the control unit, and charge the adjustment capacitor Cslp of the second branch in which it is located through the first current, and the third switch unit 30 includes a third switch 31 and a fourth switch 32 connected in series; wherein, the first end of the second switch 21 is connected to the current source Islp, the second end of the second switch 21 is connected to the first end of the third switch 31, the second end of the third switch 31 is connected to the first end of the fourth switch 32, the second end of the fourth switch 32 is connected to the first end of the adjustment capacitor Cslp, and the second end of the adjustment capacitor Cslp is connected to the first reference voltage end.

[0092] Specifically, in the disclosed embodiment, the second switch 21 responds to a second control signal, the third switch 31 responds to a third control signal, and the fourth switch 32 responds to a fourth control signal. The second control signal is a control signal generated by the control unit based on the clock frequency, the third control signal is a control signal generated by the control unit based on the input voltage Vin, and the fourth control signal is a control signal generated by the control unit based on the output voltage Vout. This configuration allows the number of connected current sources Islp to change based on the switching frequency, and the number of adjustment capacitors Cslp to change based on the input voltage Vin and the output voltage Vout. This ensures that the circuit loop gain remains unchanged with changes in duty cycle, load, and switching frequency, thereby ensuring system stability.

[0093] It should be noted that the first reference voltage terminal in the embodiment of the present disclosure may be a ground terminal.

[0094] In some embodiments, as Figure 8 As shown, the second switch unit 20 is configured to transmit the first current generated by the current source Islp of the first branch in which it is located to each second branch in response to the third control signal and the fourth control signal output by the control unit, and the second switch unit 20 includes a third switch 31 and a fourth switch 32 connected in series; the third switch unit 30 is configured to select the second branch in which it is located in response to the second control signal output by the control unit, and charge the adjustment capacitor Cslp of the second branch in which it is located through the first current, and the third switch unit 30 includes a second switch 21; wherein, the first end of the third switch 31 is connected to the current source Islp, the second end of the third switch 31 is connected to the first end of the fourth switch 32, the second end of the fourth switch 32 is connected to the first end of the second switch 21, the second end of the second switch 21 is connected to the first end of the adjustment capacitor Cslp, and the second end of the adjustment capacitor Cslp is connected to the first reference voltage end.

[0095] Specifically, in the disclosed embodiment, the second switch 21 responds to a second control signal, the third switch 31 responds to a third control signal, and the fourth switch 32 responds to a fourth control signal. The second control signal is a control signal generated by the control unit based on the clock frequency, the third control signal is a control signal generated by the control unit based on the input voltage Vin, and the fourth control signal is a control signal generated by the control unit based on the output voltage Vout. This configuration allows the number of connected current sources Islp to change based on the switching frequency, and the number of adjustment capacitors Cslp to change based on the input voltage Vin and the output voltage Vout. This ensures that the circuit loop gain remains unchanged with changes in duty cycle, load, and switching frequency, thereby ensuring system stability.

[0096] It should be noted that the first reference voltage terminal in the embodiment of the present disclosure may be a ground terminal.

[0097] In some embodiments, the switches in the first switch unit 10 , the second switch unit 20 and the third switch unit 30 of the ramp voltage generating circuit in the embodiment of the present disclosure are single-pole single-throw switches or switching transistors, which is not limited in the present disclosure.

[0098] In some embodiments, when the switches in the first switch unit 10, the second switch unit 20, and the third switch unit 30 are switching transistors, the switching characteristics of the switching transistors are the same. Specifically, the transistors used in the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In order to distinguish the source and drain of the transistor, one of the poles is called the first pole, the other pole is called the second pole, and the gate is called the control pole. According to the characteristics of the transistor, the transistor can be divided into N-type and P-type. When a P-type transistor is used, the first pole is the source of the P-type transistor, the second pole is the drain of the P-type transistor, and when a low-level signal is input to the gate, the source and drain are turned on; when an N-type transistor is used, the first pole is the source of the N-type transistor, the second pole is the drain of the N-type transistor, and when a high-level signal is input to the gate, the source and drain are turned on.

[0099] In a second aspect, embodiments of the present disclosure further provide a voltage regulation circuit, comprising the oscillator 1 of any of the aforementioned embodiments. The voltage regulation circuit of the embodiments of the present disclosure, after applying the oscillator 1 of the aforementioned embodiments, can compensate for the ramp voltage Vramp, so that the circuit loop gain does not change with changes in duty cycle, load, or switching frequency, thereby ensuring system stability and maintaining constant accuracy of the output voltage Vout. Furthermore, the range of the output voltage Vout of the error amplifier EA varies little under different duty cycle and load conditions, eliminating the need for special consideration of the voltage swing, resulting in a faster dynamic response of the circuit loop.

[0100] In some embodiments, as Figure 1 As shown, the voltage regulation circuit also includes a sampling feedback module 2, a PWM regulation module 3 and a voltage conversion module 4; wherein the voltage conversion module 4 is configured to generate an output voltage Vout according to the pulse signal P1 output by the PWM regulation module 3 and the input voltage Vin; the sampling feedback module 2 is configured to sample the output voltage Vout to generate a feedback voltage Vfb, and generate a control voltage Vc according to the feedback voltage Vfb and the reference voltage Vref; the PWM regulation module 3 is configured to generate a pulse signal P1 according to the sawtooth wave signal output by the oscillator 1 and the control voltage Vc.

[0101] In some embodiments, as Figure 1As shown, the voltage conversion module 4 includes an inductor L, a power switch tube S1, a diode S2, a load capacitor Co and a load resistor Rload; the first end of the inductor L is connected to the input voltage Vin terminal, the second end of the inductor L is connected to the second end of the power switch tube S1 and the first end of the diode S2, the first end of the power switch tube S1 is connected to the second reference voltage terminal, the control electrode of the power switch tube S1 is connected to the second end of the PWM regulation module 3, and the second end of the diode S2 is connected to the first end of the load capacitor Co and the first end of the load resistor Rload.

[0102] In the embodiment of the present disclosure, the voltage conversion module 4 is actually a Boost circuit, which achieves voltage conversion by storing a portion of the input energy in the inductor L and then transmitting the energy to the output terminal by turning the power switch tube S1 on and off. It should be noted that the power switch tube S1 in the embodiment of the present disclosure can be an N-type tube, and the second reference voltage terminal can be a terminal with a lower voltage than the node connected to the second terminal of the power switch tube S1. The second reference voltage terminal can be grounded.

[0103] In some embodiments, as Figure 1 As shown, the sampling feedback module 2 includes a first voltage-dividing resistor Rf1, a second voltage-dividing resistor Rf2, and an error amplifier EA; the first end of the first voltage-dividing resistor Rf1 is connected to the second end of the diode S2, the second end of the first voltage-dividing resistor Rf1 is connected to the first end of the second voltage-dividing resistor Rf2 and the inverting input end of the error amplifier EA, the non-inverting input end of the error amplifier EA is connected to the reference voltage Vref end, and the output end of the error amplifier EA is connected to the first end of the PWM regulation module 3.

[0104] In the embodiment of the present disclosure, the output voltage Vout is divided by a first voltage-dividing resistor Rf1 and a second voltage-dividing resistor Rf2, and the collected feedback voltage Vfb is input to the inverting input terminal of the error amplifier EA, and the reference voltage Vref is input to the non-inverting input terminal of the error amplifier EA. The error amplifier EA amplifies the error between the feedback voltage Vfb and the reference voltage Vref and outputs it to the PWM module.

[0105] In some embodiments, as Figure 1 As shown, the PWM regulation module 3 includes a PWM regulator 03; the output end of the error amplifier EA is connected to the non-inverting input end of the PWM regulator 03, the inverting input end of the PWM regulator 03 is connected to the oscillator 1, and the output end of the PWM regulator 03 is connected to the control end of the power switch tube S1.

[0106] In the disclosed embodiment, the output voltage Vout of the voltage regulation circuit is dependent on the input voltage Vin, the duty cycle, and the load. A specific modulation scheme can be employed to adjust the duty cycle, thereby stabilizing the circuit output voltage Vout. In the disclosed embodiment, the non-inverting input of the PWM regulator 03 receives a control voltage Vc, while the inverting input of the PWM regulator 03 receives a ramp voltage Vramp. The PWM regulator 03 compares the control voltage Vc with the ramp voltage Vramp and outputs a pulse signal P1 with a specific duty cycle to control the on / off switching of the power switch S1.

[0107] In some embodiments, as Figure 1 As shown, the voltage regulation circuit also includes a loop compensation module 5 to compensate for the feedback loop of the voltage regulation circuit. In the voltage regulation circuit of the embodiment of the present disclosure, the factors that cause the output voltage Vout to be unstable are mainly changes in the input voltage Vin and the output load. For example, if the output voltage Vout oscillates violently or cannot return to the rated output voltage Vout within a certain period of time, this is a fatal hazard to the system, so loop compensation is required to enable it to output stably when facing external interference. Therefore, in general, there are two reasons for performing loop compensation: one is to hope that the output can quickly return to a stable value when the input and load change; the other is to ensure that the system can quickly return to a stable value after being disturbed, and the overshoot value is within an acceptable range.

[0108] In some embodiments, as Figure 1 As shown, the loop compensation module 5 includes a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2 and a third capacitor C3; the first end of the first resistor R1 is connected to the output end of the error amplifier EA, the second end of the first resistor R1 is connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is connected to the inverting input end of the error amplifier EA, the first end of the third capacitor C3 is connected to the output end of the error amplifier EA, and the second end of the third capacitor C3 is connected to the inverting input end of the error amplifier EA; the first end of the second resistor R2 is connected to the first end of the first voltage divider resistor Rf1, the second end of the second resistor R2 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the second end of the first voltage divider resistor Rf1. In the embodiment of the present disclosure, the circuit is loop compensated by adopting a double-zero three-pole compensation circuit; wherein, the zero point is in front and the pole is in the back, which can increase more phases, thereby pushing up the shear frequency and improving the system response rate.

[0109] It should be noted that the structure of the loop compensation module 5 in the embodiment of the present disclosure includes but is not limited to the first resistor R1, the second resistor R2, the first capacitor C1, the second capacitor C2 and the third capacitor C3, and can be specifically configured according to actual needs, and the present disclosure does not impose any restrictions on this.

[0110] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. An oscillator, applied to a PWM regulation module of a voltage regulation circuit, for providing a pulse signal to the voltage regulation circuit; the voltage regulation circuit is configured to generate an output voltage based on the pulse signal and an input voltage; characterized in that: The oscillator includes a control unit and a ramp voltage generating circuit; wherein, The ramp voltage generating circuit includes M parallel first branches, N parallel second branches, and a first switch unit; M and N are both integers greater than or equal to 2; the M parallel first branches and the N parallel second branches are connected in series, and the first switch unit is connected in parallel with the N parallel second branches; any of the first branches is configured with a current source and a second switch unit connected in series; any of the second branches is configured with a third switch unit and an adjustment capacitor connected in series; The first switch unit is configured to switch on the branch in which it is located in response to a first control signal output by the control unit; the first control signal is opposite to the pulse signal; The second switch unit is configured to transmit the first current generated by the current source of the first branch in which the second switch unit is located to each of the second branches in response to a second control signal output by the control unit; the second control signal is a control signal generated by the control unit according to a clock frequency; The third switch unit is configured to switch on the second branch in response to a third control signal and a fourth control signal output by the control unit, and charge the regulating capacitor of the second branch in which the third switch unit is located through the first current; the third control signal is a control signal generated by the control unit according to the input voltage, and the fourth control signal is a control signal generated by the control unit according to the output voltage; or, The second switch unit is configured to transmit the first current generated by the current source of the first branch in which the second switch unit is located to each of the second branches in response to the third control signal and the fourth control signal output by the control unit; The third switch unit is configured to switch on the second branch in response to the second control signal output by the control unit, and charge the regulating capacitor of the second branch through the first current.

2. The oscillator according to claim 1, wherein The first switch unit includes a first switch, a first end of the first switch is connected to the first ends of the N parallel second branches, and a second end of the first switch is connected to the second ends of the N parallel second branches.

3. The oscillator according to claim 1, wherein: The second switch unit is configured to transmit the first current generated by the current source of the first branch to each of the second branches in response to the second control signal output by the control unit, and the second switch unit includes a second switch; the third switch unit is configured to switch on the second branch in response to the third control signal and the fourth control signal output by the control unit, and charge the regulating capacitor of the second branch in response to the third control signal and the fourth control signal output by the control unit, and the third switch unit includes a third switch and a fourth switch connected in series; wherein, The first end of the second switch is connected to the current source, the second end of the second switch is connected to the first end of the third switch, the second end of the third switch is connected to the first end of the fourth switch, the second end of the fourth switch is connected to the first end of the regulating capacitor, and the second end of the regulating capacitor is connected to the first reference voltage end.

4. The oscillator according to claim 1, wherein: When the second switch unit is configured to transmit the first current generated by the current source of the first branch in which it is located to each of the second branches in response to the third control signal and the fourth control signal output by the control unit, the second switch unit includes a third switch and a fourth switch connected in series; when the third switch unit is configured to switch on the second branch in which it is located in response to the second control signal output by the control unit and charge the adjustment capacitor of the second branch in which it is located through the first current, the third switch unit includes a second switch; wherein, The first end of the third switch is connected to the current source, the second end of the third switch is connected to the first end of the fourth switch, the second end of the fourth switch is connected to the first end of the second switch, the second end of the second switch is connected to the first end of the regulating capacitor, and the second end of the regulating capacitor is connected to the first reference voltage end.

5. A voltage regulating circuit, characterized in that: Comprising the oscillator according to any one of claims 1-4.

6. The voltage regulating circuit according to claim 5, wherein: It also includes a sampling feedback module, a PWM regulation module and a voltage conversion module; The voltage conversion module is configured to generate an output voltage according to the pulse signal output by the PWM regulation module and the input voltage; The sampling feedback module is configured to sample the output voltage to generate a feedback voltage, and generate a control voltage according to the feedback voltage and a reference voltage; The PWM regulation module is configured to generate the pulse signal according to the sawtooth wave signal output by the oscillator and the control voltage.

7. The voltage regulating circuit according to claim 6, wherein: The voltage conversion module includes an inductor, a power switch tube, a diode, a load capacitor and a load resistor; the first end of the inductor is connected to the input voltage end, the second end of the inductor is connected to the second end of the power switch tube and the first end of the diode, the first end of the power switch tube is connected to the second reference voltage end, the control electrode of the power switch tube is connected to the second end of the PWM regulation module, and the second end of the diode is connected to the first end of the load capacitor and the first end of the load resistor.

8. The voltage regulating circuit according to claim 7, wherein: The sampling feedback module includes a first voltage-dividing resistor, a second voltage-dividing resistor, and an error amplifier; the first end of the first voltage-dividing resistor is connected to the second end of the diode, the second end of the first voltage-dividing resistor is connected to the first end of the second voltage-dividing resistor and the inverting input end of the error amplifier, the non-inverting input end of the error amplifier is connected to the reference voltage end, and the output end of the error amplifier is connected to the first end of the PWM regulation module.

9. The voltage regulating circuit according to claim 8, wherein: The PWM regulation module includes a PWM regulator; the output end of the error amplifier is connected to the non-inverting input end of the PWM regulator, the inverting input end of the PWM regulator is connected to the oscillator, and the output end of the PWM regulator is connected to the control end of the power switch tube.

10. The voltage regulating circuit according to claim 8, wherein: A loop compensation module is also included to compensate the feedback loop of the voltage regulation circuit.

11. The voltage regulating circuit according to claim 10, wherein: The loop compensation module includes a first resistor, a second resistor, a first capacitor, a second capacitor and a third capacitor; the first end of the first resistor is connected to the output end of the error amplifier, the second end of the first resistor is connected to the first end of the first capacitor, the second end of the first capacitor is connected to the inverting input end of the error amplifier, the first end of the third capacitor is connected to the output end of the error amplifier, and the second end of the third capacitor is connected to the inverting input end of the error amplifier; the first end of the second resistor is connected to the first end of the first voltage divider resistor, the second end of the second resistor is connected to the first end of the second capacitor, and the second end of the second capacitor is connected to the second end of the first voltage divider resistor.

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