Method for access control by means of multi-stage garbage collection management and related device

Abstract

This invention provides a method and related apparatus for access control of a memory device using multi-stage garbage collection management. The method includes: during a first garbage collection phase, sending a first simple read instruction to a non-volatile memory to attempt to read first valid data from a first source block; sending the first valid data to an internal buffer of the non-volatile memory for programming into a first destination block; sending a second simple read instruction to attempt to read second valid data from the first source block; and preventing a re-attempt to read the second valid data from the first source block if reading the second valid data from the first source block fails; completing at least one host trigger operation; and during a second garbage collection phase, re-attempting to read the second valid data from the first source block.

Description

Technical Field

[0001] This invention relates to memory control, and more particularly to a method and related apparatus, such as a memory device and its memory controller, for access control by means of multi-phase garbage collection (GC) management. Background Technology

[0002] Advances in memory technology have enabled the widespread use of various portable and non-portable memory devices, such as memory cards compliant with SD / MMC, CF, MS, and XD standards, and embedded storage devices compliant with UFS and eMMC standards. Improving access control for these memory devices has always been a problem that needs to be solved in this field.

[0003] NAND flash memory can include single-level cell (SLC) and multiple-level cell (MLC) flash memory. In SLC flash memory, each transistor, acting as a memory cell, can have either a charge value corresponding to logic 0 or 1. In contrast, in MLC flash memory, the storage capacity of each transistor acting as a memory cell can be fully utilized. Transistors in MLC flash memory can be driven by higher voltages than those in SLC flash memory, and different voltage levels can be used to record at least two bits of information (e.g., 00, 01, 11, or 10). Theoretically, the recording density of MLC flash memory can be at least twice that of SLC flash memory, which is why NAND flash memory manufacturers prefer MLC flash memory.

[0004] The low cost and large capacity of MLC flash memory mean it is more likely to be used in memory devices than SLC flash memory. However, MLC flash memory does have instability issues. To ensure that access control of flash memory in a memory device meets the required specifications, the flash memory controller can be equipped with certain management mechanisms to properly manage data access.

[0005] However, even memory devices with the aforementioned management mechanisms may have certain drawbacks. For example, in memory devices containing the aforementioned flash memory, the controller may be designed with limited hardware resources to save on the overall cost of the memory device, thus the controller's data buffer may be very small. During garbage collection (GC), the controller may need to read certain data pages from one or more SLC blocks in the flash memory and write these data pages into quadruple-level cell (QLC) blocks in the flash memory. Due to limited hardware resources, the controller may be forced to buffer only one data page at a time. In the event of an abnormal read where the controller cannot obtain a correctable result from hard decoding when reading a data page, since hard decoding cannot overcome the error, the controller may need to trigger soft decoding. As a result, the flash memory may reuse one of its internal buffers, and in particular, it may corrupt previously received data from the controller, which could lead to a data error problem. One or more other solutions may be proposed to prevent data error problems, but these may introduce other problems, such as certain side effects.

[0006] Therefore, a novel approach and related architecture are needed to avoid the aforementioned problems without or with minimal side effects. Summary of the Invention

[0007] One object of the present invention is to provide a method and related equipment, such as a memory device and a memory controller, for access control through multi-stage waste collection management, in order to solve the above-mentioned problems.

[0008] At least one embodiment of the present invention provides a method for access control of a memory device by means of a multi-phase garbage collection (GC) management. The method is applicable to a controller of the memory device, the memory device including the controller and a non-volatile (NV) memory, the NV memory including at least one NV memory element comprising a plurality of blocks. The method includes: during a first garbage collection phase, sending a first simple read instruction to the NV memory to attempt to read first valid data from a first source block among the plurality of blocks; during the first garbage collection phase, upon successful reading of the first valid data from the first source block, sending the first valid data to an internal buffer of the NV memory for programming into a first destination block among the plurality of blocks; during the first garbage collection phase, Send a second simple read instruction to the non-volatile memory to attempt to read a second valid data from the first source block; during the first garbage collection phase, prevent a re-attempt to read the second valid data from the first source block if reading the second valid data from the first source block fails; complete at least one host-triggered operation during a time period between an end point of the first garbage collection phase and the start point of a second garbage collection phase following the first garbage collection phase, wherein the controller performs the at least one host-triggered operation in response to at least one of a plurality of host instructions from a host device; and during the second garbage collection phase, re-attempt to read the second valid data from the first source block.

[0009] In addition to the methods described above, the present invention also provides a controller for a memory device, the memory device including the controller and a non-volatile (NV) memory, the NV memory including at least one NV memory element, the at least one NV memory element including a plurality of blocks, and the controller including a processing circuit. The processing circuit is configured to control the controller according to a plurality of host instructions from a host device, so as to allow the host device to access the NV memory through the controller. For example: during a first garbage collection phase, the controller sends a first simple read instruction to the non-volatile memory to attempt to read a first valid data from a first source block among the plurality of blocks; during the first garbage collection phase, in response to a successful read of the first valid data from the first source block, the controller sends the first valid data to an internal buffer of the non-volatile memory for programming into a first destination block among the plurality of blocks; during the first garbage collection phase, the controller sends a second simple read instruction to the non-volatile memory to attempt to read a second valid data from the first source block; during the first garbage collection phase... During the period, in response to the failure to read the second valid data from the first source block, the controller prevents a re-attempt to read the second valid data from the first source block; during a time period between an end point of the first garbage collection phase and the start point of a second garbage collection phase following the first garbage collection phase, the controller completes at least one host-triggered operation, wherein the controller performs the at least one host-triggered operation in response to at least one of the plurality of host instructions from the host device; and during the second garbage collection phase, the controller re-attempts to read the second valid data from the first source block.

[0010] In addition to the methods described above, the present invention also provides a memory device, such as a memory device including the controller described above. The memory device includes: a non-volatile memory for storing information; and a controller coupled to the non-volatile memory for controlling the operation of the memory device.

[0011] At least one embodiment of the present invention provides a method for access control of a memory device by means of a multi-phase garbage collection (GC) management, the method being applicable to... The method comprises: a controller of the memory device, the memory device including the controller and a non-volatile (NV) memory, the non-volatile memory including at least one non-volatile memory element, the at least one non-volatile memory element including a plurality of blocks; the method comprising: during a time period prior to the start time of a first garbage collection phase, in response to a plurality of first host instructions from a host device, sending a plurality of first read instructions to the non-volatile memory to attempt to read a first data multiple times from at least one page of a first block, wherein for each of the multiple reads except the last one, reading the first data from the at least one page of the first block is successful, and for the last of the multiple reads, reading the first data from the at least one page of the first block is unsuccessful; during the time period prior to the start time of the first garbage collection phase, in response to the unsuccessful reading of the first data from the at least one page of the first block, sending at least one second read instruction to the non-volatile memory to re-read the data. An attempt is made to read the first data from at least one page of the first block; during the first garbage collection phase, a first valid data is read from at least one first page of a first source block and the first valid data is sent to an internal buffer of the non-volatile memory for programming into a first destination block of the plurality of blocks, wherein the first block is used as the first source block and the at least one first page of the first source block is different from the at least one page of the first block; during the first garbage collection phase, an attempt is made to read the first data from the first source block, and in case the attempt to read the first data from the first source block fails, a re-attempt to read the first data from the first source block is prevented, so as to wait for further processing during a second garbage collection phase following the first garbage collection phase; and during a time period between an end point of the first garbage collection phase and an start point of the second garbage collection phase, in response to at least one other host instruction of the plurality of host instructions, the first valid data is read from the destination block and an attempt is made to read the first data from the first source block.

[0012] In addition to the methods described above, the present invention also provides a controller for a memory device, the memory device including the controller and a non-volatile (NV) memory, the NV memory including at least one NV memory element, the at least one NV memory element including a plurality of blocks, and the controller including a processing circuit. The processing circuit is configured to control the controller according to a plurality of host instructions from a host device, so as to allow the host device to access the NV memory through the controller. For example: During a period of time prior to the start of a first garbage collection phase, in response to multiple first host instructions from the host device, the controller sends multiple first read instructions to the non-volatile memory to attempt to read first data multiple times from at least one page of a first block, wherein reading the first data from the at least one page of the first block is successful in each of the multiple reads except the last one, and reading the first data from the at least one page of the first block is unsuccessful in the last of the multiple reads; During the period of time prior to the start of the first garbage collection phase, in response to the unsuccessful reading of the first data from the at least one page of the first block, the controller sends at least one second read instruction to the non-volatile memory to re-attempt to read the first data from the at least one page of the first block; During the first garbage collection phase, the controller reads data from at least one page of a first source block... A first page reads a first valid data and sends the first valid data to an internal buffer of the non-volatile memory for programming into a first destination block of the plurality of blocks, wherein the first block is used as the first source block and the at least one first page of the first source block is different from the at least one page of the first block; during the first garbage collection phase, the controller attempts to read the first data from the first source block, and in response to the failure to read the first data from the first source block, prevents a re-attempt to read the first data from the first source block, in order to wait for further processing during a second garbage collection phase following the first garbage collection phase; and during a time period between an end point of the first garbage collection phase and an start point of the second garbage collection phase, in response to at least one other host instruction among the plurality of host instructions, the controller reads the first valid data from the destination block and attempts to read the first data from the first source block.

[0013] In addition to the methods described above, the present invention also provides a memory device, such as a memory device including the controller described above. The memory device includes: a non-volatile memory for storing information; and a controller coupled to the non-volatile memory for controlling the operation of the memory device.

[0014] The method and related apparatus of this invention ensure that the memory device operates correctly under various conditions. Examples of the aforementioned apparatus include controllers and memory devices. Furthermore, the method and related apparatus provided by this invention can solve related technical problems without or with a low likelihood of causing side effects. In addition, the method and related apparatus provided by this invention, through multi-stage garbage collection management, can ensure the real-time response of the memory device to the host device, thereby improving overall performance. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0016] Figure 2A An embodiment of the present invention illustrates the use of a multi-phase garbage collection (GC) management system for a memory device such as... Figure 1 The first part of the flowchart of the method for access control of the memory device shown.

[0017] Figure 2B A second part of the flowchart illustrates a method for access control of the memory device by means of multi-stage GC management.

[0018] Figure 3 An embodiment of the present invention is illustrated as follows: Figure 2A as well as Figure 2B The method shown is an access control scheme.

[0019] Figure 4 An embodiment of the present invention is illustrated as follows: Figure 2A as well as Figure 2B The method shown is a multi-stage GC control scheme.

[0020] Figure 5 An embodiment of the present invention is illustrated as follows: Figure 2A as well as Figure 2B The method shown requires an advanced-read (NAR) control scheme for the source block.

[0021] Figure 6 An embodiment of the present invention is illustrated based on, as follows Figure 5 The image shows certain NAR information entries recorded by the source block NAR control scheme.

[0022] Figure 7 An embodiment of the present invention is illustrated as follows: Figure 2A as well as Figure 2BThe method shown is a one-write plus multi-stage GC control scheme.

[0023] Figure 8 An improvement for input / output per second (IOPS) is illustrated according to an embodiment of the present invention.

[0024] [Symbol Explanation]

[0025] 10: Electronic Systems

[0026] 50: Main unit

[0027] 52: Processor

[0028] 54: Power Supply Circuit

[0029] 100: Memory device

[0030] 110: Memory controller

[0031] 112: Microprocessor

[0032] 112M: Read-Only Memory (ROM)

[0033] 112C: Program Code

[0034] 114: Control Logic Circuit

[0035] 116: Random Access Memory (RAM)

[0036] 116B: Data Buffer

[0037] 118: Transmission Interface Circuit

[0038] 120: Non-volatile (NV) memory

[0039] 120B: Internal buffer

[0040] 122-1, 122-2~122-N: Non-volatile (NV) memory elements

[0041] RB: Read buffer

[0042] WB: Write buffer

[0043] SBLK#0: Source Block

[0044] STBL, STBL(0), STBL(1): The source block requires advanced read (NAR) table.

[0045] S10, S11, S12, S13A, S13B, S14, S15A, S15B, S16, S17, S18, S19A, S19B, S20, S21A, S21B: Steps

[0046] Need_AER: Advanced reading flag required.

[0047] t: time Detailed Implementation

[0048] Figure 1This is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 may include a host device 50 and a memory device 100. The host device 50 may include at least one processor (e.g., one or more processors), collectively referred to as processor 52, and the host device 50 may further include a power supply circuit 54 coupled to the processor 52. The processor 52 is configured to control the operation of the host device 50, and the power supply circuit 54 is configured to provide power to the processor 52 and the memory device 100, and to output one or more drive voltages to the memory device 100. The memory device 100 may be configured to provide storage space to the host device 50 and to obtain the one or more drive voltages from the host device 50 as power for the memory device 100. Examples of the host device 50 may include (but are not limited to): a multifunction mobile phone, a wearable device, a tablet computer, and personal computers such as desktop computers and laptop computers. Examples of memory device 100 may include (but are not limited to): a portable memory device (e.g., a memory card conforming to SD / MMC, CF, MS, or XD specifications), a solid-state drive (SSD), and various embedded storage devices such as embedded storage devices conforming to the Universal Flash Storage (UFS) standard or the embedded MMC (eMMC) standard. According to this embodiment, memory device 100 may include a controller such as a memory controller 110 and a non-volatile (NV) memory 120, wherein the controller is configured to control the operation of memory device 100 and access NV memory 120, and NV memory 120 is configured to store information. NV memory 120 may include an internal buffer 120B and at least one NV memory element (e.g., one or more NV memory elements), such as multiple NV memory elements 122-1, 122-2, ..., 122-N, where "N" may represent a positive integer greater than 1. For example, NV memory 120 may be flash memory, and the plurality of NV memory elements 122-1, 122-2, ... and 122-N may be a plurality of flash memory chips or a plurality of flash memory dies, but the present invention is not limited thereto. Additionally, internal buffer 120B may include a read buffer RB and a write buffer WB.The read buffer RB is configured to buffer (or temporarily store) one or more data pages of one or more read operations, such as one or more data pages read from one or more memory elements 122-1, 122-2, ... and 122-N, for reading by the memory controller 110 during the one or more read operations, and the write buffer WB is configured to buffer one or more data pages of one or more write operations, such as one or more data pages sent from the memory controller 110, for programming into one or more NV memory elements 122-1, 122-2, ... and 122-N during the one or more write operations.

[0049] like Figure 1As shown, the memory controller 110 may include processing circuitry such as a microprocessor 112, a storage unit such as a read-only memory (ROM) 112M, a control logic circuitry 114, a random access memory (RAM) 116, and a transmission interface circuitry 118, wherein the above components may be coupled to each other via a bus. RAM 116 is implemented using static random access memory (SRAM), but the invention is not limited thereto. RAM 116 may be configured to provide internal storage space to the memory controller 110. For example, RAM 116 may serve as a buffer memory to buffer data. In particular, RAM 116 may include a buffer as a data buffer 116B, and the data buffer 116B may have a buffer size corresponding to at least one data page (e.g., one or more data pages). The memory controller 110 can be designed with limited hardware resources to save on the overall cost of the memory device 100, so the data buffer 116B can be very small, for example, it can have a buffer size corresponding to a single data page to buffer only one data page, but the invention is not limited thereto. Additionally, in this embodiment, the ROM 112M is used to store program code 112C, and the microprocessor 112 is used to execute program code 112C to control access to the NV memory 120. Note that in some examples, program code 112C can be stored in RAM 116 or any form of memory. Additionally, the data protection circuit (not shown) in the control logic circuit 114 can protect data and / or perform error correction, while the transmission interface circuit 118 can conform to a specific communication standard (such as Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIe), Embedded Multi-Media Card (eMMC), or Universal Flash Storage (UFS)) and can communicate according to that specific communication standard.

[0050] In this embodiment, the host device 50 can access the memory device 100 by sending a host instruction and a corresponding logical address to the memory controller 110. The memory controller 110 receives the host instruction and the logical address, converts the host instruction into a memory operation instruction (hereinafter referred to as an operation instruction), and controls the NV memory to read, write / program, etc., memory cells (e.g., data pages) with physical addresses in the NV memory 120, wherein the physical address may be associated with the logical address. When the memory controller 110 performs an erase operation on any NV memory element 122-n (the symbol "n" can represent any integer in the interval [1,N]) among a plurality of NV memory elements 122-1, 122-2, ... and 122-N, at least one block among the plurality of blocks of the NV memory device 122-n will be erased, wherein each of the plurality of blocks may contain a plurality of pages (e.g., data pages), and access operations (e.g., read or write) may be performed on one or more pages.

[0051] According to some embodiments, the processing circuitry, such as microprocessor 112, can control memory controller 110 according to a plurality of host instructions from host device 50, allowing host device 50 to access NV memory 120 via memory controller 110. Memory controller 110 can store data in NV memory 120 for host device 50, read stored data in response to a host instruction from host device 50 (e.g., one of the plurality of host instructions), and provide data read from NV memory 120 to host device 50. In NV memory 120, such as flash memory, at least one NV memory element (e.g., a plurality of NV memory elements 122-1, 122-2, ..., and 122-N) can include a plurality of blocks, such as a first set of physical blocks in NV memory element 122-1, a second set of physical blocks in NV memory element 122-2, ..., and an Nth set of physical blocks in NV memory element 122-N. Memory controller 110 can be designed to appropriately manage the plurality of blocks such as these sets of physical blocks.

[0052] In particular, these multiple blocks, such as these groups of physical blocks, may contain multiple data blocks (e.g., multiple valid blocks storing valid data) and multiple spare blocks. The memory controller 110 can perform block management on these multiple data blocks and the multiple spare blocks. For example, the memory controller 110 can select a spare block from the multiple spare blocks and change the spare block into a new member of the multiple data blocks, such as a new data block for data writing. In response to a write request to write data at a logical address, the memory controller 110 can write the data to a first location within the NV memory 120, such as a physical address associated with the logical address. In response to another write request to write data at the same logical address, the memory controller 110 can write the data to a second location within the NV memory 120, such as another physical address associated with this logical address, and determine that the data at the first location in the NV memory 120 becomes invalid data. Additionally, the memory controller 110 may trigger a garbage collection (GC) procedure to discard invalid data in one or more of the plurality of data blocks and store the valid data in the one or more data blocks together elsewhere. In particular, it may select one or more spare blocks from the plurality of spare blocks and change the one or more spare blocks into one or more new members of the plurality of data blocks, such as one or more new data blocks, copy the valid data from the one or more data blocks into the one or more new data blocks, and change the one or more data blocks into one or more new members of the plurality of spare blocks, such as one or more new spare blocks, so as to prepare more storage space for further storage of new data by erasing the one or more new spare blocks.

[0053] The memory controller 110 can record, maintain, and / or update block management information for the block management in at least one table, such as at least one temporary table in RAM 116, and at least one non-temporary table in NV memory 120, wherein the latter is in NV memory 120 and may therefore also be referred to as an intra-NV memory (intra-NVM) table. The at least one temporary table may contain a temporary version of at least a portion (e.g., a portion or all) of the at least one non-temporary table. For example, the at least one non-temporary table may contain at least one logical-to-physical (L2P) address mapping table (e.g., one or more L2P address mapping tables) for recording logical addresses (e.g., logical block addresses (LBAs) indicating multiple logical blocks and logical page addresses (LPAs) indicating multiple logical pages within any of the multiple logical blocks) and physical addresses (e.g., physical block addresses (PBAs) indicating multiple physical blocks and physical page addresses indicating multiple physical pages within any of the multiple physical blocks). The at least one temporary table may contain a temporary version of at least one sub-table (e.g., one or more sub-tables) of the at least one L2P address mapping table, wherein the memory controller 110 (e.g., microprocessor 112) can perform bidirectional address translation between the host-side storage space (e.g., logical address) of the host device 50 and the device-side storage space (e.g., physical address) of the NV memory 120 within the memory device 100, in order to access data for the host device 50. For example, the at least one non-temporary table may also contain a spare block management table for managing the plurality of spare blocks, and the at least one temporary table may contain a temporary version of the spare block management table. Additionally, the memory controller 110 may back up the at least one temporary table to the at least one non-temporary table in the NV memory 120 (e.g., one or more NV memory elements 122-1, 122-2, ... and 122-N), and the memory controller 110 may load at least a portion (e.g., part or all) of the at least one non-temporary table into the RAM 116 to become the at least one temporary table for quick reference.For example, the at least one temporary table may also include at least one GC management table for multi-stage GC management, such as a need-advanced-read (NAR) table for at least one source block (e.g., one or more source block NAR tables), collectively referred to as the source block NAR table STBL, and the memory controller 110 may back up the source block NAR table STBL to the NV memory 120 (e.g., the one or more NV memory elements 122-1, 122-2, ... and 122-N) to become part of the at least one non-temporary table in the NV memory 120.

[0054] Figure 2A as well as Figure 2B According to one embodiment of the present invention, a memory device such as [example device] is illustrated by means of a multi-stage GC management. Figure 1 A first part and a second part of a flowchart of a method for access control of a memory device shown, wherein nodes A and B can indicate Figure 2A as well as Figure 2B The connection between their respective local workflows. This method can be applied to... Figure 1 The architecture shown (e.g., electronic device 10, memory device 100, memory controller 110, and microprocessor 112) can be performed by the memory controller 110 (e.g., microprocessor 112) of memory device 100. For better understanding, the first GC phase of the aforementioned GC procedure (in...) Figure 2A (The term "1st GC stage" is used for brevity and may include...) Figure 2A Most of the operations in the first part shown, such as steps S11, S12, S13A, S13B, S14, S15A, and S15B, and a second GC phase of the GC procedure (in Figure 2B (The term "2nd GC stage" is used for brevity and may include...) Figure 2B Most of the operations in the second part shown, such as steps S17, S18, S19A, S19B, S20A, and S20B.

[0055] In step S10, the memory controller 110 (e.g., microprocessor 112) can determine whether the GC program is triggered (labeled "GC" for brevity). If yes, proceed to step S11; otherwise, proceed to step S10.

[0056] For example, the memory controller 110 (e.g., microprocessor 112) can determine whether to trigger the GC procedure based on whether the count of a spare block among the plurality of spare blocks is less than a predetermined spare block count threshold, and in particular, selectively perform one of the following operations:

[0057] (1) If the number of spare blocks is less than the predetermined spare block count threshold, then the GC procedure is triggered; and

[0058] (2) If the number of spare blocks is greater than or equal to the predetermined number of spare blocks, then the GC process should be avoided.

[0059] However, this invention is not limited thereto.

[0060] In step S11, the memory controller 110 (e.g., microprocessor 112) may send a simple read instruction to the NV memory 120 to attempt to read valid data from a source block (e.g., any one of the one or more data blocks), and in particular, to attempt to read the valid data from a physical page within the source block.

[0061] In step S12, the memory controller 110 (e.g., microprocessor 112) can determine whether reading the valid data from the source block (e.g., the physical page such as a data page) was successful. If yes, proceed to step S13A; if no, proceed to step S13B.

[0062] In step S13A, in response to the successful reading of valid data from the source block (e.g., the physical page such as a data page), the memory controller 110 (e.g., microprocessor 112) can send the valid data to the internal buffer 120B (e.g., write buffer WB) of the NV memory 120 for programming into a destination block (e.g., any new data block among one or more new data blocks).

[0063] In step S13B, in response to the failure to read valid data from the source block (e.g., the physical page such as a data page), the memory controller 110 (e.g., microprocessor 112) may skip the data page and mark it as requiring advanced reading, for example by using an Advanced Reading flag Need_AER to indicate that the data page is scheduled for further processing with an advanced read operation during the next GC phase, such as the second (2nd) GC phase.

[0064] For example, within memory device 100, memory controller 110 can be designed with limited hardware resources to save on the overall cost of memory device 100; therefore, the data buffer 116B of memory controller 110 can be small. During the GC process, memory controller 110 may need to read certain data pages from one or more single-level cell (SLC) blocks in NV memory 120 and write these data pages to a higher-level cell block in NV memory 120, such as a triple-level cell (TLC) block, a quadruple-level cell (QLC) block, etc. When data buffer 116B is very small, memory controller 110 may be forced to buffer only one data page at a time. Specifically, this data page is read from the SLC block for buffering in data buffer 116B and then sent to the internal buffer 120B of NV memory 120 for collection as one of a set of associated data pages expected to be simultaneously programmed into the higher-order cellular block, such as the TLC block, the QLC block, etc. For example, when the higher-order cellular block represents the TLC block, the set of associated data pages could be three associated data pages. As another example, when the higher-order cellular block represents the QLC block, the set of associated data pages could be four associated data pages.

[0065] For a normal read where the memory controller 110 can obtain a correctable result from hard-decoding when reading any data page, after the set of associated data pages has been sent to the internal buffer 120B of the NV memory 120, the memory controller 110 can trigger the NV memory 120 to simultaneously program the set of associated data pages into the higher-order cell block. For an abnormal read where the memory controller 110 cannot obtain a correctable result from hard-decoding when reading a data page during the current GC phase, such as the first (1st) GC phase, because hard decoding cannot overcome the error, the memory controller 110 can skip this data page and mark it as requiring further reading, for example, by using the Need_AER flag as described above. Since the memory controller 110 does not need to immediately trigger soft-decoding, the memory controller 110 can prevent the NV memory 120 from reusing its internal buffers 120B (e.g., read buffer RB and / or write buffer WB), and in particular, prevent one or more previously collected data pages in the group of associated data pages in the write buffer WB from being overwritten by other information, thus preventing data error problems from occurring.

[0066] In step S14, the memory controller 110 (e.g., microprocessor 112) can determine whether enough data pages have been collected from the memory controller 110 (e.g., its internal data buffer 116B) into the NV memory 120 (e.g., its internal buffer 120B) for programming. If yes, proceed to step S15A; otherwise, proceed to step S15B.

[0067] For example, if the destination block is a TLC block, the memory controller 110 (e.g., microprocessor 112) may selectively perform one of the following operations:

[0068] (1) When three data pages have been collected into the NV memory 120 (e.g., its internal buffer 120B), the memory controller 110 (e.g., microprocessor 112) can determine that enough data pages have been collected, and therefore proceeds to step S15A; and

[0069] (2) When no three data pages have been collected into the NV memory 120 (e.g., its internal buffer 120B), the memory controller 110 (e.g., microprocessor 112) can determine that not enough data pages have been collected, and thus proceed to this step S15B;

[0070] However, the invention is not limited thereto. For example, when the target region block is a QLC block, the memory controller 110 (e.g., microprocessor 112) can selectively perform one of the following operations:

[0071] (1) When four data pages have been collected into the NV memory 120 (e.g., its internal buffer 120B), the memory controller 110 (e.g., microprocessor 112) can determine that enough data pages have been collected, and therefore proceeds to step S15A; and

[0072] (2) When no four data pages have been collected into the NV memory 120 (e.g., its internal buffer 120B), the memory controller 110 (e.g., microprocessor 112) can determine that not enough data pages have been collected, and thus proceed to step S15B.

[0073] In step S15A, the memory controller 110 (e.g., microprocessor 112) may trigger the programming of data pages collected in the NV memory 120 (e.g., internal buffer 120B therein), for example, by sending a programming-trigger command to the NV memory 120.

[0074] In step S15B, the memory controller 110 (e.g., microprocessor 112) can determine whether the first (1st) GC stage has been completed. If yes, proceed to step S16; otherwise, proceed to step S11.

[0075] like Figure 2A As shown, the memory controller 110 (e.g., microprocessor 112) can perform the following operations:

[0076] (1) During the first GC phase, when step S11 is entered at a first time point, the memory controller 110 may send a first simple read instruction to the NV memory 120 to attempt to read the first valid data from the source block;

[0077] (2) During the first GC phase, when steps S12 and S13A are subsequently entered, in response to the successful reading of the first valid data from the source block, the memory controller 110 may send the first valid data to the internal buffer 120B of the NV memory 120 for programming into the destination block.

[0078] (3) During the first GC phase, when step S11 is entered at a second time point (e.g., a time point after the first time point), the memory controller 110 may send a second simple read instruction to the NV memory 120 to attempt to read second valid data from the source block;

[0079] (4) During the first GC phase, when steps S12 and S13B are subsequently entered, the memory controller 110 can prevent a retry of reading the second valid data from the source block because reading the second valid data from the source block is unsuccessful.

[0080] (5) During the first GC phase, when step S11 is entered at a third time point (e.g., a time point after the second time point), since reading the second valid data from the source block is unsuccessful, the memory controller 110 may send a third simple read instruction to the NV memory 120 to attempt to read the third valid data from the source block; and

[0081] (6) During the first GC phase, when steps S12 and S13B are subsequently entered, in response to the successful reading of the third valid data from the source block, the memory controller 110 may send the third valid data to the internal buffer 120B of the NV memory 120 for programming into the destination block.

[0082] However, the present invention is not limited thereto. Figure 2B As shown, the memory controller 110 (e.g., microprocessor 112) may further perform the following operations:

[0083] (7) During a time period between the end of the first GC phase and the start of the second GC phase following the first GC phase, when re-entering step S16 to wait for the opportunity to start the second GC phase, the memory controller 110 may perform at least one host-triggered operation (e.g., one or more host-triggered operations), wherein the memory controller 110 may perform the at least one host-triggered operation in response to at least one of a plurality of host instructions, in particular, in response to a read request from the host device 50, performing data reading and / or in response to a write request from the host device 50; and

[0084] (8) During the second GC phase, the memory controller 110 may retry reading the second valid data from the source block.

[0085] For example, the plurality of simple read commands may include the first simple read command, the second simple read command, the third simple read command, and so on. To prevent re-attempting to read the second valid data from the source block, the memory controller 110 may prevent the sending of any advanced read command to the NV memory 120, wherein the advanced read command and any simple read command among the plurality of simple read commands belong to different types of read commands. In particular, the advanced read command may represent any read command among the plurality of read commands that causes more read processing time to the NV memory 120 than the simple read command. Examples of the plurality of read commands may include, but are not limited to: a corrective read command, a digital signal processing (DSP)-on read command, a soft-read command, and a Redundant Array of Independent Disks (RAID) recovery read command.

[0086] In step S16, the memory controller 110 (e.g., microprocessor 112) can determine whether to start the second (2nd) GC phase. If yes, proceed to step S17; otherwise, proceed to step S16.

[0087] For example, memory controller 110 (e.g., microprocessor 112) may selectively perform one of the following operations:

[0088] (1) When the memory controller 110 is still performing the at least one host trigger operation in response to at least one host instruction, the memory controller 110 (e.g., microprocessor 112) may determine to continue waiting, in particular, waiting for a predetermined state of the memory device 100, such as a non-busy state, an idle state, etc. (e.g., at least one host trigger operation has been completed and no additional host instruction has been received), and thus proceed to step S16; and

[0089] (2) When the memory controller 110 completes the at least one host trigger operation in response to at least one host instruction, in particular, when the predetermined state is detected, such as the non-busy state, the idle state, etc., the memory controller 110 (e.g., microprocessor 112) may determine to start the second (2nd) GC phase and thus proceed to step S17.

[0090] In step S17, for the valid data (e.g., the second valid data) that was not successfully read during the first GC phase, the memory controller 110 (e.g., microprocessor 112) may send an advanced read instruction to the NV memory 120 to attempt to read the valid data from the source block (e.g., the source block mentioned in step S11), and in particular, to attempt to read the valid data (e.g., the second valid data) from a target page in the second GC phase, wherein the target page may represent any of the previously accessed data pages (e.g., one or more previously accessed data pages) that were skipped and marked as requiring advanced read during the first GC phase in step S13B.

[0091] In the loop including steps S17, S18, and S19B, the memory controller 110 (e.g., microprocessor 112) may send at least one advanced read instruction (e.g., one or more advanced read instructions) such as the advanced read instruction mentioned in step S17 to the NV memory 120 to attempt to read the valid data (e.g., the aforementioned second valid data) from the source block, wherein the at least one advanced read instruction and any of the plurality of simple read instructions belong to different types of read instructions. In particular, the at least one advanced read instruction may include at least one read instruction (e.g., one or more read instructions) from the plurality of read instructions that causes more read processing time for the NV memory 120 than any of the simple read instructions. The memory controller 110 (e.g., microprocessor 112) may use the plurality of read instructions to request the NV memory 120 to enable the relevant read processing mechanisms respectively. Because the read processing mechanisms associated with these multiple types of read instructions are more complex than those associated with any simple read instruction, the read processing time of the NV memory 120 is longer compared to that of any simple read instruction.

[0092] In step S18, the memory controller 110 (e.g., microprocessor 112) can determine whether reading the valid data (e.g., the second valid data) from the source block (e.g., the target page such as any previously accessed data page) was successful. If yes, proceed to step S19A; if no, proceed to step S19B.

[0093] In step S19A, upon successful reading of valid data (e.g., the second valid data) from the source block (e.g., the target page such as any previously accessed data page), the memory controller 110 (e.g., microprocessor 112) can send the valid data to an internal buffer 120B (e.g., write buffer WB) of the NV memory 120 for programming into a destination block in the second GC stage. For example, when the destination block in the first GC stage is not full (e.g., there is more storage space to store additional data pages), the destination block in the second GC stage can be equal to the destination block in the first GC stage. Alternatively, when the destination block in the first GC stage is full (e.g., there is no more storage space to store any additional data pages), the destination block in the second GC stage can be another destination block (e.g., another new data block within one or more new data blocks).

[0094] In step S19B, since reading valid data (e.g., the second valid data) from the source block (e.g., the target page such as any previously accessed data page) is unsuccessful, the memory controller 110 (e.g., the microprocessor 112) can determine whether the next type of advanced read instruction among the various types of advanced read instructions is available. If yes, proceed to step S17 to retry reading the valid data (e.g., the second valid data) from the source block (e.g., the target page such as any previously accessed data page) using the next type of advanced read instruction; if no, proceed to step S19C.

[0095] In step S19C, the memory controller 110 (e.g., microprocessor 112) may execute an error handling procedure (referred to as "EHP" for brevity). For example, in this error handling procedure, the memory controller 110 (e.g., microprocessor 112) may send a predetermined type of advanced read instruction (e.g., the same advanced read instruction just used in step S17) to retry reading the valid data from the same target page (e.g., the same previously accessed data page just accessed in step S17) one or more times, for example, until the number of retry operations of the error handling procedure reaches a predetermined error handling retry count threshold. In a better case where this retry operation is successful, the memory controller 110 (e.g., microprocessor 112) may send the valid data to the internal buffer 120B (e.g., write buffer WB) of the NV memory 120 for programming to the target block in the second GC stage, wherein this sending operation is similar to the sending operation in step S19A. In the worst-case scenario where the retry fails, the memory controller 110 (e.g., microprocessor 112) can record the unsuccessful processing result in a log file for further processing.

[0096] In step S20, the memory controller 110 (e.g., microprocessor 112) can determine whether enough data pages have been collected from the memory controller 110 (e.g., its internal data buffer 116B) into the NV memory 120 (e.g., internal buffer 120B) for programming. If yes, proceed to step S21A; if no, proceed to step S21B.

[0097] For example, if the destination block is a TLC block, the memory controller 110 (e.g., microprocessor 112) may selectively perform one of the following operations:

[0098] (1) When three data pages have been collected into the NV memory 120 (e.g., its internal buffer 120B), the memory controller 110 (e.g., microprocessor 112) can determine that enough data pages have been collected, and therefore proceeds to step S21A; and

[0099] (2) When no three data pages have been collected into the NV memory 120 (e.g., its internal buffer 120B), the memory controller 110 (e.g., microprocessor 112) can determine that not enough data pages have been collected, and thus proceed to step S21B;

[0100] However, the invention is not limited thereto. For example, when the target region block is a QLC block, the memory controller 110 (e.g., microprocessor 112) can selectively perform one of the following operations:

[0101] (1) When four data pages have been collected into the NV memory 120 (e.g., its internal buffer 120B), the memory controller 110 (e.g., microprocessor 112) can determine that enough data pages have been collected, and therefore proceeds to step S21A; and

[0102] (2) When no four data pages have been collected into the NV memory 120 (e.g., the internal buffer 120B therein), the memory controller 110 (e.g., the microprocessor 112) can determine that not enough data pages have been collected, and thus proceed to step S21B.

[0103] In step S21A, the memory controller 110 (e.g., microprocessor 112) may trigger the programming of data pages collected into the NV memory 120 (e.g., internal buffer 120B therein), for example, by sending the programming trigger instruction to the NV memory 120.

[0104] In step S21B, the memory controller 110 (e.g., microprocessor 112) can determine whether the second (2nd) GC stage has been completed. If yes, proceed to step S10; otherwise, proceed to step S17.

[0105] To better understand this method, it can be used... Figure 2A as well as Figure 2B The workflow shown is for illustrative purposes only, but the invention is not limited thereto. According to some embodiments, one or more steps may be performed... Figure 2A as well as Figure 2B Add, delete, or modify within the workflow shown.

[0106] According to some embodiments, the operation of the first GC phase can be performed in the background while the memory controller 110 is writing data from the host device 50 to the NV memory 120 in response to at least one host instruction. For example, the memory controller 110 may be intermittently writing the data to the NV memory 120. As another example, the memory controller 110 may be periodically writing the data to the NV memory 120. Furthermore, the operation of the second GC phase can be performed without the memory device 100 writing any data in response to any host instruction from the host device 50. For the sake of simplicity, similar descriptions in these embodiments will not be repeated here.

[0107] Figure 3 An embodiment of the present invention is illustrated as follows: Figure 2A as well as Figure 2B The method illustrated presents an access control scheme. When the target block is a QLC block, each buffer in the read buffer RB and write buffer WB can be designed to have a buffer size corresponding to four data pages. For example, data buffer 116B can be designed to have a relatively small buffer size, such as a buffer size corresponding to one data page. Memory controller 110 (e.g., microprocessor 112) can use this multi-stage GC management to perform access control of the memory device 100 to prevent data error problems. For simplicity, similar details in these embodiments are not repeated here.

[0108] Figure 4 An embodiment of the present invention is illustrated as follows: Figure 2A as well as Figure 2B The method illustrated presents a multi-stage GC control scheme. The memory controller 110 (e.g., microprocessor 112) can maintain the aforementioned NAR table, such as the source block NAR table STBL, to manage at least one source block (SBLK), such as one or more source blocks. For example, the source block mentioned in step S11 may represent any one of the at least one source blocks, and the at least one source block may contain a first source block, such as SBLK#0, but the invention is not limited thereto. In the case where the at least one source block contains multiple source blocks (e.g., the first source block, such as SBLK#0, and a second source block, such as SBLK#1), the source block mentioned in step S11 may represent any one of the multiple source blocks.

[0109] like Figure 4As shown, during the first GC phase, step S11 can be executed multiple times to attempt to read the valid data from the first source block, such as SBLK#0. Furthermore, for certain physical pages (e.g., four physical pages) with valid data that were not successfully read (marked with "?" for better understanding), step S13B can be executed multiple times (e.g., four times). In this way, the memory controller 110 (e.g., microprocessor 112) can mark these physical pages as needing advanced reads using the Need_AER flag. Specifically, the Need_AER flag is set to a first predetermined value, such as one (marked as "Need_AER = 1" for simplicity), to indicate that these physical pages are scheduled for further processing by advanced read operations during the next GC phase, such as the second GC phase, where the first predetermined value differs from a preset value, such as zero. For simplicity, similar details in these embodiments are not repeated here.

[0110] According to some embodiments, the first predetermined value can be replaced with any of a plurality of predetermined values ​​that are different from the preset value. For the sake of simplicity, similar details in these embodiments will not be repeated here.

[0111] Figure 5 An embodiment of the present invention is illustrated as follows: Figure 2A as well as Figure 2B The method shown is a source block NAR control scheme. When the at least one source block contains multiple source blocks such as SBLK#0, SBLK#1, etc., the source block NAR table STBL can contain multiple sub-tables corresponding to source blocks (SBLK)#0, #1, etc., such as SBLK#0 NAR table STBL(0), SBLK#1 NAR table STBL(1), etc., corresponding to source blocks (SBLK)#0, #1, etc.

[0112] like Figure 5As shown, the index of any source block NAR table corresponding to a certain SBLK in SBLK#0 NAR table STBL(0), SBLK#1 NAR table STBL(1), etc., can be a physical page address (PPA) to indicate a physical page in this SBLK. Since a physical address can contain a physical block address (PBA) to indicate this SBLK (e.g., an SBLK that includes this physical page) and a PPA to indicate the physical page, the memory controller 110 (e.g., microprocessor 112) can determine the at least one previously accessed data page (e.g., at least one physical page that was skipped and marked as needing further reading in step S13B during the first GC phase) based on the source block NAR table STBL (e.g., a sub-table such as the source block NAR table corresponding to this SBLK) to obtain the Need_AER flag corresponding to this physical address.

[0113] Before starting to use the NAR table of any source block corresponding to this SBLK, the memory controller 110 (e.g., microprocessor 112) can clear all NAR information entries in the plurality of NAR information entries of the NAR table of this source block, specifically, setting each of the plurality of NAR information entries to a preset value such as zero (e.g., Need_AER = 0). During the first GC phase, when entering step S13B due to unsuccessful reading of valid data for a physical page in this SBLK, the memory controller 110 (e.g., microprocessor 112) can change a NAR information entry corresponding to this physical page (e.g., the NAR information entry corresponding to the PPA of this physical page) to the first predetermined value such as one (e.g., Need_AER = 1). In the second GC phase, when entering step S19A due to successful reading of valid data for this physical page in this SBLK, the memory controller 110 (e.g., microprocessor 112) can change this NAR information entry back to the preset value such as zero (e.g., Need_AER = 0). For the sake of simplicity, similar content will not be repeated in this embodiment.

[0114] According to some embodiments, when the at least one source block contains only the first source block such as SBLK#0, the memory controller 110 (e.g., microprocessor 112) may only use the SBLK#0 NAR table STBL(0) and does not need to use the SBLK#1 NAR table STBL(1), etc., but the present invention is not limited thereto. For example, the memory controller 110 (e.g., microprocessor 112) may only create the SBLK#0 NAR table STBL(0) and does not need to create the SBLK#1 NAR table STBL(1), etc. For the sake of simplicity, similar content in these embodiments will not be repeated here.

[0115] Figure 6 An embodiment of the present invention is illustrated based on, as follows Figure 5 The source block NAR control scheme shown contains certain NAR information entries. The SBLK#0 NAR table STBL(0) can be used as an example of any of the aforementioned source block NAR tables. During the first GC phase, when step S13B is entered due to unsuccessful reading of valid data from any physical page among the multiple PPAs {132,134,1132,1133} within the source block such as SBLK#0, the memory controller 110 (e.g., microprocessor 112) can change the NAR information entry corresponding to this physical page (e.g., the NAR information entry corresponding to one of the multiple PPAs {132,134,1132,1133}) to a first predetermined value such as one (e.g., Need_AER = 1). For simplicity, similar content will not be repeated here in this embodiment.

[0116] Figure 7 An embodiment of the present invention is illustrated as follows: Figure 2A as well as Figure 2BThe method illustrated employs a write-plus-multi-stage GC control scheme. As described above, the first GC stage can be performed in the background while the memory controller 110 writes data from the host device 50 to the NV memory 120 in response to at least one host instruction. For example, the host device 50 may have a sustained write behavior (labeled "write" for simplicity, where a downward arrow may represent a write request and / or write operation) to allow the memory device 100 to perform certain other operations. The memory controller 110 (e.g., microprocessor 112) can utilize this multi-stage GC management to control access to the memory device 100 to prevent data corruption and further prevent any delays in the at least one host-triggered operation. For example, by performing up to a predetermined number of GC operations, such as ten GC operations (denoted as "10GC" for simplicity), during an idle phase following a writing phase in any of a plurality of sustained write cycles (e.g., the cycles indicated by the rectangles drawn with dashed lines), the memory controller 110 (e.g., the microprocessor 112) can prevent any delay in host-triggered write operations. For the sake of simplicity, similar descriptions are not repeated here in this embodiment.

[0117] Figure 8 An improvement in input / output per second (IOPS) is illustrated according to an embodiment of the present invention. The memory controller 110 (e.g., microprocessor 112) can be as follows: Figure 7 The diagram illustrates that up to a predetermined number of GC operations, such as ten GC operations, are performed during the idle phase of any of the multiple continuous write cycles without delaying any host-triggered write operations. Compared to a single-stage GC control scheme that does not rely on this multi-stage GC management, a memory controller 110 (e.g., microprocessor 112) operating according to this method (e.g., the multi-stage GC control scheme) can maintain a larger average write IOPS relative to time (denoted as "t" for simplicity) and prevent write IOPS from dropping to zero. For example, a curve drawn with a thick line corresponds to the single-stage GC control scheme and indicates that write IOPS sometimes drops to zero, while a curve drawn with a thin line corresponds to the multi-stage GC control scheme and indicates that the average write IOPS is larger than the average of the single-stage GC control scheme and does not drop to zero. For simplicity, similar descriptions are not repeated here in this embodiment.

[0118] According to some embodiments, a test preparation procedure of the method may include certain additional steps for... Figure 2AThis test preparation process is performed before step S10 and can be used to test whether the memory device 100 (e.g., the memory controller 110 therein) is correctly implemented to operate according to the method. This test preparation process can be inserted before step S10 without altering the method. Figure 2A as well as Figure 2B The original steps shown include steps S10, S11, etc., and related local workflows (e.g., loops) that contain these original steps. In this test preparation procedure, the memory controller 110 (e.g., microprocessor 112) can perform the following operations:

[0119] (1) In a period of time before the start of the first GC phase, in response to a set of host instructions (e.g., host write instructions) among multiple host instructions, the memory controller 110 (e.g., microprocessor 112) can send the data carried by the set of host instructions to the NV memory 120 for programming into the multiple data blocks, wherein the amount of data is large enough to trigger the GC program.

[0120] (2) During the time period prior to the start of the first GC phase, in response to multiple first host instructions (e.g., host read instructions) among multiple host instructions, the memory controller 110 (e.g., microprocessor 112) may send multiple first read instructions, such as a large number of simple read instructions, to the NV memory 120 to attempt to read first data multiple times from at least one page of a first block (e.g., the source block such as SBLK#0) among the multiple blocks, wherein for each of the multiple reads except the last one, reading the first data from the at least one page of the first block is successful, and for the last of the multiple reads, reading the first data from the at least one page of the first block is unsuccessful; and

[0121] (3) During the time period before the start time of the first GC phase, in response to the failure to read the first data from the at least one page of the first block, the memory controller 110 (e.g., microprocessor 112) may send at least one second read instruction, such as one or more advanced read instructions, to the NV memory 120 to retry reading the first data from the at least one page of the first block.

[0122] The first data in the at least one page of the first block may have become corrupted, for example, due to a certain effect (e.g., read interference) of the read operation corresponding to the plurality of first read instructions, but the present invention is not limited thereto.

[0123] Following this test preparation procedure, based on Figure 2A as well as Figure 2BThe original steps shown, such as steps S10 and S11, can be further performed by the memory controller 110 (e.g., microprocessor 112) as follows:

[0124] (1) During the first GC phase, when step S11 is entered at the first time point, the memory controller 110 (e.g., microprocessor 112) may send the first simple read instruction to the NV memory 120 to attempt to read the first valid data from the source block (e.g., the source block such as SBLK#0), and in particular, successfully read the first valid data from at least one first page of the source block (e.g., the source block such as SBLK#0); (2) During the first GC phase, when steps S12 and S13A are subsequently entered, the memory controller 110 may send the first valid data to the internal buffer 120B of the NV memory 120 for programming into the destination block, wherein the first block is used as the source block (e.g., the source block such as SBLK#0), and the at least one first page of the source block is different from the at least one page of the first block;

[0125] (3) During the first GC phase, when step S11 is entered at the second time point, the memory controller 110 may send the second simple read instruction to the NV memory 120 to attempt to read the second valid data (e.g., the first data that may have become corrupted) from the source block (e.g., the source block such as SBLK#0).

[0126] (4) During the first GC phase, when steps S12 and S13B are subsequently entered, if reading the second valid data (e.g., the first data that may have become corrupted) from the source block fails, the memory controller 110 may prevent retrying to read the second valid data (e.g., the first data mentioned above) from the source block, and wait for further processing during the second GC phase following the first GC phase; and (5) During the time period between the end of the first GC phase and the start of the second GC phase, when re-entering step S16 to wait for the opportunity to start the second GC phase, the memory controller 110 (e.g., the microprocessor 112) may read the first valid data from the destination block and attempt to read the second valid data (e.g., the first data that may have become corrupted) from the source block, in response to at least one other host instruction among a plurality of host instructions; however, the invention is not limited thereto. Furthermore, for this multi-stage GC management, retrying to read the second valid data (e.g., the first data that may have become corrupted) from the source block may be postponed to the second GC phase. In this way, the operation of reading the first valid data and the operation of attempting to read the second valid data (e.g., the first data mentioned above) are performed on different blocks, such as the destination block and the source block, respectively. This indicates that the memory device 100 (e.g., the memory controller 110 therein) has been correctly implemented to operate according to this method. For the sake of simplicity, similar content in these embodiments will not be repeated here.

[0127] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

Claims

1. A method for access control of a memory device using a multi-stage waste collection management system, the method being a controller applicable to the memory device, the memory device including the controller and a non-volatile memory, the non-volatile memory including at least one non-volatile memory element, the at least one non-volatile memory element including a plurality of blocks, the method comprising: During a first garbage collection phase, a first simple read instruction is sent to the non-volatile memory to attempt to read a first valid data from a first source block among the plurality of blocks; During the first garbage collection phase, in response to the successful reading of the first valid data from the first source block, the first valid data is sent to an internal buffer of the non-volatile memory for programming into a first destination block among the plurality of blocks; During the first garbage collection phase, a second simple read instruction is sent to the non-volatile memory to attempt to read a second valid data from the first source block; During the first garbage collection phase, in response to the failure to read the second valid data from the first source block, re-attempting to read the second valid data from the first source block is prevented, wherein preventing re-attempting to read the second valid data from the first source block further includes: Prevent sending any of the at least one advanced read instruction for rereading the second valid data to the non-volatile memory; Among them, the multiple simple read instructions include the first simple read instruction and the second simple read instruction, and any advanced read instruction and any simple read instruction among the multiple simple read instructions belong to different types of read instructions; During a time period between an end point of the first garbage collection phase and the start point of a second garbage collection phase following the first garbage collection phase, at least one host trigger operation is completed, wherein the controller performs the at least one host trigger operation in response to at least one of a plurality of host commands from a host device; and During the second garbage collection phase, an attempt is made to reread the second valid data from the first source block.

2. The method of claim 1, wherein, The "any advanced read instruction" refers to any read instruction among the various types of read instructions that causes more read processing time in the non-volatile memory than the "any simple read instruction".

3. The method of claim 1, wherein, During this second garbage collection phase, the re-attempt to read the second valid data from the first source block includes: Send the at least one advanced read instruction to the non-volatile memory to attempt to read the second valid data from the first source block, wherein the plurality of simple read instructions include the first simple read instruction and the second simple read instruction; the at least one advanced read instruction and any of the plurality of simple read instructions belong to different types of read instructions.

4. The method of claim 3, wherein, The at least one advanced read instruction is one of at least one read instruction among a variety of read instructions that causes more read processing time to the non-volatile memory than any simple read instruction.

5. The method of claim 1, wherein, Also includes: During the first garbage collection phase, in response to the failure to read the second valid data from the first source block, a third simple read instruction is sent to the non-volatile memory to attempt to read a third valid data from the first source block; as well as During the first garbage collection phase, in response to the successful reading of the third valid data from the first source block, the third valid data is sent to the internal buffer of the non-volatile memory for programming into the first destination block.

6. The method of claim 1, wherein, The first garbage collection phase is performed in the background while the controller is writing data from the host device to the non-volatile memory in response to the at least one host instruction.

7. The method of claim 6, wherein, The second garbage collection phase is performed when the memory device does not write any data in response to any host instruction from the host device.

8. A controller for a memory device, the memory device including the controller and a non-volatile memory, the non-volatile memory including at least one non-volatile memory element, the at least one non-volatile memory element including a plurality of blocks, the controller including: A processing circuit is used to control the controller according to a plurality of host instructions from a host device, so as to allow the host device to access the non-volatile memory through the controller. in: During a first garbage collection phase, the controller sends a first simple read instruction to the non-volatile memory to attempt to read a first valid data from a first source block among the plurality of blocks; During the first garbage collection phase, in response to the successful reading of the first valid data from the first source block, the controller sends the first valid data to an internal buffer of the non-volatile memory for programming into a first destination block among the plurality of blocks; During the first garbage collection phase, the controller sends a second simple read instruction to the non-volatile memory to attempt to read a second valid data from the first source block; During the first garbage collection phase, in response to an unsuccessful attempt to read the second valid data from the first source block, the controller prevents a re-attempt to read the second valid data from the first source block, wherein preventing a re-attempt to read the second valid data from the first source block further includes: Prevent sending any of the at least one advanced read instruction for rereading the second valid data to the non-volatile memory; Among them, the multiple simple read instructions include the first simple read instruction and the second simple read instruction, and any advanced read instruction and any simple read instruction among the multiple simple read instructions belong to different types of read instructions; During a time period between an end point of the first garbage collection phase and the start point of a second garbage collection phase following the first garbage collection phase, the controller completes at least one host trigger operation, wherein the controller performs the at least one host trigger operation in response to at least one of a plurality of host commands from the host device; and During the second garbage collection phase, the controller re-attempts to read the second valid data from the first source block.

9. A memory device comprising the controller as claimed in claim 8, wherein the memory device comprises: This non-volatile memory is used to store information; and The controller is coupled to the non-volatile memory and is used to control the operation of the memory device.

10. A method for access control of a memory device using a multi-stage waste collection management system, the method being a controller applicable to the memory device, the memory device including the controller and a non-volatile memory, the non-volatile memory including at least one non-volatile memory element, the at least one non-volatile memory element including a plurality of blocks, the method comprising: During a period of time prior to the start of a first garbage collection phase, in response to a plurality of first host instructions from a plurality of host instructions from a host device, a plurality of first read instructions are sent to the non-volatile memory to attempt to read a first data multiple times from at least one page of a first block of the plurality of blocks, wherein for each of the plurality of reads except the last one, reading the first data from the at least one page of the first block is successful, and for the last of the plurality of reads, reading the first data from the at least one page of the first block is unsuccessful; During the time period prior to the start time of the first garbage collection phase, in response to the failure to read the first data from the at least one page of the first block, at least one second read instruction is sent to the non-volatile memory to retry reading the first data from the at least one page of the first block; During the first garbage collection phase, a first valid data is read from at least a first page of a first source block and the first valid data is sent to an internal buffer of the non-volatile memory for programming into a first destination block of the plurality of blocks, wherein the first block is used as the first source block and the at least one first page of the first source block is different from the at least one page of the first block. During the first garbage collection phase, an attempt is made to read the first data from the first source block, and in response to the failure to read the first data from the first source block, a re-attempt to read the first data from the first source block is prevented, so that further processing can wait during a second garbage collection phase following the first garbage collection phase; as well as During a period of time between the end of the first garbage collection phase and the start of the second garbage collection phase, in response to at least one other host instruction among the plurality of host instructions, the first valid data is read from the destination block and an attempt is made to read the first data from the first source block.

11. The method of claim 10, wherein, The at least one second read instruction and any one of the plurality of first read instructions belong to different types of read instructions.

12. The method of claim 11, wherein, The plurality of first read instructions represent a plurality of simple read instructions, while the at least one second read instruction represents at least one advanced read instruction.

13. The method as described in claim 12, characterized in that, The at least one advanced read instruction represents at least one read instruction among a plurality of read instructions that causes more read processing time to the non-volatile memory than any of the plurality of simple read instructions.

14. The method as described in claim 10, characterized in that, The attempt to reread the first data from the first source block is postponed to the second garbage collection phase.

15. The method as described in claim 10, characterized in that, Reading the first valid data from the at least one first page of the first source block also includes: Send at least one third read instruction to the non-volatile memory to attempt to read the first valid data from the at least one first page of the first source block, wherein reading the first valid data from the at least one first page of the first source block is successful.

16. The method as described in claim 15, characterized in that, The attempt to read the first data from the first source block also includes: A fourth read instruction is sent to the non-volatile memory to attempt to read the first data from the first source block.

17. The method as described in claim 15, characterized in that, The at least one second read instruction and any one of the plurality of first read instructions belong to different types of read instructions; and the at least one third read instruction belongs to the same type of read instruction as any one of the first read instructions.

18. A controller for a memory device, the memory device including the controller and a non-volatile memory, the non-volatile memory including at least one non-volatile memory element, the at least one non-volatile memory element including a plurality of blocks, the controller including: A processing circuit is used to control the controller according to a plurality of host instructions from a host device, so as to allow the host device to access the non-volatile memory through the controller. in: During a period of time prior to the start of a first garbage collection phase, in response to a plurality of first host instructions from the host device, the controller sends a plurality of first read instructions to the non-volatile memory to attempt to read a first data multiple times from at least one page of a first block of the plurality of blocks, wherein for each of the multiple reads except the last one, reading the first data from the at least one page of the first block is successful, and for the last of the multiple reads, reading the first data from the at least one page of the first block is unsuccessful; During the time period prior to the start time of the first garbage collection phase, in response to the failure to read the first data from the at least one page of the first block, the controller sends at least one second read instruction to the non-volatile memory to retry reading the first data from the at least one page of the first block; During the first garbage collection phase, the controller reads a first valid data from at least a first page of a first source block and sends the first valid data to an internal buffer of the non-volatile memory for programming into a first destination block of the plurality of blocks, wherein the first block is used as the first source block and the at least one first page of the first source block is different from the at least one page of the first block. During the first garbage collection phase, the controller attempts to read the first data from the first source block, and in response to the failure to read the first data from the first source block, prevents a re-attempt to read the first data from the first source block, in order to wait for further processing during a second garbage collection phase following the first garbage collection phase; as well as During a period of time between the end of the first garbage collection phase and the start of the second garbage collection phase, in response to at least one other host instruction among the plurality of host instructions, the controller reads the first valid data from the destination block and attempts to read the first data from the first source block.

19. A memory device comprising the controller of claim 18, wherein the memory device comprises: This non-volatile memory is used to store information; and The controller is coupled to the non-volatile memory and is used to control the operation of the memory device.

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