A network-on-chip system mapping method based on attention mechanism

Abstract

The application discloses a network-on-chip system mapping method based on an attention mechanism, which combines the attention mechanism and the connection relationship between nodes in a to-be-mapped task graph in a mapping model, forms a local attention mechanism depending on the connection relationship between nodes to avoid the introduction of unnecessary information interference in the coding of node information in the node coding stage of the mapping model, and uses the attention value between the nearest mapping node and the to-be-mapped node as the mapping probability value of the to-be-mapped node in the decoding stage of the mapping model. In the training model, polynomial sampling decoding is used to enhance the diversity of the mapping result of the model, and in the test model, the to-be-mapped node with the maximum probability is selected by using the greedy decoding method to obtain the optimal to-be-mapped node. A mapping effect evaluation model is introduced as a baseline to perform unsupervised training on the mapping model by using a reinforcement learning method. The network-on-chip mapping method based on the attention mechanism has the advantages that the same NoC architecture can be used for model training, and the same kind of to-be-mapped problem can be quickly and efficiently solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of Network on chip (NoC), in particular to a Network on chip system mapping method based on attention mechanism. BACKGROUND

[0002] Compared with bus architecture System on Chip (SoC) technology, the technical advantages of NoC mainly include: (1) NoC based on network topology can realize parallel communication of multiple tasks, greatly increasing the communication bandwidth of the system on chip. And the NoC network structure also makes the system on chip address space unrestricted, improving the scalability of the circuit. (2) NoC adopts a global asynchronous-local synchronous (GALS) communication mechanism to avoid the generation of a large clock tree, effectively solving the problem of SoC clock asynchronization, and also reducing the power consumption of the clock network. (3) NoC completely separates the two behaviors of computing and communication, expands the system from only reusing computing units to simultaneously reusing computing and communication units, greatly enhances the reusability of the system, and is beneficial to shorten the design time and reduce the development cost.

[0003] The mapping scheme determines the location of the task on the NoC platform, so the optimization of the mapping algorithm is an important means to realize low power consumption and low delay of NoC. However, the NoC mapping problem is an NP difficult problem. For a small scale Network on chip, the exhaustive traversal method can find the optimal scheme in a short time, but for a large scale NoC system, the traversal method will be very time-consuming. Based on the above background, the mapping problem has attracted great attention and attention from many domestic and foreign research institutions, and corresponding mapping schemes have been proposed, and ideal results have been achieved. However, these methods still have many shortcomings in terms of computational complexity and optimization effect, so how to efficiently obtain a low-power and low-delay Network on chip mapping scheme has important research value. SUMMARY

[0004] In view of the above problems, the present application provides a Network on chip system mapping method based on attention mechanism, which improves the action range of the attention mechanism and retains the parallel operation of the attention mechanism, and has the characteristics of efficient calculation. The attention mechanism is applied to the field of Network on chip system mapping. When decoding the encoder encoding result combined with the mapped node, different decoding strategies are adopted according to the model training and model testing conditions, so that the mapping model is exploratory during training, and the optimal node is selected as the next mapping node according to the existing conditions during model testing. The present application comprises:

[0005] Step 1, obtain the adjacency matrix of the task graph to be mapped and do the minimum-maximum normalization, and take the normalized task graph adjacency matrix as the input of the mapping model and the mapping effect evaluation model.

[0006] Step 2, the mapping model encoder takes each row of the normalized task graph adjacency matrix as the original information of the nodes in the task graph, obtains the connection relationship of each node according to the adjacency matrix as the Mask matrix of attention operation, and performs attention operation between nodes to obtain the encoding expression of each node in the task graph.

[0007] Step 3, input the encoding of each node in the task graph obtained by the encoder into the decoder, and the decoder takes the encoding expression of the last three mapped nodes as the Query vector and the encoding expression of the unmapped node as the Key vector to perform attention operation, and performs Softmax normalization processing on the obtained attention value to obtain the probability value of each unmapped node as the next mapping.

[0008] Step 4, during training, the decoder realizes sampling according to the probability value in a polynomial sampling manner, and each unmapped node is extracted according to the mapping probability value, so that each unmapped node has the possibility of being extracted as the next mapping node, thereby realizing the exploration effect during model training, and during testing, the decoder extracts the unmapped node with the maximum probability value as the next mapping node in a greedy sampling manner, thereby realizing the best effect during model testing.

[0009] Step 5, repeat step 4 until the mapping is completed, and the mapping solution sequence can be obtained That is, the arrangement of numbers from 1 to n, where the index represents the routing node on the architecture, and the element represents the IP core in the task graph. Calculate the communication delay of the solution sequence as the mapping result.

[0010] Step 6, the mapping effect evaluation model is composed of a fully connected neural network, which estimates the communication delay of the task graph to be mapped.

[0011] Step 7, take the communication delay calculated by the on-chip network mapping model solution sequence as the actual system communication delay L(π), and take the system communication delay estimated by the mapping effect evaluation model as the baseline b(s), and optimize the on-chip network mapping model by gradient descent, as follows:

[0012]

[0013] Where L(θ|s)=E pθ(π|s) [L(π)], L((θ|s) is the expected value of the communication delay of the task graph to be mapped.

[0014] Step 8: The system communication delay L(pi) calculated by the on-chip network mapping model is taken as the actual value, the system communication delay b(s) estimated by the mapping effect evaluation model is taken as the predicted value, and the mapping effect evaluation model is optimized by taking the mean square error (MSE) as the loss function, as follows:

[0015] MSE(L(pi), b(s)) = (L(pi) - b(s)) 2 BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a system block diagram of the on-chip network system mapping method based on the attention mechanism of the present application;

[0017] Figure 2 is a task graph input and mapping sequence output schematic diagram of the on-chip network mapping model of the present application;

[0018] Figure 3 is an encoder part schematic diagram of the on-chip network mapping model of the present application;

[0019] Figure 4 is a decoder schematic diagram of the on-chip network mapping model in the training mode of the present application;

[0020] Figure 5 is a decoder schematic diagram of the on-chip network mapping model in the test mode of the present application;

[0021] Figure 6 is the mapping model test result of the same task graph using the local attention mechanism and not using the local attention mechanism as the encoder. DETAILED DESCRIPTION

[0022] The technical solutions in the specific embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application:

[0023] As shown in Figure 1 is a flowchart of the on-chip network system mapping method based on the attention mechanism, the mapping scheme is composed of a mapping model and a mapping effect evaluation model, the mapping model solves the task graph mapping sequence and calculates the actual communication delay of the sequence, the mapping effect evaluation model evaluates the communication delay of the specific task graph, and the mapping model is updated according to the actual communication delay and the evaluated communication delay.

[0024] As shown in Figure 2As shown, the task graph to be mapped containing four IP cores is mapped to a 2x2 Mesh architecture, and the solution sequence of the mapping model solution is m={C4, C1, C2, C3}, the meaning of the solution sequence is that IP core C4 is mounted to R1 router, IP core C1 is mounted to R2 router, IP core C2 is mounted to R3 router, and IP core C3 is mounted to R4 router, where the index represents the routing node on the architecture, and the element represents the IP core in the task graph, and the solving process is described in detail later.

[0025] The mapping model is composed of an encoder and a decoder, and the encoder flow chart of the mapping model is as shown in Figure 3 First, the adjacency matrix of the task graph to be mapped is subjected to minimum-maximum standardization, and the formula is:

[0026]

[0027] Where x' is the standardized value, x is the original value, x max is the maximum element value in the adjacency matrix, and x min is the minimum element value in the adjacency matrix.

[0028] The Mask matrix of the connection relationship between nodes is obtained according to the adjacency matrix, and the specific formula is as follows:

[0029]

[0030] The standardized adjacency matrix and the Mask matrix are taken as the input of the encoder, and the encoder does N-layer local multi-head attention mechanism on the input according to the Mask matrix, and the formula is as follows:

[0031] a i =f(Q,K i )·Mask,i∈{1…n}

[0032]

[0033]

[0034] The N-layer local multi-head attention is connected by a residual network and a feedforward fully connected layer, and the formulas are as follows:

[0035] Sub_layer_output=LayerNorm(x+SubLayer(x))

[0036] FFN(x)=max(0,xW1+b1)W2+b2

[0037] As shown in Figure 4As shown, the mapping model decoder takes the encoder output {En1, En2, En3, En4} of each node in the task graph as the decoder input, and splices the three nodes just mapped to obtain wherein l represents the number of decoder iterations, and q represents As the Query vector, if the number of mapped nodes is less than three, a learnable model placeholder vector h0 is introduced, As the Query vector, the unmapped nodes are taken as the Key vector to perform single-head attention operation. The value after Softmax calculation of the attention value is the probability value {p1, p2, p3, p4} of the unmapped nodes as the next mapping node. In decoding, the nodes are decoded by polynomial sampling according to the probability size. The node with a larger probability value has a greater probability of being extracted as the next mapping node. This time, the IP core C2 with the smallest probability value is extracted as the next mapping node. The polynomial sampling decoding makes each node possible to be extracted, realizing the diversity of the solution in model training.

[0038] Figure 5 For the mapping model decoder flowchart in testing, the encoder output {En1, En2, En3, En4} of each node in the task graph is taken as the input of the decoder, and the three mapped nodes are spliced to obtain wherein l represents the number of decoder iterations, and if the number of mapped nodes is less than three, a learnable model placeholder vector h0 is introduced, As the Query vector, the unmapped nodes are taken as the Key vector to perform single-head attention operation. The value after Softmx calculation of the attention value is the probability value {p1, p2, p3, p4} of the unmapped nodes as the next mapping node. Different from the training, the unmapped node IP core C1 with the largest probability value is selected as the next mapping node in decoding, so as to ensure that the model can obtain the optimal solution in testing.

[0039] In training, polynomial decoding as shown in Figure 5 is adopted until the complete mapping solution sequence is output. The normalized system latency of the solution sequence is calculated according to the mapping solution sequence, and the calculation formula is as follows:

[0040]

[0041] wherein w i,j represents the communication amount between the i node and the j node, hop i,j represents the communication hop number from the mapped node i to the node j, and c i is different for different task graphs. j Therefore, the communication amount w i,j is normalized, that is, the communication latency of the task graph is normalized with T normPositive correlation, T norm ≥1, T norm Representing the average communication hop number between any two nodes on the NoC architecture, and the ideal value is one.

[0042] In the test, the greedy decoding as shown in Figure 6 The mapping program ends here, and no subsequent model parameter update operation is required.

[0043] The mapping effect evaluation model is composed of a fully connected neural network, the communication delay calculated by the on-chip network mapping model sequence is taken as the actual system communication delay L(π), and the system communication delay estimated by the mapping effect evaluation model is taken as the baseline b(s). The on-chip network mapping model is optimized through gradient descent, and the formula is as follows:

[0044]

[0045] Where L(θ|s)=E pθ(π|s) [L(π)], L((θ|s) is the expected communication delay of the task graph to be mapped.

[0046] The system communication delay L(π) calculated by the on-chip network mapping model sequence is taken as the actual value, and the system communication delay b(s) estimated by the mapping effect evaluation model is taken as the predicted value. The mapping effect evaluation model is optimized through the mean square error (MSE) as the loss function, and the formula is as follows:

[0047] MSE(L(π),b(s))=(L(π)-b(s)) 2

[0048] Figure 6 The standardized system communication delay of the task graph mapping solution obtained by using the local attention mechanism as the encoder and not using the local attention mechanism as the encoder respectively is tested by the method, wherein the standardized system communication delay of the local attention mechanism mapping solution is 1.511, and the standardized system communication delay of the local attention mechanism mapping solution is 2.04. It can be seen that compared with not using the attention mechanism, the standardized system communication delay of the mapping solution is reduced by 25.93%, and the standardized system communication delay of the mapping solution is greatly reduced.

[0049] The above description of the application and its embodiments is illustrative and not restrictive, and the application can be practiced in other specific forms without departing from the spirit or essential character thereof. The drawings are intended to be illustrative, and not limiting, and any reference to a "figure" is to be understood as a reference to a drawing in which that figure is shown. Any reference to "embodiments" is to be understood as a reference to one or more embodiments. Any reference to "the figure" is to be understood as a reference to the figure in which that figure is shown. Any reference to "the drawing" is to be understood as a reference to the drawing as a whole, and any reference to "the figures" is to be understood as a reference to all of the drawings. Any reference to "the invention" is to be understood as a reference to the application as a whole, and any reference to "the invention" is to be understood as a reference to one or more embodiments of the application. Any reference to "the invention" is to be understood as a reference to the application as a whole, and any reference to "the invention" is to be understood as a reference to one or more embodiments of the application. Any reference to "the invention" is to be understood as a reference to the application as a whole, and any reference to "the invention" is to be understood as a reference to one or more embodiments of the application. Any reference to "

Claims

1. An on-chip network mapping method based on an improved attention mechanism, characterized in that, Includes the following steps: Step 1: Input the adjacency matrix of the task graph to be mapped and perform min-max normalization on the adjacency matrix. Use the normalized task graph adjacency matrix as the input to the mapping model and the mapping effect evaluation model. Step 2: The mapping model encoder uses each row of the normalized task graph adjacency matrix as the original information of the nodes in the task graph. Based on the adjacency matrix, the connection relationship of each node is obtained as the Mask matrix for attention operation. Attention operation is performed between each node to obtain the encoded representation of each node in the task graph. Step 3: Input the encoding of each node in the task graph obtained by the encoder into the decoder. The decoder uses the encoding of the three most recently mapped nodes as the Query vector and the encoding of the unmapped nodes as the Key vector to perform attention operation. The attention values ​​are then processed by Softmax normalization to obtain the probability value of each unmapped node as the next mapping. Step 4: During training, the decoder uses multinomial sampling to sample based on probability values. Each unmapped node is selected according to its mapping probability value, so that each unmapped node has a chance to be selected as the next mapped node. This achieves the exploration effect during model training. During testing, the decoder uses greedy sampling to select the unmapped node with the highest probability value as the next mapped node. This achieves the best effect during model testing. Step 5: Repeat step 4 until the mapping is complete to obtain the mapping solution sequence. That is, a sequence of numbers from 1 to n, where the index represents a routing node in the architecture and the element represents an IP core in the task graph. The communication latency of this solution sequence is calculated as the mapping result. Step 6: The mapping effect evaluation model is composed of a fully connected neural network to estimate the communication latency of the task graph to be mapped; Step 7: Use the communication delay calculated by the solution sequence of the on-chip network mapping model as the actual system communication delay L(π), and the system communication delay estimated by the mapping effect evaluation model as the baseline b(s). Optimize the on-chip network mapping model using gradient descent, as shown in the following formula: Where L(θ|s)=E pθ(π|s) [L(π)], L((θ|s) represents the expected communication delay of the task graph to be mapped; Step 8: Use the system communication delay L(π) calculated by the solution sequence of the on-chip network mapping model as the actual value, and the system communication delay b(s) estimated by the mapping effect evaluation model as the predicted value. Optimize the mapping effect evaluation model using the mean squared error (MSE) as the loss function, as shown in the following formula: MSE(L(π),b(s))=(L(π)-b(s)) 2 。 2. The on-chip network mapping method based on the improved attention mechanism according to claim 1, characterized in that, In step 1, the adjacency matrix of the task graph to be mapped is obtained and the adjacency matrix is ​​normalized by min-max. The normalized result is used as the input of the mapping model and the mapping effect evaluation model.

3. The on-chip network mapping method based on the improved attention mechanism according to claim 1, characterized in that, In step 2, a local attention mechanism is used based on the connection relationship between nodes in the task graph to be mapped to overcome the introduction of information from nodes without connection relationship by the global attention mechanism, making the encoder more efficient in encoding the information of each node.

4. The on-chip network mapping method based on the improved attention mechanism according to claim 1, characterized in that, In steps 3-5, when decoding the node information encoded by the encoder, different decoding methods are used in the model training and testing phases, so that the mapping model can exhibit exploratory behavior during training and output the best results during testing.

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