Chip layout 3D modeling methods, systems, storage media and electronic devices

Abstract

This invention discloses a method, system, storage medium, and electronic device for three-dimensional modeling of chip layouts. The method includes: determining a modeling area of ​​the chip layout; acquiring a first graphic and a second graphic located within the modeling area on the chip layout, wherein the first graphic covers the second graphic, the first graphic is used to define the etching shape, and the second graphic is used to define the deposition shape; determining a feature area that does not overlap with the first graphic in the modeling area; determining a reference plane in three-dimensional space; constructing a first block of a first thickness on the reference plane with the feature area as its base; constructing a second block of a second thickness on the reference plane with the second graphic as its base; and placing the second block on the reference plane according to the position of the second graphic within the modeling area to obtain a three-dimensional layout model. This invention solves the problem that two-dimensional layouts in the prior art cannot meet the requirements of three-dimensional scale analysis, and can convert two-dimensional layouts into three-dimensional models, facilitating intuitive three-dimensional scale analysis.

Description

Technical Field

[0001] This invention relates to the field of chip layout design, and in particular to a chip layout design. Figure 3 3D modeling methods, systems, storage media, and electronic devices. Background Technology

[0002] Chip layout is the basis for chip fabrication. For some chips, etching processes are used to create etched structures such as grooves on a plane, and deposition processes are used to create thin films on the same plane. Correspondingly, chip layout design requires drawing graphics representing the etching and deposition areas. However, since all graphics on a chip layout are drawn on a single plane, it is a two-dimensional layout. Two-dimensional layouts have low visualization capabilities, making it impossible to intuitively analyze at a three-dimensional scale to check the accuracy of the layout. The position of the etched and deposited structures in the horizontal and vertical directions must be subjectively judged by humans. If the two-dimensional layout could be converted into a three-dimensional model, more subjective three-dimensional analysis would be possible. However, currently, software available for drawing chip layouts does not support this function. Therefore, there is an urgent need to implement a function that can convert two-dimensional layouts into three-dimensional models. Summary of the Invention

[0003] The purpose of this invention is to provide a chip board. Figure 3 This invention relates to three-dimensional modeling methods, systems, storage media, and electronic devices to address the problem that two-dimensional layouts cannot meet the requirements of three-dimensional scale analysis in existing technologies. It can convert two-dimensional layouts into three-dimensional models, facilitating intuitive three-dimensional scale analysis.

[0004] To address the aforementioned technical problems, this invention provides a chip-based design. Figure 3 3D modeling methods include:

[0005] The modeling area of ​​the chip layout is determined, and a first graphic and a second graphic located within the modeling area on the chip layout are obtained. The first graphic covers the second graphic. The first graphic is used to define the etching shape, and the second graphic is used to define the deposition shape.

[0006] Determine the feature regions that do not overlap with the first graphic in the modeling region;

[0007] A reference plane is determined in three-dimensional space, and a first block of first thickness is constructed on the reference plane with the feature region as the bottom surface.

[0008] On the reference surface, a second block of second thickness is constructed with the second graphic as the bottom surface, and the second block is placed on the reference surface according to the position of the second graphic in the modeling area to obtain a three-dimensional layout model.

[0009] Preferably, the chip layout further includes a third graphic located within the modeling region that does not intersect with the first graphic, the third graphic being used to define the shape of the deposition, and the method further includes:

[0010] Obtain a third graphic located within the modeling area on the chip layout;

[0011] On the reference plane, a third block of third thickness is constructed with the third graphic as the bottom surface, and the third block is placed on the first block according to the position of the third graphic in the modeling area.

[0012] Preferably, the step of determining the feature region that does not overlap with the first graphic includes:

[0013] Perform a Boolean subtraction operation on the modeling region and the first graphic to obtain a feature region that does not overlap with the modeling region and the first graphic.

[0014] Preferably, the step of constructing a first patch of first thickness on the reference plane with the feature region as the bottom surface includes:

[0015] Construct a feature bottom surface on the reference plane that has the same shape as the feature region;

[0016] The feature bottom surface is geometrically stretched in a direction perpendicular to the reference plane according to a first thickness to obtain a first block.

[0017] Preferably, the method further includes:

[0018] Construct a foundation block of preset thickness on the reference plane with the modeling area as the bottom surface;

[0019] Align the bottom surface of the foundation block with the bottom surface of the first block, and place the first block on the foundation block.

[0020] Preferably, the step of constructing a foundation block of a predetermined thickness on the reference plane with the modeling area as the bottom surface includes:

[0021] Construct a base surface on the reference plane that has the same shape as the modeling area;

[0022] The foundation bottom surface is geometrically stretched in a direction perpendicular to the reference plane according to a preset thickness to obtain a foundation block.

[0023] Preferably, the method further includes:

[0024] Obtain three-dimensional coordinate parameters, which are used to define the sectional space;

[0025] A cross-sectional view block is constructed in the three-dimensional space based on the three-dimensional coordinate parameters;

[0026] Perform a Boolean subtraction operation on the 3D layout model and the sectional view block to obtain the non-overlapping parts of the 3D layout model and the sectional view block.

[0027] To address the aforementioned technical problems, the present invention also provides a chip-based version. Figure 3 3D modeling system, including:

[0028] The pattern acquisition module is used to determine the modeling area of ​​the chip layout and acquire a first pattern and a second pattern located within the modeling area on the chip layout. The first pattern covers the second pattern. The first pattern is used to define the etching shape, and the second pattern is used to define the deposition shape.

[0029] A graphic determination module is used to determine feature regions that do not overlap with the modeling region and the first graphic.

[0030] The first construction module is used to determine a reference plane in three-dimensional space and construct a first block of a first thickness on the reference plane with the feature region as the bottom surface;

[0031] The second construction module is used to construct a second block of a second thickness on the reference surface with the second graphic as the bottom surface, and to place the second block on the reference surface according to the position of the second graphic in the modeling area to obtain a three-dimensional layout model.

[0032] To address the aforementioned technical problems, the present invention also provides a storage medium storing a computer program, the computer program being configured to execute the chip board described in any of the preceding claims when running. Figure 3 3D modeling methods.

[0033] To address the aforementioned technical problems, the present invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the chip board described in any of the preceding claims. Figure 3 3D modeling methods.

[0034] Unlike existing technologies, the chip board provided by this invention... Figure 3 The 3D modeling method obtains the first and second graphics located within the modeling area on the chip layout, then determines the feature areas that do not overlap with the first graphics. First, a first block is constructed on a reference plane in 3D space with the feature areas as the base, and then a second block is constructed with the second graphics as the base. Based on the position of the second graphics within the modeling area, the second block is placed on the reference plane to obtain a 3D layout model. This allows the 2D layout to be converted into a 3D model, facilitating intuitive 3D scale analysis.

[0035] The chip version provided by this invention Figure 3 3D modeling systems, storage media and electronic devices, and chip boards Figure 3 The 3D modeling methods belong to the same inventive concept and therefore have the same beneficial effects, which will not be elaborated here. Attached Figure Description

[0036] Figure 1 Chip board provided for embodiments of the present invention Figure 3 A flowchart illustrating the 3D modeling method.

[0037] Figure 2 This is a schematic diagram showing the positional relationship between the modeled area on the chip layout and the first and second graphics.

[0038] Figure 3 This is a schematic diagram of the first block constructed on the reference plane.

[0039] Figure 4 This is a schematic diagram showing the positional relationship between the second and third tiles and the first tile in three-dimensional space.

[0040] Figure 5 for Figure 1 The diagram shows the specific process flow of step S3 in the 3D modeling method.

[0041] Figure 6 This is a schematic diagram of the feature base surface constructed on the reference plane.

[0042] Figure 7 In order to be in Figure 1 The flowchart shown is a schematic diagram of the process after step S4 or step S6 in the 3D modeling method.

[0043] Figure 8 This is a schematic diagram showing the positional relationship between the foundation block constructed on the reference plane and the first block.

[0044] Figure 9 In order to be in Figure 7 The diagram shows the specific process flow of step S7 in the 3D modeling method.

[0045] Figure 10 Chip board provided for another embodiment of the present invention Figure 3 A flowchart illustrating the 3D modeling method.

[0046] Figure 11 This is a schematic diagram showing the positional relationship between the 3D layout model and the sectional view blocks.

[0047] Figure 12 This is a schematic diagram of the result of performing a Boolean subtraction operation between a 3D layout model and a sectional view block.

[0048] Figure 13Chip board provided for yet another embodiment of the present invention Figure 3 A schematic diagram of the 3D modeling system. Detailed Implementation

[0049] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0050] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0052] Please refer to Figure 1 This invention provides a chip-based version. Figure 3 3D modeling method, which includes the following steps:

[0053] S1: Determine the modeling area of ​​the chip layout and obtain the first and second graphics located within the modeling area on the chip layout. The first graphic covers the second graphic. The first graphic is used to define the shape of the etching, and the second graphic is used to define the shape of the deposition.

[0054] The modeling area refers to the region where the modeling is performed. This area can be the entire chip layout or a portion thereof. Considering that the chip layout is typically drawn on a rectangular interface, the preferred shape for the modeling area is rectangular.

[0055] The modeling area can be determined based on user operations. For example, if the user inputs the coordinates of four vertices, the four vertices are connected sequentially to form a rectangle, and the area enclosed by the rectangle is the modeling area. Alternatively, the user can manually select two vertices on the chip layout, and these two vertices are used as diagonal vertices to form a rectangle, and the area enclosed by the rectangle is the modeling area. Or, the user can perform a selection operation on the chip layout, and a rectangle is formed based on the selection operation, and the area enclosed by the rectangle is the modeling area.

[0056] Regardless of how the modeling area is defined, it is essential to ensure that the first pattern is located within that area. The first pattern represents the shape of the etching, that is, the shape of the etched portion on the chip. Although it is a specific pattern on the chip layout, it corresponds to an etched structure on the chip. The second pattern represents the shape of the deposition, indicating the deposition structure, such as a thin film, that needs to be formed on the chip through deposition processes. Furthermore, the etching process of the first pattern precedes the deposition process of the second pattern.

[0057] like Figure 2 As shown in the figure, the rectangular box BOX represents the modeling area, graphic A represents the first graphic, and graphic B represents the second graphic. The first graphic A covers the second graphic B, and both are located within the modeling area BOX.

[0058] S2: Determine the feature regions that do not overlap with the first graphic.

[0059] The modeling area is part of the chip layout and is also a graphic. The first graphic is within the modeling area; therefore, there are overlapping and non-overlapping parts. The feature area is the non-overlapping part. In other words, the feature area is a graphic with a hollow center. Figure 2 As shown in the figure, the shaded areas represent the feature regions.

[0060] In this embodiment, the feature region can be determined using Boolean operations. Specifically, the step of determining the feature region where the modeling region and the first graphic do not overlap is as follows: perform a Boolean subtraction operation on the modeling region and the first graphic to obtain the feature region where the modeling region and the first graphic do not overlap. Boolean operations are logical operations in the computer field, including logically Boolean AND, AND, and NOT operations. In computer geometry, they represent set AND, OR, and NOT operations between polygons or polyhedra. The Boolean subtraction operation calculates the difference between two graphics and is a Boolean NOT operation.

[0061] S3: Determine the reference plane in three-dimensional space, and construct the first block of the first thickness on the reference plane with the feature region as the bottom surface.

[0062] In this context, the 3D space is a 3D display interface, and the reference plane is a plane within that space. This plane can be the plane containing the XY coordinate axes, the XZ coordinate axes, or the YZ coordinate axes in a 3D coordinate system, or it can be a custom plane. After creating or calling the 3D space, a reference plane needs to be defined. The first block constructed on the reference plane is a structure with parallel top and bottom surfaces and a height equal to a first thickness. The first thickness is a user-defined or default modeling thickness.

[0063] The top and bottom surfaces of the first etched block have the same shape as the feature area. Because the feature area is hollowed out in the middle, the center of the etched block is also hollow, consistent with the physical structure of the actual chip. For example... Figure 3 As shown, the three-dimensional structure D1 in the figure represents the first block. The first block D1 is constructed on the XY plane. The top view shape of the first block D1 is the same as the modeling area, and the height is the first thickness h1. The first block D1 intuitively shows the three-dimensional structure after etching.

[0064] S4: Construct a second block of second thickness on the reference plane with the second graphic as the bottom surface, and place the second block on the reference plane according to the position of the second graphic in the modeling area to obtain the three-dimensional layout model.

[0065] The second block constructed on the reference plane is a structure with parallel top and bottom surfaces and a height equal to the second thickness. The second thickness is a user-defined or default modeling thickness. Since the first graphic covers the second graphic, the second block is located within the hollow area of ​​the first block. Corresponding to the actual physical structure of the chip, the second block cannot be suspended; therefore, it is placed on the reference plane within the hollow area of ​​the first block. For example... Figure 4 As shown, the three-dimensional structure D2 in the figure represents the second block. The top view shape of the second block D2 is the same as that of the second graphic. The height of the second block D2 is the second thickness h2. The second block D2 intuitively shows the three-dimensional structure after the deposition process.

[0066] Through the above methods, the chip version of this embodiment of the invention... Figure 3 The 3D modeling method transforms the etched and deposited shapes from two-dimensional planar graphics into three-dimensional solid graphics, intuitively displaying the three-dimensional structure after etching and deposition. This invention enables the conversion of two-dimensional plans into three-dimensional models, facilitating intuitive three-dimensional scale analysis. Furthermore, instead of directly creating a three-dimensional solid model of the modeling area and then hollowing it out, this invention first determines the region after removing the first graphic as the bottom surface, and then geometrically stretches the bottom surface to obtain a hollow three-dimensional solid graphic. This significantly reduces computational resources and improves the performance of the three-dimensional view.

[0067] In some embodiments of this application, please refer again to Figure 1 The chip layout also includes a third pattern located within the modeling region that does not intersect with the first pattern. This third pattern defines the shape of the deposition. The deposition process of the third pattern follows the deposition process of the second pattern. Figure 3 3D modeling methods also include:

[0068] S5: Get the third graphic located within the modeling area on the chip layout.

[0069] When determining the modeling area, it is necessary to ensure that the first and third patterns are located within the modeling area. The third pattern represents the shape of the deposition, indicating the deposition structure, such as a thin film, that needs to be formed on the chip through the deposition process. Figure 3 As shown, the modeling area BOX also contains a third graphic C, which is adjacent to the first graphic A, but they do not overlap.

[0070] S6: Construct a third block with a third thickness on the reference plane with the third graphic as the bottom surface, and place the third block on the first block according to the position of the third graphic in the modeling area.

[0071] The third block is a structure with parallel top and bottom surfaces and a height equal to the third thickness. The shapes of the top and bottom surfaces of the third block are the same as those of the third graphic. The third thickness is a user-defined or default modeling thickness.

[0072] The third graphic is located outside the feature region; therefore, the third graphic block precisely avoids the hollow area of ​​the first graphic block. Corresponding to the actual physical structure of the chip, the third graphic block is placed on the first graphic block, as shown below. Figure 4 As shown, the three-dimensional structure D3 in the figure represents the third block. The third block D3 avoids the hollow area (that is, the etched area) of the first block D1 and is located on the first block D1. The top view shape of the third block D3 is the same as that of the third figure. The height of the third block D3 is the third thickness h3. The third block D3 intuitively shows the three-dimensional structure after the deposition process.

[0073] In some embodiments of this application, please refer to Figure 5 The step of constructing a first patch of first thickness on the reference plane with the feature region as the bottom surface, i.e., step S3, includes:

[0074] S31: Construct a feature base surface on the reference plane that has the same shape as the feature region.

[0075] The feature base has the same shape as the feature region, and it is also a two-dimensional planar graphic. The difference is that the feature base is constructed in three-dimensional space. For example... Figure 6 As shown, a feature base U1 is constructed on the XY plane of the three-dimensional spatial coordinate system XYZ.

[0076] S32: Geometrically stretch the feature bottom surface in the direction perpendicular to the reference plane according to the first thickness to obtain the first block.

[0077] The feature base is composed of many points. Geometric stretching of each point transforms it into a line, with the line length being the first thickness. The transformed lines from each point constitute the first tile. For example... Figure 3 As shown, after geometrically stretching the feature bottom surface U1, the first block D1 is obtained. The shapes of the upper and lower surfaces of the first block D1 are the same as those of the feature bottom surface U1, and the height of the first block D1 is the first thickness h1.

[0078] In some embodiments of this application, please refer to Figure 7 After step S4 or step S6 mentioned above, the chip board Figure 3 3D modeling methods also include:

[0079] S7: Construct a foundation block of preset thickness on the reference plane with the modeling area as the bottom surface.

[0080] S8: Align the bottom surface of the foundation block with the bottom surface of the first block, and place the first block on the foundation block.

[0081] Since chip layouts typically don't depict the chip substrate, but in reality, device structures are formed on a substrate, this embodiment constructs a ground plane block to represent the substrate for a more realistic display of the device structure. The ground plane block is a structure with parallel upper and lower surfaces and a height of a preset thickness; the shapes of both the upper and lower surfaces are identical to the modeling area. For example... Figure 8 As shown in the figure, the three-dimensional structure F represents the foundation block. The thickness of the foundation block F is h. The first block D1 is placed on the foundation block F, and the two are aligned vertically and fit together.

[0082] For further details, please refer to... Figure 9 The step of constructing a foundation block of preset thickness on the reference plane with the modeling area as the bottom surface, namely step S7, includes:

[0083] S71: Construct a base surface on the reference plane that has the same shape as the modeling area.

[0084] S72: Geometrically stretch the foundation bottom surface in the direction perpendicular to the reference plane according to the preset thickness to obtain the foundation block.

[0085] The foundation block, like the first block mentioned above, is obtained through geometric stretching.

[0086] Please refer to Figure 10 Another embodiment of the present invention provides a chip board Figure 33D modeling method. The 3D modeling method in this embodiment is based on the 3D modeling method in the foregoing embodiments, and includes all the technical features of the 3D modeling method in the foregoing embodiments. The difference is that the 3D modeling method in this embodiment also includes the following steps:

[0087] S91: Obtain the three-dimensional coordinate parameters, which are used to define the section space.

[0088] The three-dimensional coordinate parameters can be obtained from external input data, such as the user inputting the three-dimensional coordinate information of multiple vertices, or the user selecting multiple points in three-dimensional space with the mouse, thereby determining the three-dimensional coordinate information of multiple points.

[0089] S92: Construct a section view block in three-dimensional space based on three-dimensional coordinate parameters.

[0090] The three-dimensional coordinate parameters define the sectional space. After the sectional view block is constructed, the sectional view block serves as the three-dimensional structure of the sectional space.

[0091] S93: Perform a Boolean subtraction operation on the 3D layout model and the section view block to obtain the non-overlapping parts of the 3D layout model and the section view block.

[0092] Boolean subtraction calculates the difference between two polyhedra, and is a Boolean NOT operation. Sectional view blocks allow for the inspection of the interior of a 3D model. For example... Figure 11 As shown, the block P drawn with a dashed line in the figure represents a sectional view block, and the upper surface of sectional view block P is on the same plane as the upper surface of the third block D3. Figure 12 As shown, after performing a Boolean subtraction operation between the sectional view block P and the 3D layout model, the part of the 3D layout model that does not overlap with the sectional view block is obtained.

[0093] Please refer to Figure 13 Another embodiment of the present invention provides a chip board Figure 3 3D modeling system. This system includes:

[0094] The pattern acquisition module 1 is used to determine the modeling area of ​​the chip layout and acquire a first pattern and a second pattern located within the modeling area on the chip layout. The first pattern covers the second pattern. The first pattern is used to define the etching shape, and the second pattern is used to define the deposition shape. The modeling area represents the modeling range; it can be the entire chip layout or a portion thereof. Considering that the chip layout is typically drawn on a rectangular interface, the shape of the modeling area is preferably rectangular.

[0095] The modeling area can be determined based on user operations. For example, if the user inputs the coordinates of four vertices, the four vertices are connected sequentially to form a rectangle, and the area enclosed by the rectangle is the modeling area. Alternatively, the user can manually select two vertices on the chip layout, and these two vertices are used as diagonal vertices to form a rectangle, and the area enclosed by the rectangle is the modeling area. Or, the user can perform a selection operation on the chip layout, and a rectangle is formed based on the selection operation, and the area enclosed by the rectangle is the modeling area.

[0096] Regardless of how the modeling area is defined, it is essential to ensure that the first pattern is located within that area. The first pattern represents the shape of the etching, that is, the shape of the etched portion on the chip. Although it is a specific pattern on the chip layout, it corresponds to an etched structure on the chip. The second pattern represents the shape of the deposition, indicating the deposition structure, such as a thin film, that needs to be formed on the chip through deposition processes. Furthermore, the etching process of the first pattern precedes the deposition process of the second pattern.

[0097] The graphic determination module 2 is used to determine the feature regions that do not overlap with the modeling area and the first graphic. The modeling area is part of the chip layout and is also a graphic. The first graphic is within the modeling area; therefore, there are overlapping and non-overlapping parts between them. The feature region is the non-overlapping part. In other words, the feature region is a graphic with a hollow center. Figure 2 As shown in the figure, the shaded areas represent the feature regions.

[0098] The first construction module 3 is used to determine a reference plane in three-dimensional space, and to construct a first block of a first thickness on the reference plane with the feature region as its base. Here, three-dimensional space is a 3D display interface, and the reference plane is a plane in three-dimensional space. This plane can be the plane containing the XY coordinate axes, the XZ coordinate axes, or the YZ coordinate axes in a three-dimensional coordinate system, or it can be a custom plane. After creating or calling the three-dimensional space, a reference plane needs to be determined. The first block constructed on the reference plane is a structure with parallel top and bottom surfaces and a height equal to the first thickness. The first thickness is a user-defined or default modeling thickness.

[0099] The top and bottom surfaces of the first pattern block have the same shape as the feature area. Because the feature area is hollowed out in the middle, the center of the etched pattern block is hollow, consistent with the physical structure of the actual chip.

[0100] The second construction module 4 is used to construct a second block of a second thickness on the reference plane with the second graphic as its base, and to place the second block on the reference plane according to the position of the second graphic within the modeling area to obtain a 3D layout model. The second block constructed on the reference plane is a structure with parallel upper and lower surfaces and a height equal to the second thickness. The second thickness is a user-defined or default modeling thickness. Since the first graphic covers the second graphic, the second block is located within the hollow area of ​​the first block. Corresponding to the physical structure of the actual chip, the second block cannot be suspended; therefore, it is placed on the reference plane within the hollow area of ​​the first block.

[0101] The 3D modeling system in this embodiment may also include the aforementioned chip board. Figure 3 Other technical features of the 3D modeling method are implemented to achieve all the method steps of the 3D modeling method in the foregoing embodiments, and have the same technical effects as the 3D modeling method in the foregoing embodiments, which will not be repeated here.

[0102] The present invention also provides a storage medium storing a computer program, the computer program being configured to execute the chip version of any of the foregoing embodiments at runtime. Figure 3 3D modeling methods.

[0103] Specifically, in this embodiment, the storage medium may include, but is not limited to, USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks, and other media capable of storing computer programs.

[0104] The present invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute a chip board according to any embodiment. Figure 3 3D modeling methods.

[0105] Specifically, the memory and processor can be connected via a data bus. Furthermore, the aforementioned electronic device may also include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0106] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0107] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for three-dimensional modeling of a chip layout, characterized by, The method comprises the following steps: determining a modeling area of a chip layout, and acquiring a first pattern and a second pattern in the modeling area on the chip layout, the first pattern covering the second pattern, the first pattern being used to define the shape of etching, and the second pattern being used to define the shape of deposition; determining a feature area where the modeling area and the first pattern do not overlap; determining a reference surface in a three-dimensional space, and constructing a first tile with a first thickness on the reference surface with the feature area as a bottom surface; constructing a second tile with a second thickness on the reference surface with the second pattern as a bottom surface, and placing the second tile on the reference surface according to the position of the second pattern in the modeling area, to obtain a three-dimensional layout model.

2. The method of claim 1, wherein, The chip layout further has a third pattern in the modeling area which does not intersect with the first pattern, the third pattern being used to define the shape of deposition, and the method further comprises: acquiring the third pattern in the modeling area on the chip layout; constructing a third tile with a third thickness on the reference surface with the third pattern as a bottom surface, and placing the third tile on the first tile according to the position of the third pattern in the modeling area.

3. The method of claim 1, wherein, The step of determining the feature area where the modeling area and the first pattern do not overlap comprises: performing a Boolean subtraction operation on the modeling area and the first pattern to obtain the feature area where the modeling area and the first pattern do not overlap.

4. The method of claim 1, wherein, The step of constructing the first tile with the first thickness on the reference surface with the feature area as a bottom surface comprises: constructing a feature bottom surface with the same shape as the feature area on the reference surface; geometrically stretching the feature bottom surface in a direction perpendicular to the reference surface according to the first thickness, to obtain the first tile.

5. The method of claim 1, wherein, The method further comprises: constructing a foundation tile with a preset thickness on the reference surface with the modeling area as a bottom surface; aligning the bottom surface of the foundation tile with the bottom surface of the first tile, and placing the first tile on the foundation tile.

6. The method of claim 5, wherein, The step of constructing the foundation tile with the preset thickness on the reference surface with the modeling area as a bottom surface comprises: constructing a foundation bottom surface with the same shape as the modeling area on the reference surface; geometrically stretching the foundation bottom surface in a direction perpendicular to the reference surface according to the preset thickness, to obtain the foundation tile.

7. The method according to any one of claims 1 to 6, characterized in that, The method further comprises: acquiring a three-dimensional coordinate parameter, the three-dimensional coordinate parameter being used to define a sectioned space; constructing a sectioned tile in the three-dimensional space according to the three-dimensional coordinate parameter; performing a Boolean subtraction operation on the three-dimensional layout model and the sectioned tile to obtain a part of the three-dimensional layout model which does not overlap with the sectioned tile.

8. A chip layout 3D modeling system, characterized in that, The method comprises the following steps: a pattern acquisition module, configured to determine a modeling area of a chip layout, and acquire a first pattern and a second pattern in the modeling area on the chip layout, the first pattern covering the second pattern, the first pattern being used to define the shape of etching, and the second pattern being used to define the shape of deposition; a pattern determination module, configured to determine a feature area where the modeling area and the first pattern do not overlap; A first constructing module is configured to determine a reference surface in a three-dimensional space, and construct a first tile with a first thickness on the reference surface with the feature region as a bottom surface; A second constructing module is configured to construct a second tile with a second thickness on the reference surface with the second pattern as a bottom surface, and place the second tile on the reference surface according to a position of the second pattern in the modeling region, to obtain a three-dimensional layout model.

9. A storage medium, characterized by The storage medium stores a computer program, and the computer program is configured to execute the chip layout three-dimensional modeling method in any one of claims 1 to 7 when running.

10. An electronic device, comprising: The chip layout three-dimensional modeling method in any one of claims 1 to 7 is executed by a processor configured to run a computer program stored in a memory.

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