Timing optimization method, device and electronic equipment

Abstract

In an embodiment of the present disclosure, a timing optimization method is provided, comprising: performing static timing analysis on the integrated circuit and obtaining a path to be processed in the integrated circuit; determining a network to be processed based on the path to be processed, wherein the network to be processed includes a network appearing on the path to be processed; isolating the load in each network to be processed, wherein the load isolation includes classifying the load in the network to be processed, wherein the classification results include critical loads and non-critical loads, and adding buffer units around the non-critical loads; and the load classification includes trying different load marking schemes, estimating the delay variation of each marking result, and selecting the best scheme to classify the loads. The processing scheme disclosed in the present disclosure can improve the efficiency of timing convergence on critical paths.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a timing optimization method based on load shielding, and more particularly to a timing optimization method, device and electronic equipment based on load shielding. Background Art

[0002] Timing is a key element in integrated circuits. Only when the timing requirements are met can the integrated circuit work properly. In the field of physical design automation of very large-scale integrated circuits, timing optimization is particularly important.

[0003] A key approach to optimizing timing characteristics is to reduce the number of fan-outs on critical paths. Traditional fan-out optimization targets high fan-out issues in circuits, such as nets with dozens, hundreds, or even more loads. Clustering algorithms typically use constraints (such as location information, capacitance and resistance on the nets) to group the loads into several groups. New buffers are then added to drive these groups, effectively reducing the fan-out. This high fan-out optimization is typically global, focusing on the nets with high fan-out in the circuit and ignoring the timing path on which the net resides. Clearly, fan-out optimization on critical paths yields higher returns than fan-out optimization on non-critical paths.

[0004] Based on this, traditional fan-out optimization methods have the problem of low timing convergence efficiency on the critical path, and a method that can efficiently optimize the circuit timing characteristics is needed. Summary of the Invention

[0005] In view of this, an embodiment of the present disclosure provides a timing optimization method based on load shielding, which at least partially solves the problems existing in the prior art.

[0006] According to one aspect of an embodiment of the present disclosure, a timing optimization method for an integrated circuit is provided, comprising:

[0007] Performing static timing analysis on the integrated circuit and obtaining a path to be processed in the integrated circuit;

[0008] Determine a line net to be processed based on the path to be processed, wherein the line net to be processed includes a line net appearing on the path to be processed;

[0009] Perform load isolation processing on the load in each of the lines to be processed, and the load isolation processing includes

[0010] The loads in the network to be processed are classified, and the classification results include critical loads and non-critical loads.

[0011] Add buffer cells around the non-critical loads.

[0012] According to a specific implementation of the embodiment of the present disclosure, the load classification processing of the load in the to-be-processed line network further includes:

[0013] Initialize the marking scheme, including obtaining the timing margins of all loads in the line network to be processed, and marking the load with the smallest timing margin as the critical load, and marking the others as non-critical loads,

[0014] estimating a delay change from the driving unit to each load in the to-be-processed network after adding the buffer unit around the non-critical load in the current marking scheme, and recording the delay change;

[0015] Updating the marking scheme, including changing the marking of the load with the smallest timing margin among the currently marked non-critical loads to a critical load, and repeating this step until all the loads in the to-be-processed line network are marked as critical loads;

[0016] The delay variations recorded in each marking scheme are compared, and buffer units are added around the non-critical load based on the buffer unit addition situation in which the delay variation is the smallest.

[0017] According to a specific implementation of the embodiment of the present disclosure, before performing load isolation processing on the load in each of the to-be-processed line networks, the method further includes:

[0018] Obtaining the number of times the line net to be processed appears on the path to be processed;

[0019] sorting the line nets to be processed based on the number of times the line nets to be processed appear on the path to be processed;

[0020] Based on the sorting result, the order of performing load isolation processing on the loads in each of the to-be-processed line networks is determined.

[0021] According to a specific implementation of the embodiment of the present disclosure, sorting the loads in the to-be-processed network includes:

[0022] Obtaining a timing margin on a path where each load in the line network to be processed is located;

[0023] The loads are sorted from small to large based on the timing margin on the path where each load is located. The smaller the timing margin of the load, the higher the ranking.

[0024] According to a specific implementation of the embodiment of the present disclosure, in estimating the current marking scheme, before adding the buffer unit around the non-critical load, the method includes:

[0025] Calculating a minimum spanning tree of the drive unit and non-critical loads of the wire network, including using the coordinates of the drive unit as the root node position and the coordinates of the non-critical load as the leaf node position, and constructing a Manhattan distance minimum spanning tree;

[0026] The Steiner point of the minimum spanning tree is used as a candidate position to determine a position for adding a buffer unit in the line network to be processed.

[0027] According to a specific implementation of the embodiment of the present disclosure, adding a buffer unit around the non-critical load further includes:

[0028] performing clustering of different numbers of non-critical loads based on coordinate positions, wherein the number of clusters is less than 4;

[0029] Compare the silhouette coefficients of different number clustering schemes, and take the scheme with the smallest silhouette coefficient as the optimal number clustering scheme.

[0030] According to a specific implementation of the embodiment of the present disclosure, the process of adding a buffer unit around a non-critical load further includes:

[0031] Traverse the addition results of different types of buffer units in the process library, including

[0032] For each attempt at a different buffer unit type, first estimate the delay change after adding the buffer unit based on the corresponding non-critical load and the location where the buffer unit needs to be placed;

[0033] A buffer unit type with the smallest delay change after the buffer unit is added is selected as the buffer unit type added around the non-critical load.

[0034] According to a specific implementation of the embodiment of the present disclosure, the load isolation processing of the load in each of the to-be-processed line networks further includes:

[0035] performing a timing update on the processed circuit;

[0036] Perform static timing analysis on the circuit after the timing update to obtain a processing result.

[0037] In a second aspect, an embodiment of the present disclosure provides a timing optimization device, including the timing optimization method according to the first aspect of the present disclosure or any implementation thereof.

[0038] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising the timing optimization method according to the first aspect of the present disclosure or any implementation thereof, or comprising the timing optimization device according to the second aspect of the present disclosure.

[0039] In an embodiment of the present disclosure, a timing optimization method is provided, comprising: performing static timing analysis on the integrated circuit and obtaining a path to be processed in the integrated circuit; determining a network to be processed based on the path to be processed, wherein the network to be processed includes a network appearing on the path to be processed; performing load isolation processing on the load in each network to be processed, wherein the load isolation processing comprises classifying the load in the network to be processed, wherein the classification results include critical loads and non-critical loads, and adding buffer units around the non-critical loads; wherein the load classification processing comprises trying different load marking schemes, estimating the delay variation of each marking result, and selecting the best scheme to classify the loads. Through the processing scheme disclosed in the present disclosure, the timing convergence efficiency on the critical path can be improved, and the timing optimization effect is more significant. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0041] Figure 1 A flowchart of a timing optimization method provided in an embodiment of the present disclosure;

[0042] Figure 2 A flowchart of another timing optimization method provided by an embodiment of the present disclosure;

[0043] Figure 3 A schematic diagram of buffer unit clustering for the timing optimization method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0045] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0046] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0047] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0048] Additionally, in the following description, specific details are provided to provide a thorough understanding of the examples. However, one skilled in the art will appreciate that the aspects described can be practiced without these specific details.

[0049] Description of some concepts:

[0050] The embodiments of the present disclosure are mainly applied to the field of very large scale integrated circuit (VLSI) physical design automation technology.

[0051] Static timing analysis: Use exhaustive analysis methods to obtain all the timing paths in the entire circuit, calculate the propagation delay of the signal on these paths, check whether the setup time and hold time of the signal meet the timing requirements, and find out the methods that violate the timing constraints by analyzing the maximum and minimum path delays.

[0052] Time margin: The actual arrival time of the data signal on the timing path minus the required arrival time of the data signal is called the time margin (Slack). A time margin of less than 0 indicates a timing violation.

[0053] Timing critical path: A collection of paths with poor timing margins among all the timing paths in a circuit. It is usually used to characterize the lower limit of the timing characteristics of the entire circuit. The timing critical path directly affects the size of the circuit's operating frequency. The smaller the timing margin value of the timing critical path, the lower the maximum frequency of the circuit.

[0054] Critical loads: All loads on a net whose timing margin value is lower than the standard timing margin.

[0055] Number of clusters: The number of newly added buffer-driven loads.

[0056] Silhouette coefficient: An indicator for evaluating clustering effectiveness, with a value range of [-1, 1]. The closer it is to 1, the better the clustering effect. The formula is as follows:

[0057]

[0058] Among them, a(i) is the average distance between i and other sample points in the cluster to which it belongs; b(i) is the minimum value of the average distance between i and samples in other clusters.

[0059] Manhattan distance minimum spanning tree: Given some points in a two-dimensional plane, the spanning tree with the shortest Manhattan distance after all points are connected is obtained.

[0060] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0061] First, refer to Figure 1 , Figure 1 A flowchart of a timing optimization method provided in an embodiment of the present disclosure includes:

[0062] Step 101 : Perform static timing analysis on the integrated circuit and obtain a path to be processed in the integrated circuit.

[0063] It is easy to understand that, compared to the traditional technology of global high fan-out optimization, the disclosed embodiment starts from the fan-out optimization of the critical path. Compared with the non-critical path, the wire nets on the critical path are usually more sensitive to the number of fan-outs. Increasing the fan-out of some wire nets may cause the timing of the entire critical path to deteriorate a lot; conversely, reducing the fan-out of the wire nets can usually significantly optimize the critical path and even achieve the effect of timing convergence. Therefore, the present embodiment starts from the critical path and performs fan-out optimization on the wire nets on the critical path, which can effectively improve the optimization efficiency of the circuit timing characteristics. In the disclosed embodiment, static timing analysis is first performed on the integrated circuit to obtain the path to be processed in the circuit. The path to be processed is the critical path that the disclosed embodiment will perform timing optimization.

[0064] Step 102 : determining a net to be processed based on the path to be processed, where the net to be processed includes the nets appearing on the path to be processed.

[0065] It can be understood that the nets appearing on the critical path can directly affect the timing characteristics of the critical path. Therefore, the nets to be processed are the nets appearing on the path to be processed.

[0066] Step 103: perform load isolation processing on the load in each line network to be processed.

[0067] All loads in the processing network are subjected to load isolation processing. In this embodiment, the load isolation processing is performed on the critical path to improve the timing characteristics. In this embodiment, the load isolation processing needs to be performed on each processing network.

[0068] The core strategy of load isolation is to keep the connection of critical loads unchanged and add new buffers to drive non-critical loads to reduce the fan-out of the line network.

[0069] Load isolation processing, that is, separating the critical loads in the critical path.

[0070] Load isolation processing includes:

[0071] Step 201 : Classify the loads in the network to be processed, and the classification results include critical loads and non-critical loads.

[0072] In this embodiment, a greedy strategy is primarily used. First, critical and non-critical loads are classified and labeled accordingly. Different embodiments have different classification criteria for critical and non-critical loads. Therefore, this embodiment does not impose any specific restrictions. It is sufficient that loads can be classified as critical and non-critical based on certain rules.

[0073] Step 202: Add buffer units around non-critical loads.

[0074] In this step, by adding buffer units around non-critical loads, that is, adding new buffer units to drive non-critical loads, the fan-out of the network can be reduced, that is, the timing optimization of the critical path corresponding to the network can be achieved.

[0075] In one embodiment, Figure 2 As shown, Figure 2 This is a flow chart of another timing optimization method provided by an embodiment of the present disclosure. As shown in the figure, before adding buffer units around non-critical loads, the method also includes:

[0076] Step 301 : Initializing a marking scheme, including obtaining the timing margins of all loads in the line network to be processed, marking the load with the smallest timing margin as a critical load, and marking the others as non-critical loads.

[0077] Step 302 : estimating the delay variation from the driving unit to each load in the to-be-processed network after adding the buffer unit around the non-critical load in the current marking scheme, and recording the delay variation.

[0078] Step 303, updating the marking scheme, including changing the marking of the load with the smallest timing margin among the currently marked non-critical loads to a critical load, and repeating this step until the marking results of all the loads in the line network to be processed are critical loads.

[0079] Step 304 : compare the delay variations recorded in each marking scheme, and add buffer units around the non-critical load based on the buffer unit addition situation where the delay variation is the smallest.

[0080] In this embodiment, it is necessary to determine the optimal solution for adding buffer units around non-critical loads. As is easy to understand, this embodiment adopts a greedy strategy. By calculating the combination of multiple critical loads and non-critical loads, the delay change after adding buffer units around different numbers of non-critical loads is calculated, and the delay change each time is recorded as the solution for each load isolation. The solution with the smallest delay change is then used as the optimal solution for load isolation. If the delay change is a negative value, that is, the circuit timing becomes worse after load isolation, it means that load isolation cannot be performed. If it is not negative, the solution with the smallest delay change is used as the optimal solution for load isolation.

[0081] In another embodiment of the present disclosure, before load isolation processing is performed on the load in each line network to be processed, the process also includes: obtaining the number of times the line network to be processed appears on the path to be processed; sorting the line networks to be processed based on the number of times the line network to be processed appears on the path to be processed; and determining the order of load isolation processing for the load in each line network to be processed based on the sorting result.

[0082] In this embodiment, step 103 requires load isolation for each pending net. In typical embodiments, pending nets must be processed in a specific order. Therefore, this embodiment specifies the order in which the pending nets are processed. As can be understood, the more frequently a net appears on a critical path, the greater its impact on critical path timing optimization. Therefore, in this embodiment, the primary factor in weighting the nets is the number of times a pending net appears on all critical paths. Next, based on the order of the sorting results, load isolation is performed on each pending net.

[0083] In one embodiment of the present disclosure, sorting the loads in the processing network includes sorting the loads from small to large based on the timing margin on the path where each load is located, and the smaller the timing margin of the load, the higher the ranking.

[0084] In this embodiment, the criterion for sorting load tags is timing margin. As is readily understood by those skilled in the art, the lower the timing margin of a load, the greater the impact of modifying its connections on the network, the more critical it is to the network, and the less room for optimization for that load. Based on this, this embodiment first obtains the timing margin for each load path in the existing network. Then, based on the timing margin for each load path, loads with smaller timing margins are ranked higher.

[0085] In one of the embodiments of the present disclosure, in estimating the current marking scheme, before adding the buffer unit around the non-critical load, it includes: calculating the minimum spanning tree of the driving unit and the non-critical load of the network, including taking the coordinates of the driving unit as the root node position and the coordinates of the non-critical load as the leaf node position, and constructing a Manhattan distance minimum spanning tree; using the Steiner point of the minimum spanning tree as a candidate position to determine the position of adding the buffer unit in the network to be processed.

[0086] In this embodiment, the loads driven by each buffer are already determined. A Manhattan distance minimum spanning tree is constructed, using the coordinates of the network's driver units as the root node and the coordinates of non-critical loads as leaf nodes. This tree ensures the overall cable length is minimized. In the Manhattan distance minimum spanning tree calculation, the buffer unit is placed at the Steiner branch point closest to the driver unit.

[0087] In one embodiment of the present disclosure, adding buffer units around non-critical loads also includes: clustering the non-critical loads into different numbers based on coordinate positions, where the number of clusters is less than 4; comparing the silhouette coefficients of different numbers of clustering schemes, and taking the scheme with the smallest silhouette coefficient as the optimal number of clustering schemes.

[0088] like Figure 3 As shown, Figure 3 A schematic diagram of buffer unit clustering for the timing optimization method provided in an embodiment of the present disclosure. In this embodiment, the optimal number of clusters is determined by evaluating the silhouette coefficient, or it can be set to a value below 4, such as 1, 2, or 3. This can largely avoid the problem of excessively dispersed loads driven by newly added single buffer units, resulting in excessive buffer unit output capacitance.

[0089] In one embodiment of the present disclosure, the process of adding buffer units around non-critical loads also includes: traversing the results of adding different types of buffer units in the process library, including attempting each different type of buffer unit, first estimating the delay change after the buffer unit is added based on the corresponding non-critical load and the location where the buffer unit needs to be placed, and selecting the buffer unit type with the smallest delay change after the buffer unit is added as the buffer unit type added around the non-critical load.

[0090] As you can understand, buffer units come in different types, and for different non-critical loads, different types of buffer units have different impacts on the latency of the non-critical load. Therefore, it is necessary to traverse the process library and compare the different buffer unit addition results, selecting the buffer unit type that corresponds to the addition result with the smallest latency change.

[0091] In another embodiment of the present disclosure, performing load isolation processing on the load in each line network to be processed further includes: performing timing update on the processed circuit; and performing static timing analysis processing on the circuit after the timing update to obtain a processing result.

[0092] It is easy to understand that in this embodiment, after load isolation processing is performed on each line network to be processed, it is also necessary to obtain the timing report of the modified netlist to verify the timing optimization results. Therefore, it is necessary to first update the timing of the processed circuit, and then perform static timing analysis processing on the subsequent integrated circuit to obtain the processing results of this time.

[0093] The above embodiments of the present disclosure have the following advantages over existing fan-out optimization technologies:

[0094] 1) Shorter runtime: Compared to high fan-out optimization with global scans, the present invention only considers critical paths and processes smaller nets, resulting in shorter runtimes.

[0095] 2) The optimization effect is more significant. The timing characteristics on the critical path are more sensitive to the number of fan-outs. In particular, nets that appear frequently on the critical path will see greater benefits after optimization, which is equivalent to optimizing multiple critical paths simultaneously.

[0096] Furthermore, as those skilled in the art will appreciate, the timing optimization method disclosed herein can be used to optimize the timing of integrated circuits or electronic devices. Electronic devices herein include, but are not limited to, intermediate products such as RF front-ends and filter amplifier modules, as well as terminal products such as mobile phones, Wi-Fi, and drones, or other communication equipment such as communication base stations and routers.

[0097] Based on the above, the present disclosure proposes the following solutions:

[0098] 1. A timing optimization method for an integrated circuit, comprising:

[0099] Performing static timing analysis on the integrated circuit and obtaining a path to be processed in the integrated circuit;

[0100] Determine a line net to be processed based on the path to be processed, wherein the line net to be processed includes a line net appearing on the path to be processed;

[0101] Perform load isolation processing on the load in each of the lines to be processed, and the load isolation processing includes

[0102] The loads in the network to be processed are classified, and the classification results include critical loads and non-critical loads.

[0103] Add buffer cells around the non-critical loads.

[0104] 2. According to the timing optimization method described in item 1, the load classification processing of the load in the line network to be processed further includes:

[0105] Initialize the marking scheme, including obtaining the timing margins of all loads in the line network to be processed, and marking the load with the smallest timing margin as the critical load, and marking the others as non-critical loads,

[0106] estimating a delay change from the driving unit to each load in the to-be-processed network after adding the buffer unit around the non-critical load in the current marking scheme, and recording the delay change;

[0107] Updating the marking scheme, including changing the marking of the load with the smallest timing margin among the currently marked non-critical loads to a critical load, and repeating this step until all the loads in the to-be-processed line network are marked as critical loads;

[0108] The delay variations recorded in each marking scheme are compared, and buffer units are added around the non-critical load based on the buffer unit addition situation in which the delay variation is the smallest.

[0109] 3. According to the timing optimization method described in item 1, before isolating the load in each of the to-be-processed line networks, the method further comprises:

[0110] Obtaining the number of times the line net to be processed appears on the path to be processed;

[0111] sorting the line nets to be processed based on the number of times the line nets to be processed appear on the path to be processed;

[0112] Based on the sorting result, the order of performing load isolation processing on the loads in each of the to-be-processed line networks is determined.

[0113] 4. According to the timing optimization method described in 2, marking the load in the line network to be processed includes:

[0114] Obtaining a timing margin on a path where each load in the line network to be processed is located;

[0115] The loads are sorted from small to large based on the timing margin on the path where each load is located. The smaller the timing margin of the load, the higher the ranking.

[0116] 5. The timing optimization method according to item 2, wherein in estimating the current marking scheme, before adding the buffer unit around the non-critical load, the method further comprises:

[0117] Calculating a minimum spanning tree of the drive unit and non-critical loads of the wire network, including using the coordinates of the drive unit as the root node position and the coordinates of the non-critical load as the leaf node position, and constructing a Manhattan distance minimum spanning tree;

[0118] The Steiner point of the minimum spanning tree is used as a candidate position to determine a position for adding a buffer unit in the line network to be processed.

[0119] 6. The timing optimization method according to item 2, wherein adding a buffer unit around a non-critical load further comprises:

[0120] performing clustering of different numbers of non-critical loads based on coordinate positions, wherein the number of clusters is less than 4;

[0121] Compare the silhouette coefficients of different number clustering schemes, and take the scheme with the smallest silhouette coefficient as the optimal number clustering scheme.

[0122] 7. The timing optimization method according to item 2, wherein the process of adding buffer units around non-critical loads further comprises:

[0123] Traverse the addition results of different types of buffer units in the process library, including

[0124] For each attempt at a different buffer unit type, first estimate the delay change after adding the buffer unit based on the corresponding non-critical load and the location where the buffer unit needs to be placed;

[0125] A buffer unit type with the smallest delay change after the buffer unit is added is selected as the buffer unit type added around the non-critical load.

[0126] 8. According to the timing optimization method described in item 1, the load isolation processing of the load in each of the to-be-processed line nets further comprises:

[0127] performing a timing update on the processed circuit;

[0128] Perform static timing analysis on the circuit after the timing update to obtain a processing result.

[0129] 9. A timing optimization device, comprising the timing optimization method according to any one of 1-8.

[0130] 10. An electronic device, comprising the timing optimization method according to any one of 1-8 or the timing optimization device according to 9.

[0131] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A timing optimization method applied to an integrated circuit, characterized in that: include: Performing static timing analysis on the integrated circuit and obtaining a path to be processed in the integrated circuit; Determine a line net to be processed based on the path to be processed, wherein the line net to be processed includes a line net appearing on the path to be processed; Perform load isolation processing on the load in each of the lines to be processed, and the load isolation processing includes The loads in the network to be processed are classified, and the classification results include critical loads and non-critical loads. Add buffer cells around the non-critical loads.

2. The timing optimization method according to claim 1, wherein: The load classification processing of the load in the to-be-processed line network further comprises: Initialize the marking scheme, including obtaining the timing margins of all loads in the line network to be processed, and marking the load with the smallest timing margin as the critical load, and marking the others as non-critical loads, estimating a delay change from the driving unit to each load in the to-be-processed network after adding the buffer unit around the non-critical load in the current marking scheme, and recording the delay change; Updating the marking scheme, including changing the marking of the load with the smallest timing margin among the currently marked non-critical loads to a critical load, and repeating this step until all the loads in the to-be-processed line network are marked as critical loads; The delay variations recorded in each marking scheme are compared, and buffer units are added around the non-critical load based on the buffer unit addition situation in which the delay variation is the smallest.

3. The timing optimization method according to claim 1, wherein: Before performing load isolation processing on the load in each of the to-be-processed lines, the method further includes: Obtaining the number of times the line net to be processed appears on the path to be processed; sorting the line nets to be processed based on the number of times the line nets to be processed appear on the path to be processed; Based on the sorting result, the order of performing load isolation processing on the loads in each of the to-be-processed line networks is determined.

4. The timing optimization method according to claim 2, wherein: The sorting of the loads in the to-be-processed network includes: Obtaining a timing margin on a path where each load in the line network to be processed is located; The loads are sorted from small to large based on the timing margin on the path where each load is located. The smaller the timing margin of the load, the higher the ranking.

5. The timing optimization method according to claim 2, wherein: The step of estimating the current marking scheme, before adding the buffer unit around the non-critical load, includes: Calculating a minimum spanning tree of the drive unit and non-critical loads of the wire network, including using the coordinates of the drive unit as the root node position and the coordinates of the non-critical load as the leaf node position, and constructing a Manhattan distance minimum spanning tree; The Steiner point of the minimum spanning tree is used as a candidate position to determine a position for adding a buffer unit in the line network to be processed.

6. The timing optimization method according to claim 2, wherein: The adding of buffer units around non-critical loads further includes: performing clustering of different numbers of non-critical loads based on coordinate positions, wherein the number of clusters is less than 4; Compare the silhouette coefficients of different number clustering schemes, and take the scheme with the smallest silhouette coefficient as the optimal number clustering scheme.

7. The timing optimization method according to claim 2, wherein: The process of adding a buffer unit around the non-critical load also includes: Traverse the addition results of different types of buffer units in the process library, including For each attempt at a different buffer unit type, first estimate the delay change after adding the buffer unit based on the corresponding non-critical load and the location where the buffer unit needs to be placed; A buffer unit type with the smallest delay change after the buffer unit is added is selected as the buffer unit type added around the non-critical load.

8. The timing optimization method according to claim 1, wherein: The load isolation processing of the load in each of the to-be-processed lines further comprises: performing a timing update on the processed circuit; Perform static timing analysis on the circuit after the timing update to obtain a processing result.

9. A timing optimization device, characterized in that: The method comprises the timing optimization method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The method comprises the timing optimization method according to any one of claims 1 to 8 or the timing optimization device according to claim 9.

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