An incremental static timing analysis method based on artificial intelligence

Abstract

The present invention proposes an artificial intelligence-based incremental static timing analysis method suitable for analyzing circuit delays during the ECO phase of confirmation in digital circuit design. The method extracts circuit device characteristic data related to the timing data based on circuit timing data from the original design confirmation phase without ECO. A delay prediction model is constructed based on a neural network and trained using the circuit device characteristic data to obtain model parameters. The circuit device characteristic data of the incremental design after ECO is extracted and input into the trained delay prediction model to obtain circuit delay data of the incremental design structure, as well as corresponding delay data and gain data. The delay data and gain data are then fed back to the placer and router. This method ensures static timing prediction accuracy while solving the problem of incremental design results failing to meet timing closure requirements.

Description

Technical Field

[0001] The present invention belongs to the technical field of incremental static timing analysis, and in particular relates to an incremental static timing analysis method based on artificial intelligence. Background Art

[0002] In digital circuit design, designers often encounter situations where, after back-end design has begun or even tape-out has been completed, specifications change or bugs are discovered, requiring design changes. This is known as the Error Correction Operation (ECO) phase in digital circuit design.

[0003] Static timing analysis (STA) is a key technology in the integrated circuit design verification process. Its purpose is to systematically evaluate the timing performance of a circuit to ensure that the design meets predetermined timing constraints. STA predicts the circuit's timing behavior under different operating conditions by analyzing the circuit's logical structure and clock architecture. STA results are important for guiding subsequent design optimization, improving circuit timing stability, and reducing the number of design iterations. In the physical implementation phase of incremental design, the placement and routing processes are crucial steps. Together, they ensure the optimization of the circuit design's geometry and electrical performance. To ensure that the circuit's timing meets constraints, STA estimation is required during the placement and routing process. STA can predict circuit performance after ECO, facilitating optimization of the layout and routing process to ensure that the revised design meets the expected performance standards and timing requirements.

[0004] However, existing STA tools are complex to implement, requiring the extraction of resistance and capacitance information for the entire circuit based on the circuit's topology and physical implementation. High-precision STA tools are typically used only during the sign-off phase. The STA algorithms used during the layout and routing phase are typically less accurate for efficiency reasons, and the development of sign-off STA tools is complex. However, in incremental design, since delay information from the previous version under the same process conditions is already available, we can leverage this information and employ artificial intelligence (AI) methods to avoid extracting the entire circuit's resistance and capacitance information. This significantly simplifies implementation complexity while still achieving comparable sign-off accuracy.

[0005] Traditional delay prediction models are either insufficiently accurate or extremely slow. This results in traditional incremental design flows relying on low-precision delay prediction models almost exclusively, except for the final Timing ECO step. This makes final timing closure extremely difficult and requires extensive manual intervention. Once the number of logic cells added to the incremental design exceeds a certain threshold, the backend becomes nearly unable to meet timing closure. Therefore, given the characteristics of the incremental design flow, a delay prediction technology is urgently needed that can guarantee sufficient accuracy while running quickly and within a reasonable timeframe. This technology can address the fundamental issue of incremental design results failing to meet timing closure.

[0006] Therefore, in order to solve the defects of the existing STA calculation method, the present invention proposes an incremental static timing analysis method based on artificial intelligence. Summary of the Invention

[0007] The present invention provides an artificial intelligence-based incremental static timing analysis method, which aims to use a neural network to construct a delay prediction model, which is applied to the analysis of circuit delay in the ECO confirmation stage of digital circuit design, and solves the fundamental problem that incremental design results are difficult to meet timing convergence.

[0008] The scheme of the present invention is as follows:

[0009] An artificial intelligence-based incremental static timing analysis method, the method comprising the following steps:

[0010] Step S1 : extracting circuit device characteristic data related to the timing data based on the circuit timing data that has not been ECOed in the original design confirmation stage.

[0011] The circuit device characteristic data related to the timing data at least includes: the topological structure of the circuit, the physical characteristics of the circuit devices and the link relationship.

[0012] The method for extracting circuit device characteristic data related to timing data includes: parsing circuit timing data that has not been ECOed in the original design confirmation stage to extract the circuit topology; extracting physical characteristics of circuit devices, wherein the physical characteristics include at least type, size, resistance, capacitance, and area; extracting link relationships between circuit devices, wherein the link relationships include at least connected nodes, path length, and connection type; and standardizing the extracted characteristic data to obtain circuit device characteristic data.

[0013] Step S2: constructing a delay prediction model based on a neural network, and training the delay prediction model using circuit device characteristic data to obtain model parameters.

[0014] The neural network is a heterogeneous graph neural network, which uses supervised learning for model training. The supervised labels required for model training are derived from the time series data obtained by the original design using commercial tools. The graph structure in the heterogeneous graph neural network is constructed as follows:

[0015] Each device in the circuit, including standard cells and macro cells, is mapped as a node in the graph, and the node attributes contain the physical characteristics of the device; the physical connection relationship between devices is mapped as an edge in the graph, and the edge attributes include the connection type and path length link characteristics; the connections between different types of device nodes constitute a heterogeneous graph structure.

[0016] The neural network includes: an input layer, a graph convolution layer, a feature aggregation layer, a fully connected layer and an output layer;

[0017] Furthermore, the input layer receives input features of circuit nodes and initializes the input features to node features, wherein the input features are circuit device feature data; the initialization is expressed as: ,in, Representation node The initial characteristics of Representation node Node features.

[0018] Furthermore, the graph convolution layer uses heterogeneous graph convolution operations to aggregate and update different types of node features. The function formula of the graph convolution layer is:

[0019]

[0020] in, Representation node In the Layer characteristics, Representation node The set of neighbor nodes of is the normalization coefficient, and It is The weight matrix of the layer, ReLU is the activation function of the graph convolution layer.

[0021] Furthermore, the feature aggregation layer aggregates the features of each node to generate a new node feature representation. The function formula of the feature aggregation layer is:

[0022]

[0023] in, Representation node In the last layer of features, Represents a feature aggregation function.

[0024] Furthermore, the fully connected layer inputs the aggregated node features into the fully connected layer for feature transformation and nonlinear transformation. The function formula of the fully connected layer is:

[0025]

[0026] in, Representation node The output delay prediction value of and are the weights and biases of the fully connected layer, is the activation function of the fully connected layer.

[0027] The output layer outputs the predicted delay value of the node .

[0028] Step S3: extracting characteristic data of the circuit components of the incremental design after ECO, inputting the trained delay prediction model, and obtaining circuit delay data of the incremental design structure and corresponding delay data and gain data.

[0029] Step S4: sending the delay data and gain data back to the placer and router.

[0030] Furthermore, the training process of the neural network includes the following steps:

[0031] Step S21, initializing the weight parameters of the neural network.

[0032] Step S22: batch process the circuit device characteristic data and input it into the neural network.

[0033] Step S23: Calculate the delay prediction value of each node through forward propagation .

[0034] Step S24: Calculate the predicted value and the actual delay data The loss function formula between is: , where n is the total number of nodes.

[0035] Step S25, updating the weight parameters of the neural network through the back propagation algorithm to minimize the loss function.

[0036] Step S26: Repeat the above steps until the loss function converges.

[0037] Furthermore, the aggregation function Aggregate of the feature aggregation layer adopts weighted average aggregation, and the formula is:

[0038]

[0039] in, is a node For Node The influence weight of .

[0040] Furthermore, the fully connected layer of the neural network adopts a multi-layer perceptron MLP structure, which includes multiple hidden layers, each of which adopts The activation function performs nonlinear transformation:

[0041]

[0042] in, Indicates the The node characteristics of the layer, and They are The weight matrix and bias vector of the layer.

[0043] Furthermore, the graph convolution layer of the neural network uses a multi-head attention mechanism for feature aggregation:

[0044]

[0045] Where m is the number of attention heads, It is The attention weight of each attention head, It is Tier The weight matrix of the attention head.

[0046] Furthermore, the method further includes the steps of verifying and optimizing the circuit delay data of the incremental design: using the trained delay prediction model to make a preliminary delay prediction for the incremental design; performing error analysis on the prediction results, and calculating the error between the predicted value and the actual value. : ,If the error is greater than the preset threshold, the model parameters are fine-tuned until the error is no greater than the preset threshold.

[0047] Compared with the prior art, the present invention has the following beneficial effects:

[0048] By constructing a neural network-based delay prediction model, the present invention can quickly and accurately predict the circuit delay data after ECO. Compared with traditional timing analysis methods, this method significantly reduces computing time and resource consumption while maintaining a high prediction accuracy.

[0049] This method is particularly suitable for incremental design scenarios, that is, making local modifications based on the original design. It can quickly respond to design changes after ECO and re-evaluate the circuit's delay performance, thereby accelerating the design iteration and optimization process, while solving the problem that incremental design results are difficult to meet timing convergence. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 This is a flow chart of an incremental static timing analysis method based on artificial intelligence of the present invention. DETAILED DESCRIPTION

[0051] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention are described clearly and completely below. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0052] It should be noted that in digital circuit design, when designers revise and upgrade the design or correct bugs, if they start from scratch as a completely new design and go through all the stages such as logic synthesis, testability design, low-power design, layout and routing, and layout design again, it will take a long design cycle. However, if designers make full use of the design and implementation completed in the previous version, make a small amount of changes in the implementation of the previous version, and ensure that the changed implementation is completely consistent with the functions of the new spec, the designer's efficiency can be greatly improved. We call this stage incremental digital circuit design.

[0053] like Figure 1 FIG. 1 is a flow chart of an incremental static timing analysis method based on artificial intelligence according to the present invention, wherein the method comprises the following steps:

[0054] Step S1 : extracting circuit device characteristic data related to the timing data based on the circuit timing data that has not been ECOed in the original design confirmation stage.

[0055] The circuit device characteristic data related to the timing data at least includes: the topological structure of the circuit, the physical characteristics of the circuit devices and the link relationship.

[0056] The method for extracting circuit device characteristic data related to timing data includes: parsing circuit timing data that has not been ECOed in the original design confirmation stage to extract the circuit topology; extracting physical characteristics of circuit devices, wherein the physical characteristics include at least type, size, resistance, capacitance, and area; extracting link relationships between circuit devices, wherein the link relationships include at least connected nodes, path length, and connection type; and standardizing the extracted characteristic data to obtain circuit device characteristic data.

[0057] Step S2: constructing a delay prediction model based on a neural network, and training the delay prediction model using circuit device characteristic data to obtain model parameters.

[0058] During the training phase, the estimated timing data from the sign-off phase of the original design is used to extract timing-related circuit device features. Combined with the circuit topology, machine learning methods are used to model the circuit's delay. The neural network is a heterogeneous graph neural network, trained using supervised learning. The supervisory labels required for model training are derived from the timing data of the original design obtained using commercial tools. The graph structure in the heterogeneous graph neural network is constructed as follows:

[0059] Each device in the circuit, including standard cells and macro cells, is mapped as a node in the graph. The node attributes include the device type, size, resistance, capacitance, and area physical characteristics. The physical connection relationship between devices is mapped as an edge in the graph. The edge attributes include the connection type and path length link characteristics. The connections between different types of device nodes constitute a heterogeneous graph structure.

[0060] When building a neural network model, you first need to map the physical circuit structure into a graph structure. The specific mapping method is:

[0061] Node mapping: Map standard units in the circuit (such as various logic gates, triggers, etc.) to one type of node in the graph, and map macro units (such as memory, IP cores, etc.) to another type of node in the graph. The attributes contained in the nodes include: device type, size, resistance, capacitance, area and other physical characteristics.

[0062] Edge mapping: Map the physical connections between devices to edges in the graph. The attributes of the edges include: connection type (such as metal layer connection, direct connection, etc.), path length, line width and other characteristics.

[0063] Heterogeneous graph construction: Since the circuit contains different types of device nodes, the connections between them constitute a heterogeneous graph structure. Different weight matrices are used for message passing and feature aggregation between different types of nodes.

[0064] The neural network includes: an input layer, a graph convolution layer, a feature aggregation layer, a fully connected layer and an output layer;

[0065] The input layer receives input features of circuit nodes and initializes the input features to node features, wherein the input features are circuit device feature data; the initialization is expressed as: ,in, Representation node The initial characteristics of Representation node Node features.

[0066] The graph convolution layer uses heterogeneous graph convolution operations to aggregate and update different types of node features. The function formula of the graph convolution layer is:

[0067]

[0068] in, Representation node In the Layer characteristics, Representation node The set of neighbor nodes of is the normalization coefficient, and It is The weight matrix of the layer, ReLU is the activation function of the graph convolution layer.

[0069] The feature aggregation layer aggregates the features of each node to generate a new node feature representation. The function formula of the feature aggregation layer is:

[0070]

[0071] in, Representation node In the last layer of features, Represents a feature aggregation function.

[0072] The fully connected layer inputs the aggregated node features into the fully connected layer for feature transformation and nonlinear transformation. The function formula of the fully connected layer is:

[0073]

[0074] in, Representation node The output delay prediction value of and are the weights and biases of the fully connected layer, is the activation function of the fully connected layer.

[0075] The output layer outputs the predicted delay value of the node .

[0076] Step S3: extracting characteristic data of the circuit components of the incremental design after ECO, inputting the trained delay prediction model, and obtaining circuit delay data of the incremental design structure and corresponding delay data and gain data.

[0077] Step S4: sending the delay data and gain data back to the placer and router.

[0078] It should be noted that the training process of the neural network includes the following steps:

[0079] Step S21, initializing the weight parameters of the neural network.

[0080] Step S22: batch process the circuit device characteristic data and input it into the neural network.

[0081] Step S23: Calculate the delay prediction value of each node through forward propagation ,The real delay data comes from the timing data obtained by ,static timing analysis of the original design using commercial tools;

[0082] Step S24: Calculate the predicted value and the actual delay data The loss function formula between is: , where n is the total number of nodes.

[0083] Step S25, updating the weight parameters of the neural network through the back propagation algorithm to minimize the loss function.

[0084] Step S26: Repeat the above steps until the loss function converges.

[0085] For example, consider a digital circuit design containing multiple types of logic gates (such as AND, OR, NOT) and interconnects. An ECO (Evolutionary Design) modification (ECO) based on the original design is required, meaning that part of the circuit structure is modified to improve performance or fix errors. The original design contains 10 logic gates and 20 interconnects. The logic gates have different physical characteristics, such as type, size, resistance, capacitance, and area, and the interconnects have different path lengths and connection types (such as direct connection and cross-connection). After the ECO modification, due to specification changes or the discovery of design flaws, the circuit's functionality needs to be revised. Therefore, new logic units and corresponding interconnects are added to the original design to meet the new functional requirements. At this point, extract the characteristic data of the circuit devices of the original design, analyze the circuit timing data, and extract key information from the timing simulation results of the original design; extract the topological structure, determine the connection relationship between the logic gates, and form a topological diagram; extract the physical characteristics, and record the type, size, resistance, capacitance, and area of ​​each logic gate; extract the link relationship, and record the connected nodes, path length, and connection type of each connecting line; standardize all extracted characteristic data for use in neural network training, calculate the difference between the predicted value and the actual delay data, and update the weight parameters of the neural network according to the gradient of the loss function until the loss function converges or the preset training rounds are reached.

[0086] During the training phase, the timing estimation in the sign-off phase of the original design is fully utilized as training labels, the features of the circuit components related to timing are extracted, and the circuit topology is combined with a supervised learning method to model the circuit delay through a heterogeneous graph neural network.

[0087] Extract the circuit characteristic data after ECO and input it into the trained delay prediction model. The model outputs the delay prediction value of each node as well as the overall delay data and gain data, and transmits the data back to the placer and router. Engineers analyze the predicted delay data and gain data, evaluate the effect of ECO, and adjust the layout and routing strategies based on the prediction results to further optimize circuit performance. If the ECO effect is not ideal, the ECO design can be re-performed and the above steps can be repeated for verification and optimization.

[0088] For the neural network model, the aggregation function Aggregate of the feature aggregation layer adopts weighted average aggregation, and the formula is:

[0089]

[0090] in, is a node For Node The influence weight of .

[0091] The fully connected layer of the neural network adopts a multi-layer perceptron MLP structure, which includes multiple hidden layers. The activation function performs nonlinear transformation:

[0092]

[0093] in, Indicates the The node characteristics of the layer, and They are The weight matrix and bias vector of the layer.

[0094] The graph convolution layer of the neural network uses a multi-head attention mechanism for feature aggregation:

[0095]

[0096] Where m is the number of attention heads, It is The attention weight of each attention head, It is Tier The weight matrix of the attention head.

[0097] The method further includes the steps of verifying and optimizing the circuit delay data of the incremental design: performing preliminary delay prediction on the incremental design using the trained delay prediction model; performing error analysis on the prediction results, and calculating the error between the predicted value and the actual value. : ,If the error is greater than the preset threshold, the model parameters are fine-tuned until the error is no greater than the preset threshold.

[0098] It should be noted that those skilled in the art will appreciate that various modifications and equivalent substitutions may be made to the present invention without departing from the scope of the present invention. Furthermore, various modifications may be made to the present invention for specific circumstances or materials without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed, but rather includes all embodiments falling within the scope of the claims of the present invention.

Claims

1. An artificial intelligence-based incremental static timing analysis method suitable for analyzing circuit delay in the physical implementation phase ECO of incremental design in digital circuit design, characterized by: The method comprises the following steps: Step S1, extracting circuit device characteristic data related to the timing data based on the circuit timing data that has not been ECOed in the original design confirmation stage; Analyze the circuit timing data that was not ECOed during the original design confirmation phase to extract the circuit topology; extract the physical characteristics of the circuit components, which include at least type, size, resistance, capacitance, and area; extract the link relationships between the circuit components, which include at least connected nodes, path length, and connection type; and standardize the extracted feature data to obtain circuit component feature data. Step S2, constructing a delay prediction model based on a neural network, and training the delay prediction model using circuit device characteristic data to obtain model parameters; The neural network is a heterogeneous graph neural network, which uses supervised learning for model training. The supervised labels are derived from the time series data obtained by the original design using commercial tools. The graph structure in the heterogeneous graph neural network is constructed as follows: Each device in the circuit, including standard cells and macro cells, is mapped to a node in the graph. The node attributes include the physical characteristics of the device. The physical connection relationship between devices is mapped to an edge in the graph. The edge attributes include the connection type and path length link characteristics. The connections between different types of device nodes form a heterogeneous graph structure. The neural network includes: input layer, graph convolution layer, feature aggregation layer, fully connected layer and output layer; The input layer receives input features of circuit nodes and initializes the input features to node features, where the input features are circuit device feature data; the initialization is expressed as: ,in, Representation node The initial characteristics of Representation node Node characteristics; The graph convolution layer uses heterogeneous graph convolution operations to aggregate and update different types of node features. The function formula of the graph convolution layer is: in, Representation node In the Layer characteristics, Representation node The set of neighbor nodes of is the normalization coefficient, and It is The weight matrix of the layer, ReLU is the activation function of the graph convolution layer; The feature aggregation layer aggregates the features of each node to generate a new node feature representation. The function formula of the feature aggregation layer is: in, Representation node In the last layer of features, Represents feature aggregation function; The fully connected layer inputs the aggregated node features into the fully connected layer for feature transformation and nonlinear transformation. The function formula of the fully connected layer is: in, Representation node The output delay prediction value of and are the weights and biases of the fully connected layer, is the activation function of the fully connected layer; The output layer outputs the predicted delay value of the node ; Step S3, extracting characteristic data of the circuit components of the incremental design after ECO, inputting the trained delay prediction model, and obtaining circuit delay data of the incremental design structure and corresponding delay data and gain data; Step S4: sending the delay data and gain data back to the placer and router.

2. The artificial intelligence-based incremental static timing analysis method according to claim 1, characterized in that: The circuit device characteristic data related to the timing data at least includes: the topological structure of the circuit, the physical characteristics of the circuit devices and the link relationship.

3. The artificial intelligence-based incremental static timing analysis method according to claim 2, characterized in that: The training process of the neural network includes the following steps: Step S21, initializing the weight parameters of the neural network; Step S22, batch processing the circuit device characteristic data and inputting it into the neural network; Step S23: Calculate the delay prediction value of each node through forward propagation ; Step S24: Calculate the predicted value and the actual delay data The loss function formula between is: , where n is the total number of nodes; Step S25, updating the weight parameters of the neural network through the back propagation algorithm to minimize the loss function; Step S26: Repeat the above steps until the loss function converges.

4. The artificial intelligence-based incremental static timing analysis method according to claim 3, characterized in that: The aggregation function Aggregate of the feature aggregation layer adopts weighted average aggregation, and the formula is: in, is a node For Node The influence weight of .

5. The artificial intelligence-based incremental static timing analysis method according to claim 4, characterized in that: The fully connected layer of the neural network adopts a multi-layer perceptron MLP structure, which includes multiple hidden layers. The activation function performs nonlinear transformation: in, Indicates the The node characteristics of the layer, and They are The weight matrix and bias vector of the layer.

6. The artificial intelligence-based incremental static timing analysis method according to claim 5, characterized in that: The graph convolution layer of the neural network uses a multi-head attention mechanism for feature aggregation: Where m is the number of attention heads, It is The attention weight of each attention head, It is Tier The weight matrix of the attention head.

7. The artificial intelligence-based incremental static timing analysis method according to claim 6, characterized in that: The method further includes the steps of verifying and optimizing the circuit delay data of the incremental design: performing preliminary delay prediction on the incremental design using the trained delay prediction model; performing error analysis on the prediction results, and calculating the error between the predicted value and the actual value. : ,If the error is greater than the preset threshold, the model parameters are fine-tuned until the error is no greater than the preset threshold.

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